---------- Begin Simulation Statistics ---------- sim_seconds 2.629695 # Number of seconds simulated sim_ticks 2629694709500 # Number of ticks simulated final_tick 2629694709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 422902 # Simulator instruction rate (inst/s) host_op_rate 538135 # Simulator op (including micro ops) rate (op/s) host_tick_rate 18468797106 # Simulator tick rate (ticks/s) host_mem_usage 466428 # Number of bytes of host memory used host_seconds 142.39 # Real time elapsed on the host sim_insts 60215255 # Number of instructions simulated sim_ops 76622777 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 291720 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4684888 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 412356 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 4375828 # Number of bytes read from this memory system.physmem.bytes_read::total 134021240 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 291720 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 412356 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 704076 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3689664 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1522876 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 1493404 # Number of bytes written to this memory system.physmem.bytes_written::total 6705944 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 10770 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 73237 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 6459 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 68407 # Number of read requests responded to by this memory system.physmem.num_reads::total 15690908 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57651 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 380719 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 373351 # Number of write requests responded to by this memory system.physmem.num_writes::total 811721 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47251210 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 110933 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1781533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 156808 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 1664006 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 50964562 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 110933 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 156808 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 267741 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1403077 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 579108 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 567900 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2550085 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1403077 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47251210 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 110933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 2360641 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 156808 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 2231906 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 53514647 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15690908 # Number of read requests accepted system.physmem.writeReqs 811721 # Number of write requests accepted system.physmem.readBursts 15690908 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 811721 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 1004216192 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1920 # Total number of bytes read from write queue system.physmem.bytesWritten 6737024 # Total number of bytes written to DRAM system.physmem.bytesReadSys 134021240 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6705944 # Total written bytes from the system interface side system.physmem.servicedByWrQ 30 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 706455 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980391 # Per bank write bursts system.physmem.perBankRdBursts::1 980206 # Per bank write bursts system.physmem.perBankRdBursts::2 980218 # Per bank write bursts system.physmem.perBankRdBursts::3 980431 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts system.physmem.perBankRdBursts::5 980708 # Per bank write bursts system.physmem.perBankRdBursts::6 980610 # Per bank write bursts system.physmem.perBankRdBursts::7 980421 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts system.physmem.perBankRdBursts::11 979558 # Per bank write bursts system.physmem.perBankRdBursts::12 980154 # Per bank write bursts system.physmem.perBankRdBursts::13 980093 # Per bank write bursts system.physmem.perBankRdBursts::14 980167 # Per bank write bursts system.physmem.perBankRdBursts::15 980110 # Per bank write bursts system.physmem.perBankWrBursts::0 6645 # Per bank write bursts system.physmem.perBankWrBursts::1 6506 # Per bank write bursts system.physmem.perBankWrBursts::2 6513 # Per bank write bursts system.physmem.perBankWrBursts::3 6561 # Per bank write bursts system.physmem.perBankWrBursts::4 6643 # Per bank write bursts system.physmem.perBankWrBursts::5 6949 # Per bank write bursts system.physmem.perBankWrBursts::6 6933 # Per bank write bursts system.physmem.perBankWrBursts::7 6786 # Per bank write bursts system.physmem.perBankWrBursts::8 6904 # Per bank write bursts system.physmem.perBankWrBursts::9 6725 # Per bank write bursts system.physmem.perBankWrBursts::10 6221 # Per bank write bursts system.physmem.perBankWrBursts::11 6029 # Per bank write bursts system.physmem.perBankWrBursts::12 6513 # Per bank write bursts system.physmem.perBankWrBursts::13 6297 # Per bank write bursts system.physmem.perBankWrBursts::14 6516 # Per bank write bursts system.physmem.perBankWrBursts::15 6525 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 2629690290000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6718 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 152158 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 57651 # Write request sizes (log2) system.physmem.rdQLenPdf::0 1128915 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 971082 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 971066 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 973046 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 971647 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 972454 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2865167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2865325 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 3808659 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 25323 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 23577 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 23920 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 23318 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 22983 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 22230 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 22150 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 362 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 357 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 351 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 346 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 344 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 342 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 333 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 330 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 328 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 324 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 322 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 320 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 312 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2639 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2695 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3184 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4405 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4394 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4400 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4357 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5258 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4449 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4419 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5254 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4320 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4276 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 4193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 1201 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1181 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1179 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1168 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1166 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 1165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1166 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 1163 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 1163 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 1157 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1152 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 1147 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 1146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 1145 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 990183 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 1014.719065 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 1002.794597 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 86.877825 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 3622 0.37% 0.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 3291 0.33% 0.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 1715 0.17% 0.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 1178 0.12% 0.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 920 0.09% 1.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 703 0.07% 1.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 532 0.05% 1.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 420 0.04% 1.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 977802 98.75% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 990183 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4537 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 3458.425832 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 54557.622307 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-65535 4511 99.43% 99.43% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::131072-196607 8 0.18% 99.60% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 4 0.09% 99.69% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 2 0.04% 99.74% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 3 0.07% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.82% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.13% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4537 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4537 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 23.201675 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 21.361663 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 9.873768 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::1 5 0.11% 0.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::2 7 0.15% 0.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::3 5 0.11% 0.37% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::4 2 0.04% 0.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::5 2 0.04% 0.46% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::6 4 0.09% 0.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::7 6 0.13% 0.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8 3 0.07% 0.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::9 3 0.07% 0.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::10 3 0.07% 0.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::11 3 0.07% 0.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12 2 0.04% 0.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::13 4 0.09% 1.08% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::14 7 0.15% 1.23% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::15 17 0.37% 1.61% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 1491 32.86% 34.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 339 7.47% 41.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 208 4.58% 46.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1050 23.14% 69.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 16 0.35% 70.02% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 12 0.26% 70.29% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 20 0.44% 70.73% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 24 0.53% 71.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 18 0.40% 71.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 14 0.31% 71.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 18 0.40% 72.36% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 18 0.40% 72.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 19 0.42% 73.18% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 13 0.29% 73.46% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 11 0.24% 73.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 12 0.26% 73.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 11 0.24% 74.21% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::33 3 0.07% 74.28% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 2 0.04% 74.32% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36 1 0.02% 74.34% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::39 1015 22.37% 96.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40 76 1.68% 98.39% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::41 13 0.29% 98.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::42 42 0.93% 99.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::47 1 0.02% 99.63% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::49 5 0.11% 99.74% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::50 5 0.11% 99.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::51 5 0.11% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::53 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4537 # Writes before turning the bus around for reads system.physmem.totQLat 592300556750 # Total ticks spent queuing system.physmem.totMemAccLat 700300341750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 78454390000 # Total ticks spent in databus transfers system.physmem.totBankLat 29545395000 # Total ticks spent accessing banks system.physmem.avgQLat 37748.08 # Average queueing delay per DRAM burst system.physmem.avgBankLat 1882.97 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 44631.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 7.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 14.89 # Average write queue length when enqueuing system.physmem.readRowHits 14676487 # Number of row buffer hits during reads system.physmem.writeRowHits 89750 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.26 # Row buffer hit rate for writes system.physmem.avgGap 159349.78 # Average gap between requests system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 4.16 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 54426652 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16743677 # Transaction distribution system.membus.trans_dist::ReadResp 16743677 # Transaction distribution system.membus.trans_dist::WriteReq 763441 # Transaction distribution system.membus.trans_dist::WriteResp 763441 # Transaction distribution system.membus.trans_dist::Writeback 57651 # Transaction distribution system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution system.membus.trans_dist::ReadExReq 131342 # Transaction distribution system.membus.trans_dist::ReadExResp 131342 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892577 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 4279541 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 35343605 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16470928 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 18869222 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 143125478 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 143125478 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1225762000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3755500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 18171181500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 4987933108 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 38819144750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62041 # number of replacements system.l2c.tags.tagsinuse 51600.507824 # Cycle average of tags in use system.l2c.tags.total_refs 1699332 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 127423 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 13.336148 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 2574803290500 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 38204.625202 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 2677.995545 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 3048.557344 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 4342.999627 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 3326.329216 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.582956 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.040863 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.046517 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.066269 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.050756 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.787361 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65382 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 6447 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 56751 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.997650 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 17277037 # Number of tag accesses system.l2c.tags.data_accesses 17277037 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 9996 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3617 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 411271 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 183421 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 9883 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 3502 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 433200 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 187065 # number of ReadReq hits system.l2c.ReadReq_hits::total 1241955 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 596489 # number of Writeback hits system.l2c.Writeback_hits::total 596489 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 55903 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 58636 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 114539 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 9996 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3617 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 411271 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 239324 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 9883 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 3502 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 433200 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 245701 # number of demand (read+write) hits system.l2c.demand_hits::total 1356494 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 9996 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3617 # number of overall hits system.l2c.overall_hits::cpu0.inst 411271 # number of overall hits system.l2c.overall_hits::cpu0.data 239324 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 9883 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 3502 # number of overall hits system.l2c.overall_hits::cpu1.inst 433200 # number of overall hits system.l2c.overall_hits::cpu1.data 245701 # number of overall hits system.l2c.overall_hits::total 1356494 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 4144 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 5204 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 6442 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5023 # number of ReadReq misses system.l2c.ReadReq_misses::total 20816 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1406 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2883 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 68791 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 64185 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 4144 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 73995 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 6442 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 69208 # number of demand (read+write) misses system.l2c.demand_misses::total 153792 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.inst 4144 # number of overall misses system.l2c.overall_misses::cpu0.data 73995 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 6442 # number of overall misses system.l2c.overall_misses::cpu1.data 69208 # number of overall misses system.l2c.overall_misses::total 153792 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 292011000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 389009500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 455480250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 379549000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 1516288500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 256489 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 208991 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 4825847704 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 4517645162 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 9343492866 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 292011000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 5214857204 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 455480250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 4897194162 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 10859781366 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 292011000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 5214857204 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 455480250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 4897194162 # number of overall miss cycles system.l2c.overall_miss_latency::total 10859781366 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 9996 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3619 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 415415 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 188625 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 9884 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 3502 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 439642 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 192088 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1262771 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 596489 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 596489 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1420 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1489 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2909 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 124694 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 122821 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247515 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 9996 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3619 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 415415 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 313319 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 9884 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 3502 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 439642 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 314909 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1510286 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 9996 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3619 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 415415 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 313319 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 9884 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 3502 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 439642 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 314909 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1510286 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000553 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.009976 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.027589 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014653 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.026149 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.016484 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990141 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991941 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991062 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.551679 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.522590 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.537244 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000553 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.009976 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.236165 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014653 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.219771 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.101830 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000553 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.009976 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.236165 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014653 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.219771 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.101830 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70465.974903 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 74752.017679 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70704.788885 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 75562.213816 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 72842.452921 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 182.424609 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 141.496953 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 161.456816 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70152.312134 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70384.749739 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 70264.505369 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 70465.974903 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 70475.805176 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 70704.788885 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 70760.521356 # average overall miss latency system.l2c.demand_avg_miss_latency::total 70613.434808 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 70465.974903 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 70475.805176 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 70704.788885 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 70760.521356 # average overall miss latency system.l2c.overall_avg_miss_latency::total 70613.434808 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 57651 # number of writebacks system.l2c.writebacks::total 57651 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.inst 4144 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 5204 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 6442 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 5023 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 20816 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 1406 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 1477 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 2883 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 68791 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 64185 # 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number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 6442 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 69208 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 153792 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 239540000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 324214500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 373802250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 316907500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 1254665500 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14061406 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14772477 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 28833883 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3946484796 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3696331838 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 7642816634 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 239540000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 4270699296 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 373802250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 4013239338 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 8897482134 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 239540000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 4270699296 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 373802250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 4013239338 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 8897482134 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 351469750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 82683235750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 856250 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 84002858250 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 167038420000 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8408462374 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8295509001 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 16703971375 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 351469750 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91091698124 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 856250 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92298367251 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 183742391375 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000553 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009976 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027589 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014653 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026149 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.016484 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990141 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991941 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.991062 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551679 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.522590 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.537244 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000553 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009976 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.236165 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014653 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.219771 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.101830 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000553 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009976 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.236165 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014653 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.219771 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.101830 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57804.054054 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62301.018447 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63091.280111 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 60274.092045 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.677048 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.346861 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57369.202308 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57588.717582 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 57475.158179 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57804.054054 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57716.052382 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57988.084297 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 57853.998478 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57804.054054 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57716.052382 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57988.084297 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 57853.998478 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.toL2Bus.throughput 52790847 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2471761 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2471761 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763441 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763441 # Transaction distribution system.toL2Bus.trans_dist::Writeback 596489 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 247515 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 247515 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725013 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754007 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20046 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50514 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 7549580 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54750240 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83796742 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28484 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size::total 138654986 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 138654986 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 168824 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 4808734000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 3865148750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 4420266392 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 12925000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 30634250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.throughput 48160270 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution system.iobus.trans_dist::WriteResp 8184 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 2383092 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33447156 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 2390550 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 126646806 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 126646806 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) system.iobus.respLayer1.occupancy 38823243250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 7344844 # DTB read hits system.cpu0.dtb.read_misses 6860 # DTB read misses system.cpu0.dtb.write_hits 5551128 # DTB write hits system.cpu0.dtb.write_misses 1832 # DTB write misses system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 6351 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 7351704 # DTB read accesses system.cpu0.dtb.write_accesses 5552960 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 12895972 # DTB hits system.cpu0.dtb.misses 8692 # DTB misses system.cpu0.dtb.accesses 12904664 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.inst_hits 30211154 # ITB inst hits system.cpu0.itb.inst_misses 3603 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2758 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 30214757 # ITB inst accesses system.cpu0.itb.hits 30211154 # DTB hits system.cpu0.itb.misses 3603 # DTB misses system.cpu0.itb.accesses 30214757 # DTB accesses system.cpu0.numCycles 2627736532 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 29624937 # Number of instructions committed system.cpu0.committedOps 37728426 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 34074958 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4583 # Number of float alu accesses system.cpu0.num_func_calls 1045164 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 3935196 # number of instructions that are conditional controls system.cpu0.num_int_insts 34074958 # number of integer instructions system.cpu0.num_fp_insts 4583 # number of float instructions system.cpu0.num_int_register_reads 197582111 # number of times the integer registers were read system.cpu0.num_int_register_writes 36713164 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3288 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written system.cpu0.num_mem_refs 13470170 # number of memory refs system.cpu0.num_load_insts 7667939 # Number of load instructions system.cpu0.num_store_insts 5802231 # Number of store instructions system.cpu0.num_idle_cycles 2282002616.045546 # Number of idle cycles system.cpu0.num_busy_cycles 345733915.954454 # Number of busy cycles system.cpu0.not_idle_fraction 0.131571 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.868429 # Percentage of idle cycles system.cpu0.Branches 5074688 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 856147 # number of replacements system.cpu0.icache.tags.tagsinuse 510.849495 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 60652706 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 856659 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 70.801458 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 20216402250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 158.742483 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 352.107012 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.310044 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.687709 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997753 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 62366026 # Number of tag accesses system.cpu0.icache.tags.data_accesses 62366026 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 29795008 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 30857698 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60652706 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29795008 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu1.inst 30857698 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 60652706 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 29795008 # number of overall hits system.cpu0.icache.overall_hits::cpu1.inst 30857698 # number of overall hits system.cpu0.icache.overall_hits::total 60652706 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 416146 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 440514 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 856660 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 416146 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu1.inst 440514 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 856660 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 416146 # number of overall misses system.cpu0.icache.overall_misses::cpu1.inst 440514 # number of overall misses system.cpu0.icache.overall_misses::total 856660 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5672028500 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6130116250 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 11802144750 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 5672028500 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::cpu1.inst 6130116250 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 11802144750 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 5672028500 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu1.inst 6130116250 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 11802144750 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 30211154 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 31298212 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61509366 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 30211154 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu1.inst 31298212 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61509366 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 30211154 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu1.inst 31298212 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61509366 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013775 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014075 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013927 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013775 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014075 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013927 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013775 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014075 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013927 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13629.900323 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13915.826171 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.929879 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13629.900323 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13915.826171 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 13776.929879 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13629.900323 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13915.826171 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 13776.929879 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416146 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440514 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 856660 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 416146 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::cpu1.inst 440514 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 856660 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 416146 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 440514 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 856660 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4838197500 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5246649750 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 10084847250 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4838197500 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5246649750 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 10084847250 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4838197500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5246649750 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 10084847250 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442799750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1085250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 443885000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442799750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1085250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 443885000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013775 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014075 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013927 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013775 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014075 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013927 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013775 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014075 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013927 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11626.202102 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11910.290592 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11772.286847 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11626.202102 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11910.290592 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 11772.286847 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11626.202102 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11910.290592 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.286847 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 627716 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.875867 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 23661613 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 628228 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 37.664053 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 152.516115 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 359.359751 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.297883 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.701875 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 97787592 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 97787592 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6450546 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6749057 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13199603 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4919460 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 5055668 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 9975128 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118398 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117802 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 236200 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124425 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123348 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247773 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 11370006 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 11804725 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 23174731 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 11370006 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 11804725 # number of overall hits system.cpu0.dcache.overall_hits::total 23174731 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 182595 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 186544 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 369139 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 126114 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 124310 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 250424 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6030 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5544 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 11574 # number of LoadLockedReq misses system.cpu0.dcache.demand_misses::cpu0.data 308709 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu1.data 310854 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 619563 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 308709 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 310854 # number of overall misses system.cpu0.dcache.overall_misses::total 619563 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2721600000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2760360750 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 5481960750 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5821979202 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5534732315 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 11356711517 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81055000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79345250 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 160400250 # number of LoadLockedReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 8543579202 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu1.data 8295093065 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 16838672267 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 8543579202 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 8295093065 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 16838672267 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 6633141 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 6935601 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 13568742 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5045574 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 5179978 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10225552 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124428 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123346 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247774 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124425 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123348 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247773 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 11678715 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 12115579 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 23794294 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 11678715 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 12115579 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 23794294 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027528 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026897 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.027205 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024995 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023998 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048462 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044947 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046712 # miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026433 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025657 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026433 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025657 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14905.117884 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14797.370862 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.668041 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46164.416338 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44523.628952 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 45349.932582 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.956882 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.913781 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13858.670295 # average LoadLockedReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27675.186671 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26684.852262 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 27178.305139 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27675.186671 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26684.852262 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 27178.305139 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 596489 # number of writebacks system.cpu0.dcache.writebacks::total 596489 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182595 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186544 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 369139 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126114 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 124310 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 250424 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6030 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5544 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11574 # number of LoadLockedReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 308709 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu1.data 310854 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 619563 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 308709 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 310854 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 619563 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355168000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2386207250 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741375250 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5543852798 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5262622685 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10806475483 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68990000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68208750 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137198750 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7899020798 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7648829935 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 15547850733 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7899020798 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7648829935 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 15547850733 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90318421750 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91762441000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080862750 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13218125626 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13022508499 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26240634125 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103536547376 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104784949499 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208321496875 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027528 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026897 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024995 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023998 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048462 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044947 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046712 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12898.315945 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12791.659072 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12844.417008 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43959.059248 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42334.668852 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43152.714927 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.127695 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12303.165584 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.047866 # average LoadLockedReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 7655819 # DTB read hits system.cpu1.dtb.read_misses 7243 # DTB read misses system.cpu1.dtb.write_hits 5681899 # DTB write hits system.cpu1.dtb.write_misses 1828 # DTB write misses system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 6711 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 7663062 # DTB read accesses system.cpu1.dtb.write_accesses 5683727 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 13337718 # DTB hits system.cpu1.dtb.misses 9071 # DTB misses system.cpu1.dtb.accesses 13346789 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.inst_hits 31298229 # ITB inst hits system.cpu1.itb.inst_misses 3696 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 2898 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 31301925 # ITB inst accesses system.cpu1.itb.hits 31298229 # DTB hits system.cpu1.itb.misses 3696 # DTB misses system.cpu1.itb.accesses 31301925 # DTB accesses system.cpu1.numCycles 2631652887 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 30590318 # Number of instructions committed system.cpu1.committedOps 38894351 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 35148183 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5686 # Number of float alu accesses system.cpu1.num_func_calls 1095318 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 4014750 # number of instructions that are conditional controls system.cpu1.num_int_insts 35148183 # number of integer instructions system.cpu1.num_fp_insts 5686 # number of float instructions system.cpu1.num_int_register_reads 203876321 # number of times the integer registers were read system.cpu1.num_int_register_writes 37823170 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4205 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1482 # number of times the floating registers were written system.cpu1.num_mem_refs 13931138 # number of memory refs system.cpu1.num_load_insts 7996929 # Number of load instructions system.cpu1.num_store_insts 5934209 # Number of store instructions system.cpu1.num_idle_cycles 2293790821.520695 # Number of idle cycles system.cpu1.num_busy_cycles 337862065.479305 # Number of busy cycles system.cpu1.not_idle_fraction 0.128384 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.871616 # Percentage of idle cycles system.cpu1.Branches 5235663 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.tags.tag_accesses 0 # Number of tag accesses system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::total 1783080197250 # number of ReadReq MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1783080197250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------