---------- Begin Simulation Statistics ---------- sim_seconds 51.660717 # Number of seconds simulated sim_ticks 51660717372000 # Number of ticks simulated final_tick 51660717372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 187164 # Simulator instruction rate (inst/s) host_op_rate 219920 # Simulator op (including micro ops) rate (op/s) host_tick_rate 10422609624 # Simulator tick rate (ticks/s) host_mem_usage 677216 # Number of bytes of host memory used host_seconds 4956.60 # Real time elapsed on the host sim_insts 927696922 # Number of instructions simulated sim_ops 1090057089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 368128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 311744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 10118784 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 60722568 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 418176 # Number of bytes read from this memory system.physmem.bytes_read::total 71939400 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 10118784 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 10118784 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 88730048 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::total 88750628 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 5752 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 4871 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 158106 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 948803 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6534 # Number of read requests responded to by this memory system.physmem.num_reads::total 1124066 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1386407 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::total 1388980 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 7126 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 6034 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 195870 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1175411 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8095 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1392536 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 195870 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 195870 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1717554 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1717952 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1717554 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 7126 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 6034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 195870 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1175809 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8095 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3110488 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1124066 # Number of read requests accepted system.physmem.writeReqs 1388980 # Number of write requests accepted system.physmem.readBursts 1124066 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1388980 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 71890560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue system.physmem.bytesWritten 88748928 # Total number of bytes written to DRAM system.physmem.bytesReadSys 71939400 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 88750628 # Total written bytes from the system interface side system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 65344 # Per bank write bursts system.physmem.perBankRdBursts::1 73127 # Per bank write bursts system.physmem.perBankRdBursts::2 68334 # Per bank write bursts system.physmem.perBankRdBursts::3 62589 # Per bank write bursts system.physmem.perBankRdBursts::4 65747 # Per bank write bursts system.physmem.perBankRdBursts::5 73971 # Per bank write bursts system.physmem.perBankRdBursts::6 66723 # Per bank write bursts system.physmem.perBankRdBursts::7 65172 # Per bank write bursts system.physmem.perBankRdBursts::8 63356 # Per bank write bursts system.physmem.perBankRdBursts::9 122297 # Per bank write bursts system.physmem.perBankRdBursts::10 70526 # Per bank write bursts system.physmem.perBankRdBursts::11 71466 # Per bank write bursts system.physmem.perBankRdBursts::12 64199 # Per bank write bursts system.physmem.perBankRdBursts::13 65172 # Per bank write bursts system.physmem.perBankRdBursts::14 60121 # Per bank write bursts system.physmem.perBankRdBursts::15 65146 # Per bank write bursts system.physmem.perBankWrBursts::0 84316 # Per bank write bursts system.physmem.perBankWrBursts::1 87030 # Per bank write bursts system.physmem.perBankWrBursts::2 86821 # Per bank write bursts system.physmem.perBankWrBursts::3 84154 # Per bank write bursts system.physmem.perBankWrBursts::4 87756 # Per bank write bursts system.physmem.perBankWrBursts::5 92254 # Per bank write bursts system.physmem.perBankWrBursts::6 85357 # Per bank write bursts system.physmem.perBankWrBursts::7 85828 # Per bank write bursts system.physmem.perBankWrBursts::8 86266 # Per bank write bursts system.physmem.perBankWrBursts::9 90537 # Per bank write bursts system.physmem.perBankWrBursts::10 89139 # Per bank write bursts system.physmem.perBankWrBursts::11 90914 # Per bank write bursts system.physmem.perBankWrBursts::12 83868 # Per bank write bursts system.physmem.perBankWrBursts::13 84845 # Per bank write bursts system.physmem.perBankWrBursts::14 82305 # Per bank write bursts system.physmem.perBankWrBursts::15 85312 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 29 # Number of times write queue was full causing retry system.physmem.totGap 51660715485000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 1124051 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1386407 # Write request sizes (log2) system.physmem.rdQLenPdf::0 1060868 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 56201 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 346 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 477 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 558 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 541 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1154 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 751 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 368 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 157 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 132 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 33876 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 39158 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 77727 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 79574 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 81890 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 80157 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 81104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 84995 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 84344 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 80623 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 81914 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 84683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 81947 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 82184 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 83786 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 79897 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 78990 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 78233 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 2554 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 491 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 415 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 321 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 258 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 248 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 209 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 228 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 308 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 297 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 116 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 638647 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 251.530251 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 152.310832 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 286.508507 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 275744 43.18% 43.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 164283 25.72% 68.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 60231 9.43% 78.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 32872 5.15% 83.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 22951 3.59% 87.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 16028 2.51% 89.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 11191 1.75% 91.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 9395 1.47% 92.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 45952 7.20% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 638647 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 75991 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 14.781369 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 142.935713 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 75988 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 75991 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 75991 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 18.248240 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.695683 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 7.085121 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 64109 84.36% 84.36% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 9386 12.35% 96.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 485 0.64% 97.35% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 369 0.49% 97.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 63 0.08% 97.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 114 0.15% 98.07% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 258 0.34% 98.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 31 0.04% 98.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 303 0.40% 98.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 66 0.09% 98.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 30 0.04% 98.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 60 0.08% 99.06% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 313 0.41% 99.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 41 0.05% 99.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 27 0.04% 99.56% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 117 0.15% 99.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 162 0.21% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 21 0.03% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 2 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 3 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 12 0.02% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 75991 # Writes before turning the bus around for reads system.physmem.totQLat 16312474093 # Total ticks spent queuing system.physmem.totMemAccLat 37374161593 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5616450000 # Total ticks spent in databus transfers system.physmem.avgQLat 14522.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 33272.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing system.physmem.readRowHits 859362 # Number of row buffer hits during reads system.physmem.writeRowHits 1011981 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate 72.98 # Row buffer hit rate for writes system.physmem.avgGap 20557011.49 # Average gap between requests system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 2420719560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1320829125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 4219854600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 4493983680 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1315006290315 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29842911750000 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 34544599863120 # Total energy per rank (pJ) system.physmem_0.averagePower 668.682250 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 49645601262378 # Time in different power states system.physmem_0.memoryStateTime::REF 1725064640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 290044177622 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 2407451760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 1313589750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4541752800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 4491845280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 1315022855940 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 29842897218750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 34544901150120 # Total energy per rank (pJ) system.physmem_1.averagePower 668.688082 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 49645554021211 # Time in different power states system.physmem_1.memoryStateTime::REF 1725064640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 290092863289 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.bridge.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu.branchPred.lookups 256052360 # Number of BP lookups system.cpu.branchPred.condPredicted 178125867 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12215850 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 188334497 # Number of BTB lookups system.cpu.branchPred.BTBHits 126943208 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 67.403057 # BTB Hit Percentage system.cpu.branchPred.usedRAS 31309548 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2129742 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 7077002 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 5011250 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 2065752 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 841782 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 558947 # Table walker walks requested system.cpu.dtb.walker.walksLong 558947 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walksLongTerminationLevel::Level2 19870 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181727 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walkWaitTime::samples 558947 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::0 558947 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::total 558947 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkCompletionTime::samples 201597 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::mean 27104.207900 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::gmean 22942.325413 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::stdev 21051.309840 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::0-65535 199234 98.83% 98.83% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.83% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-196607 2010 1.00% 99.83% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::327680-393215 59 0.03% 99.94% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::total 201597 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -1569310592 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -1569310592 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -1569310592 # Table walker pending requests distribution system.cpu.dtb.walker.walkPageSizes::4K 181728 90.14% 90.14% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::2M 19870 9.86% 100.00% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::total 201598 # Table walker page sizes translated system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 558947 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 558947 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 201598 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 201598 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 760545 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 179275780 # DTB read hits system.cpu.dtb.read_misses 461379 # DTB read misses system.cpu.dtb.write_hits 158920483 # DTB write hits system.cpu.dtb.write_misses 97568 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 78530 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 1411 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 14509 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 22879 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 179737159 # DTB read accesses system.cpu.dtb.write_accesses 159018051 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 338196263 # DTB hits system.cpu.dtb.misses 558947 # DTB misses system.cpu.dtb.accesses 338755210 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 134834 # Table walker walks requested system.cpu.itb.walker.walksLong 134834 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate system.cpu.itb.walker.walksLongTerminationLevel::Level3 117333 # Level at which table walker walks with long descriptors terminate system.cpu.itb.walker.walkWaitTime::samples 134834 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::0 134834 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 134834 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 118400 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::mean 30431.579392 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::gmean 25904.631312 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::stdev 24094.406061 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::0-65535 115676 97.70% 97.70% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::65536-131071 5 0.00% 97.70% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-196607 2464 2.08% 99.78% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.85% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.10% 99.96% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::393216-458751 17 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 118400 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -1570341092 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -1570341092 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -1570341092 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 117333 99.10% 99.10% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1067 0.90% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 118400 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134834 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 134834 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118400 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 118400 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 253234 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 442741882 # ITB inst hits system.cpu.itb.inst_misses 134834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 56540 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 318606 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 442876716 # ITB inst accesses system.cpu.itb.hits 442741882 # DTB hits system.cpu.itb.misses 134834 # DTB misses system.cpu.itb.accesses 442876716 # DTB accesses system.cpu.numPwrStateTransitions 33004 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16502 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::mean 3052827188.483881 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::stdev 59796953066.006256 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 7205 43.66% 43.66% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.13% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988777699120 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16502 # Distribution of time spent in the clock gated state system.cpu.pwrStateResidencyTicks::ON 1282963107639 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::CLK_GATED 50377754264361 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2565980290 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 927696922 # Number of instructions committed system.cpu.committedOps 1090057089 # Number of ops (including micro ops) committed system.cpu.discardedOps 94830796 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 7642 # Number of times Execute suspended instruction fetching system.cpu.quiesceCycles 100756547271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.cpi 2.765968 # CPI: cycles per instruction system.cpu.ipc 0.361537 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 755349201 69.29% 69.29% # Class of committed instruction system.cpu.op_class_0::IntMult 2273269 0.21% 69.50% # Class of committed instruction system.cpu.op_class_0::IntDiv 98990 0.01% 69.51% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatMisc 109509 0.01% 69.52% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction system.cpu.op_class_0::MemRead 173855507 15.95% 85.47% # Class of committed instruction system.cpu.op_class_0::MemWrite 158370570 14.53% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1090057089 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16502 # number of quiesce instructions executed system.cpu.tickCycles 1756726391 # Number of cycles that the object actually ticked system.cpu.idleCycles 809253899 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 10800470 # number of replacements system.cpu.dcache.tags.tagsinuse 511.930063 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 322845784 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 10800982 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 29.890410 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7088310500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.930063 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1354272764 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1354272764 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 165477998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 165477998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148389977 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148389977 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 514152 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 514152 # number of SoftPFReq hits system.cpu.dcache.WriteLineReq_hits::cpu.data 336855 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_hits::total 336855 # number of WriteLineReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3884412 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3884412 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4194010 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4194010 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 314204830 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 314204830 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 314718982 # number of overall hits system.cpu.dcache.overall_hits::total 314718982 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 5939711 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 5939711 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 4167073 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 4167073 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1413293 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1413293 # number of SoftPFReq misses system.cpu.dcache.WriteLineReq_misses::cpu.data 1239143 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 1239143 # number of WriteLineReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 311310 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 311310 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses system.cpu.dcache.demand_misses::cpu.data 11345927 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 11345927 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 12759220 # number of overall misses system.cpu.dcache.overall_misses::total 12759220 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 110013337000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 110013337000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 204497661000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 204497661000 # number of WriteReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53262030500 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 53262030500 # number of WriteLineReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5161319000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 5161319000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 367773028500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 367773028500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 367773028500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 367773028500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 171417709 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 171417709 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 152557050 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 152557050 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 1927445 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 1927445 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1575998 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1575998 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4195722 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4195722 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4194011 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4194011 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 325550757 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 325550757 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 327478202 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 327478202 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034651 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.034651 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027315 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.027315 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733247 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.733247 # miss rate for SoftPFReq accesses system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786259 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 0.786259 # miss rate for WriteLineReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074197 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074197 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.034851 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.034851 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.038962 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.038962 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18521.664943 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 18521.664943 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49074.652880 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 49074.652880 # average WriteReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42982.957173 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42982.957173 # average WriteLineReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16579.354984 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16579.354984 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32414.542108 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 32414.542108 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 28824.099631 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 28824.099631 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 8297164 # number of writebacks system.cpu.dcache.writebacks::total 8297164 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 307308 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 307308 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1836532 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1836532 # number of WriteReq MSHR hits system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 159 # number of WriteLineReq MSHR hits system.cpu.dcache.WriteLineReq_mshr_hits::total 159 # number of WriteLineReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69724 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 69724 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2143999 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2143999 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2143999 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2143999 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5632403 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 5632403 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2330541 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2330541 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1405812 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1405812 # number of SoftPFReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238984 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 1238984 # number of WriteLineReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241586 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 241586 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 9201928 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9201928 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 10607740 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 10607740 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96403190500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 96403190500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108391524000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 108391524000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26704093000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26704093000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52015388000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52015388000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3504907500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3504907500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256810102500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 256810102500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283514195500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 283514195500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197989500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197989500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197989500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197989500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032858 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032858 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015277 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015277 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729366 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729366 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786158 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786158 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057579 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057579 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028266 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032392 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032392 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17115.819039 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17115.819039 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46509.168472 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46509.168472 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18995.493708 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18995.493708 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41982.291942 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41982.291942 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14507.908157 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14507.908157 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27908.292969 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 27908.292969 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26727.106386 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26727.106386 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183932.976229 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183932.976229 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91954.208270 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91954.208270 # average overall mshr uncacheable latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24348068 # number of replacements system.cpu.icache.tags.tagsinuse 511.885312 # Cycle average of tags in use system.cpu.icache.tags.total_refs 418063563 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 24348580 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 17.169936 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 32786837500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.885312 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 466760742 # Number of tag accesses system.cpu.icache.tags.data_accesses 466760742 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 418063563 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 418063563 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 418063563 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 418063563 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 418063563 # number of overall hits system.cpu.icache.overall_hits::total 418063563 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 24348590 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 24348590 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 24348590 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 24348590 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 24348590 # number of overall misses system.cpu.icache.overall_misses::total 24348590 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 329659145500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 329659145500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 329659145500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 329659145500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 329659145500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 329659145500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 442412153 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 442412153 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 442412153 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 442412153 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 442412153 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 442412153 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.055036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.055036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.055036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.055036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.055036 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13539.147257 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 13539.147257 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 13539.147257 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13539.147257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 24348068 # number of writebacks system.cpu.icache.writebacks::total 24348068 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24348590 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 24348590 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 24348590 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 24348590 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 24348590 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 24348590 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305310556500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 305310556500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305310556500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 305310556500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305310556500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 305310556500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746653000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746653000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746653000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 6746653000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055036 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055036 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055036 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.055036 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055036 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.055036 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12539.147298 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12539.147298 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12539.147298 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 12539.147298 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12539.147298 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12539.147298 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128976.906460 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128976.906460 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128976.906460 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128976.906460 # average overall mshr uncacheable latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1508622 # number of replacements system.cpu.l2cache.tags.tagsinuse 65349.873719 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 66336088 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1571990 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 42.198798 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 10459942000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 36987.173983 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 327.335267 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 410.823725 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 8044.893687 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 19579.647057 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.564379 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004995 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006269 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122755 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.298762 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997160 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 63079 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 289 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 541 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2400 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54498 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962509 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 577006805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 577006805 # Number of data accesses system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 916908 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 278918 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1195826 # number of ReadReq hits system.cpu.l2cache.WritebackDirty_hits::writebacks 8297164 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 8297164 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 24344519 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 24344519 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 10512 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 10512 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1646050 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1646050 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24242763 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 24242763 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6965917 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6965917 # number of ReadSharedReq hits system.cpu.l2cache.InvalidateReq_hits::cpu.data 704740 # number of InvalidateReq hits system.cpu.l2cache.InvalidateReq_hits::total 704740 # number of InvalidateReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 916908 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 278918 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 24242763 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 8611967 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 34050556 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 916908 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 278918 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 24242763 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 8611967 # number of overall hits system.cpu.l2cache.overall_hits::total 34050556 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5752 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4871 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 10623 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 37790 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 37790 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 636382 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 636382 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 105826 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 105826 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 313691 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 313691 # number of ReadSharedReq misses system.cpu.l2cache.InvalidateReq_misses::cpu.data 534244 # number of InvalidateReq misses system.cpu.l2cache.InvalidateReq_misses::total 534244 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5752 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 4871 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 105826 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 950073 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 1066522 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5752 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 4871 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 105826 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 950073 # number of overall misses system.cpu.l2cache.overall_misses::total 1066522 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 785759500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 668656000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1454415500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1443890500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 1443890500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84519588500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 84519588500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14015218000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 14015218000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42318242000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 42318242000 # number of ReadSharedReq miss cycles system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 10682500 # number of InvalidateReq miss cycles system.cpu.l2cache.InvalidateReq_miss_latency::total 10682500 # number of InvalidateReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 785759500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 668656000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14015218000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 126837830500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 142307464000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 785759500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 668656000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14015218000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 126837830500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 142307464000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 922660 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 283789 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1206449 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 8297164 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 8297164 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 24344519 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 24344519 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48302 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 48302 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2282432 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2282432 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24348589 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 24348589 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7279608 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 7279608 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238984 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::total 1238984 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 922660 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 283789 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 24348589 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9562040 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 35117078 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 922660 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 283789 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 24348589 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9562040 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 35117078 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006234 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017164 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.008805 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782369 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782369 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.278818 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.278818 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004346 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004346 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043092 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043092 # miss rate for ReadSharedReq accesses system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.431195 # miss rate for InvalidateReq accesses system.cpu.l2cache.InvalidateReq_miss_rate::total 0.431195 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006234 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017164 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004346 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.099359 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.030370 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006234 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017164 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004346 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.099359 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.030370 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136606.310848 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137272.839253 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 136911.936364 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38208.269383 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38208.269383 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132812.663620 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132812.663620 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132436.433391 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132436.433391 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134904.227409 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134904.227409 # average ReadSharedReq miss latency system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 19.995545 # average InvalidateReq miss latency system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 19.995545 # average InvalidateReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136606.310848 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137272.839253 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132436.433391 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133503.247119 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 133431.344126 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136606.310848 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137272.839253 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132436.433391 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133503.247119 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 133431.344126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 1279776 # number of writebacks system.cpu.l2cache.writebacks::total 1279776 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5752 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4871 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 10623 # number of ReadReq MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 4 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 4 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37790 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 37790 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 636382 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 636382 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 105823 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 105823 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 313670 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 313670 # number of ReadSharedReq MSHR misses system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 534244 # number of InvalidateReq MSHR misses system.cpu.l2cache.InvalidateReq_mshr_misses::total 534244 # number of InvalidateReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5752 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4871 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 105823 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 950052 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 1066498 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5752 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4871 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 105823 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 950052 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1066498 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 728239500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 619946000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1348185500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2569159500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2569159500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 78155754528 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 78155754528 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12956680572 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12956680572 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39179236400 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39179236400 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 37222318500 # number of InvalidateReq MSHR miss cycles system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 37222318500 # number of InvalidateReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 728239500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 619946000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12956680572 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117334990928 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 131639857000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 728239500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 619946000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12956680572 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117334990928 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 131639857000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5935856500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776686000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712542500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5935856500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776686000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712542500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782369 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782369 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.278818 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.278818 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004346 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043089 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043089 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.431195 # mshr miss rate for InvalidateReq accesses system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.431195 # mshr miss rate for InvalidateReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.030370 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.030370 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126911.936364 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67985.168034 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67985.168034 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122812.641665 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122812.641665 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122437.282746 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122437.282746 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124905.908758 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124905.908758 # average ReadSharedReq mshr miss latency system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69672.880744 # average InvalidateReq mshr miss latency system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69672.880744 # average InvalidateReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.275692 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136182.853522 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85703.692714 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97839.335238 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 71038022 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 35888421 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4192 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2302 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2302 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 1730261 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 33359239 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 9683600 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24348068 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2741013 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 48305 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 48306 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2282432 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2282432 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 24348590 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7288491 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 1345648 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 1238984 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73149864 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32634714 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 686896 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163808 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 108635282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3119933760 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1143229458 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2270312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7381280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 4272814810 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 2178284 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 92284400 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 38701577 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018037 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.133086 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 38003503 98.20% 98.20% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 698074 1.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 38701577 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 68717300491 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1477390 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 36605927318 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 15037927648 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 403140932 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 1241184926 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40331 # Transaction distribution system.iobus.trans_dist::ReadResp 40331 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231020 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231020 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 353804 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334512 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7334512 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7492432 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 37711500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 25249000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36460500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 567164602 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 147780000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115492 # number of replacements system.iocache.tags.tagsinuse 10.441393 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115508 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13153371816000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.521310 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 6.920084 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.432505 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652587 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039947 # Number of tag accesses system.iocache.tags.data_accesses 1039947 # Number of data accesses system.iocache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8846 # number of ReadReq misses system.iocache.ReadReq_misses::total 8883 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 115510 # number of demand (read+write) misses system.iocache.demand_misses::total 115550 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 115510 # number of overall misses system.iocache.overall_misses::total 115550 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::realview.ide 1687962584 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 1693032584 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 13411761018 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 13411761018 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::realview.ide 15099723602 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 15105144602 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles system.iocache.overall_miss_latency::realview.ide 15099723602 # number of overall miss cycles system.iocache.overall_miss_latency::total 15105144602 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8846 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8883 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 115510 # number of demand (read+write) accesses system.iocache.demand_accesses::total 115550 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses system.iocache.overall_accesses::realview.ide 115510 # number of overall (read+write) accesses system.iocache.overall_accesses::total 115550 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::realview.ide 190816.480217 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 190592.433187 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125738.403004 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 125738.403004 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency system.iocache.demand_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency system.iocache.demand_avg_miss_latency::total 130723.882319 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency system.iocache.overall_avg_miss_latency::total 130723.882319 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 34055 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 3409 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 9.989733 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8846 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8883 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::realview.ide 115510 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 115550 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 115510 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 115550 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::realview.ide 1245662584 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 1248882584 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073418582 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 8073418582 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 9319081166 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 9322502166 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 9319081166 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 9322502166 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140816.480217 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 140592.433187 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75690.191461 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75690.191461 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency system.membus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 86006 # Transaction distribution system.membus.trans_dist::ReadResp 525005 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution system.membus.trans_dist::WritebackDirty 1386407 # Transaction distribution system.membus.trans_dist::CleanEvict 236604 # Transaction distribution system.membus.trans_dist::UpgradeReq 38552 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution system.membus.trans_dist::ReadExReq 635760 # Transaction distribution system.membus.trans_dist::ReadExResp 635760 # Transaction distribution system.membus.trans_dist::ReadSharedReq 438999 # Transaction distribution system.membus.trans_dist::InvalidateReq 640771 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4321043 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4450695 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 237576 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4688271 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 153447468 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 153617874 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7242560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 160860434 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 3013 # Total snoops (count) system.membus.snoopTraffic 192384 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 3496836 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 3496836 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 3496836 # Request fanout histogram system.membus.reqLayer0.occupancy 99852500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 5614500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 9224879373 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 6035081327 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44925690 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ----------