---------- Begin Simulation Statistics ---------- sim_seconds 5.137942 # Number of seconds simulated sim_ticks 5137941673500 # Number of ticks simulated final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 248874 # Simulator instruction rate (inst/s) host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) host_tick_rate 5246911955 # Simulator tick rate (ticks/s) host_mem_usage 994832 # Number of bytes of host memory used host_seconds 979.23 # Real time elapsed on the host sim_insts 243705182 # Number of instructions simulated sim_ops 484425104 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 100936 # Number of read requests accepted system.physmem.writeReqs 78380 # Number of write requests accepted system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 5898 # Per bank write bursts system.physmem.perBankRdBursts::1 6403 # Per bank write bursts system.physmem.perBankRdBursts::2 6411 # Per bank write bursts system.physmem.perBankRdBursts::3 6523 # Per bank write bursts system.physmem.perBankRdBursts::4 6306 # Per bank write bursts system.physmem.perBankRdBursts::5 6840 # Per bank write bursts system.physmem.perBankRdBursts::6 6199 # Per bank write bursts system.physmem.perBankRdBursts::7 6896 # Per bank write bursts system.physmem.perBankRdBursts::8 5528 # Per bank write bursts system.physmem.perBankRdBursts::9 5898 # Per bank write bursts system.physmem.perBankRdBursts::10 6128 # Per bank write bursts system.physmem.perBankRdBursts::11 6570 # Per bank write bursts system.physmem.perBankRdBursts::12 6317 # Per bank write bursts system.physmem.perBankRdBursts::13 6334 # Per bank write bursts system.physmem.perBankRdBursts::14 6542 # Per bank write bursts system.physmem.perBankRdBursts::15 6126 # Per bank write bursts system.physmem.perBankWrBursts::0 4721 # Per bank write bursts system.physmem.perBankWrBursts::1 4902 # Per bank write bursts system.physmem.perBankWrBursts::2 4923 # Per bank write bursts system.physmem.perBankWrBursts::3 5159 # Per bank write bursts system.physmem.perBankWrBursts::4 5192 # Per bank write bursts system.physmem.perBankWrBursts::5 5457 # Per bank write bursts system.physmem.perBankWrBursts::6 4843 # Per bank write bursts system.physmem.perBankWrBursts::7 5797 # Per bank write bursts system.physmem.perBankWrBursts::8 4085 # Per bank write bursts system.physmem.perBankWrBursts::9 4367 # Per bank write bursts system.physmem.perBankWrBursts::10 4807 # Per bank write bursts system.physmem.perBankWrBursts::11 4903 # Per bank write bursts system.physmem.perBankWrBursts::12 4884 # Per bank write bursts system.physmem.perBankWrBursts::13 4699 # Per bank write bursts system.physmem.perBankWrBursts::14 5116 # Per bank write bursts system.physmem.perBankWrBursts::15 4505 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 11 # Number of times write queue was full causing retry system.physmem.totGap 5136941479000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 100936 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 78380 # Write request sizes (log2) system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5379 3 0.01% 99.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::5504-5507 3 0.01% 99.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568-5571 20 0.06% 99.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7107 2 0.01% 99.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7299 2 0.01% 99.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8131 2 0.01% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::8448-8451 2 0.01% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::10432-10435 2 0.01% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::10560-10563 2 0.01% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::11392-11395 3 0.01% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::12416-12419 2 0.01% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation system.physmem.totQLat 2741683498 # Total ticks spent queuing system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing system.physmem.readRowHits 85240 # Number of row buffer hits during reads system.physmem.writeRowHits 58432 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes system.physmem.avgGap 28647423.98 # Average gap between requests system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 6427951 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 423177 # Transaction distribution system.membus.trans_dist::ReadResp 423176 # Transaction distribution system.membus.trans_dist::WriteReq 6474 # Transaction distribution system.membus.trans_dist::WriteResp 6474 # Transaction distribution system.membus.trans_dist::Writeback 78380 # Transaction distribution system.membus.trans_dist::UpgradeReq 714 # Transaction distribution system.membus.trans_dist::UpgradeResp 714 # Transaction distribution system.membus.trans_dist::ReadExReq 80216 # Transaction distribution system.membus.trans_dist::ReadExResp 80216 # Transaction distribution system.membus.trans_dist::MessageReq 892 # Transaction distribution system.membus.trans_dist::MessageResp 892 # Transaction distribution system.membus.trans_dist::BadAddressError 1 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 32719620 # Total data (bytes) system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.l2c.tags.replacements 103855 # number of replacements system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 346717 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 513928 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 10907 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 5932 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 155624 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 223811 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.dtb.walker 47020 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.itb.walker 9087 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 331652 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 566093 # number of ReadReq hits system.l2c.ReadReq_hits::total 2240790 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits system.l2c.Writeback_hits::writebacks 1542501 # number of Writeback hits system.l2c.Writeback_hits::total 1542501 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 57 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 70841 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 36082 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu2.data 59675 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 166598 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 19693 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 10328 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 346717 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 584769 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 10907 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 5932 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 155624 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 259893 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.dtb.walker 47020 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.itb.walker 9087 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 331652 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 625768 # number of demand (read+write) hits system.l2c.demand_hits::total 2407390 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 19693 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 10328 # number of overall hits system.l2c.overall_hits::cpu0.inst 346717 # number of overall hits system.l2c.overall_hits::cpu0.data 584769 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 10907 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 5932 # number of overall hits system.l2c.overall_hits::cpu1.inst 155624 # number of overall hits system.l2c.overall_hits::cpu1.data 259893 # number of overall hits system.l2c.overall_hits::cpu2.dtb.walker 47020 # number of overall hits system.l2c.overall_hits::cpu2.itb.walker 9087 # number of overall hits system.l2c.overall_hits::cpu2.inst 331652 # number of overall hits system.l2c.overall_hits::cpu2.data 625768 # number of overall hits system.l2c.overall_hits::total 2407390 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 6671 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 16268 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 2301 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 4539 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.dtb.walker 22 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 6029 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 11901 # number of ReadReq misses system.l2c.ReadReq_misses::total 47736 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 761 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 281 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 269 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 1311 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 76320 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 23649 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 29451 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 129420 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 6671 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 92588 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2301 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 28188 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.dtb.walker 22 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 6029 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 41352 # number of demand (read+write) misses system.l2c.demand_misses::total 177156 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.inst 6671 # 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mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.825153 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.351438 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.395925 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.330442 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.179381 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.030137 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.030137 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65097.765147 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66735.043274 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 66724.789561 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12136.188612 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10586.486989 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11378.243636 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58305.547380 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61441.506672 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 60044.853164 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 47575 # number of replacements system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 5000200819009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094274 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005892 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses system.iocache.demand_misses::total 47630 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses system.iocache.overall_misses::total 47630 # number of overall misses system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129801048 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 129801048 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6845673540 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 6845673540 # number of WriteReq miss cycles system.iocache.demand_miss_latency::pc.south_bridge.ide 6975474588 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 6975474588 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::pc.south_bridge.ide 6975474588 # number of overall miss cycles system.iocache.overall_miss_latency::total 6975474588 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.toL2Bus.throughput 52188015 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 268001344 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.throughput 1276093 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 150466 # Transaction distribution system.iobus.trans_dist::ReadResp 150466 # Transaction distribution system.iobus.trans_dist::WriteReq 32862 # Transaction distribution system.iobus.trans_dist::WriteResp 32862 # Transaction distribution system.iobus.trans_dist::MessageReq 892 # Transaction distribution system.iobus.trans_dist::MessageResp 892 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 6556491 # Total data (bytes) system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.numCycles 1184263733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 72124506 # Number of instructions committed system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 981373 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls system.cpu0.num_int_insts 134713165 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written system.cpu0.num_mem_refs 14049102 # number of memory refs system.cpu0.num_load_insts 10253492 # Number of load instructions system.cpu0.num_store_insts 3795610 # Number of store instructions system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 848510 # number of replacements system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits system.cpu0.icache.overall_hits::total 129618382 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses system.cpu0.icache.overall_misses::total 867413 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 8427.250288 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4049 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 236 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.156780 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18382 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 18382 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu2.inst 18382 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 18382 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu2.inst 18382 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 18382 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 157925 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 337717 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 495642 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu1.inst 157925 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::cpu2.inst 337717 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 495642 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 157925 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu2.inst 337717 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 495642 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1899637750 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4221033432 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 6120671182 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1899637750 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4221033432 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 6120671182 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1899637750 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4221033432 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 6120671182 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003798 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.003798 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.003798 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.976039 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 1632030 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997838 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 19577218 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 1632542 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 11.991862 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 205.523243 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 299.707974 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.766620 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.401413 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.585367 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013216 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 5112635 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 2556554 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 3831407 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 11500596 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3643791 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 1689050 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 2742153 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 8074994 # number of WriteReq hits system.cpu0.dcache.demand_hits::cpu0.data 8756426 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 4245604 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 6573560 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 19575590 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 8756426 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 4245604 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 6573560 # number of overall hits system.cpu0.dcache.overall_hits::total 19575590 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 530196 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 228350 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 940486 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1699032 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 148061 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 60070 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu2.data 106578 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 314709 # number of WriteReq misses system.cpu0.dcache.demand_misses::cpu0.data 678257 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu1.data 288420 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu2.data 1047064 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2013741 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 678257 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 288420 # number of overall misses system.cpu0.dcache.overall_misses::cpu2.data 1047064 # number of overall misses system.cpu0.dcache.overall_misses::total 2013741 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3284093256 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15033857981 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 18317951237 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2239487659 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3281341546 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 5520829205 # number of WriteReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu1.data 5523580915 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::cpu2.data 18315199527 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 23838780442 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 5523580915 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu2.data 18315199527 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 23838780442 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 5642831 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 2784904 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 4771893 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 13199628 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3791852 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 1749120 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 2848731 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 8389703 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 9434683 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 4534024 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 7620624 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 21589331 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 9434683 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 4534024 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 7620624 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 21589331 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093959 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081996 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197089 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.128718 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039047 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034343 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037412 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.037511 # miss rate for WriteReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071890 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.063612 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137399 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.093275 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071890 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063612 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137399 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.093275 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14381.840403 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.201248 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 10781.404492 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37281.299467 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.169660 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 17542.647986 # average WriteReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 11838.056851 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 11838.056851 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 171453 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 11788 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.544706 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1542501 # number of writebacks system.cpu0.dcache.writebacks::total 1542501 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362466 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 362466 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17153 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 17153 # number of WriteReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu2.data 379619 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 379619 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu2.data 379619 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 379619 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 228350 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578020 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 806370 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60070 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89425 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 149495 # number of WriteReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu1.data 288420 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu2.data 667445 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 955865 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 288420 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 667445 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 955865 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2826173744 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8314744809 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11140918553 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2108252341 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2905747700 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5014000041 # number of WriteReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4934426085 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11220492509 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 16154918594 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4934426085 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11220492509 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 16154918594 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30636255000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33190282000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63826537000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 532271000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 712236000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1244507000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31168526000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33902518000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65071044000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081996 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121130 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061090 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034343 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031391 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017819 # mshr miss rate for WriteReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.044275 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.044275 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.499864 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14384.873895 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13816.137199 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35096.592992 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32493.684093 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33539.583538 # average WriteReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 2606010326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 35502902 # Number of instructions committed system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 466888 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls system.cpu1.num_int_insts 64128875 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written system.cpu1.num_mem_refs 4724906 # number of memory refs system.cpu1.num_load_insts 2973846 # Number of load instructions system.cpu1.num_store_insts 1751060 # Number of store instructions system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.branchPred.lookups 28668505 # Number of BP lookups system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. system.cpu2.numCycles 154176343 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued system.cpu2.iq.rate 1.776371 # Inst issue rate system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed system.cpu2.iew.exec_branches 27815177 # Number of branches executed system.cpu2.iew.exec_stores 3067426 # Number of stores executed system.cpu2.iew.exec_rate 1.773340 # Inst execution rate system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back system.cpu2.iew.wb_producers 212629872 # num instructions producing a value system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle system.cpu2.commit.committedInsts 136077774 # Number of instructions committed system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed system.cpu2.commit.refs 7989069 # Number of memory references committed system.cpu2.commit.loads 5135991 # Number of loads committed system.cpu2.commit.membars 163538 # Number of memory barriers committed system.cpu2.commit.branches 27499066 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. system.cpu2.commit.function_calls 428759 # Number of function calls committed. system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu2.rob.rob_reads 361063162 # The number of ROB reads system.cpu2.rob.rob_writes 552523197 # The number of ROB writes system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 136077774 # Number of Instructions Simulated system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed ---------- End Simulation Statistics ----------