---------- Begin Simulation Statistics ---------- sim_seconds 0.061487 # Number of seconds simulated sim_ticks 61487437500 # Number of ticks simulated final_tick 61487437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 86290 # Simulator instruction rate (inst/s) host_op_rate 151942 # Simulator op (including micro ops) rate (op/s) host_tick_rate 33582980 # Simulator tick rate (ticks/s) host_mem_usage 365956 # Number of bytes of host memory used host_seconds 1830.91 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1893056 # Number of bytes read from this memory system.physmem.bytes_read::total 1961408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory system.physmem.bytes_written::total 20288 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 29579 # Number of read requests responded to by this memory system.physmem.num_reads::total 30647 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory system.physmem.num_writes::total 317 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 1111642 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 30787687 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 31899329 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1111642 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1111642 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 329954 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 329954 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 329954 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1111642 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 30787687 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32229283 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 122974876 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 35563581 # Number of BP lookups system.cpu.BPredUnit.condPredicted 35563581 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 1083908 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 25421016 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 25287599 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 27814300 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 193613700 # Number of instructions fetch has processed system.cpu.fetch.Branches 35563581 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 25287599 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 58598336 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 7345607 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 30298263 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 223 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 27172491 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 322176 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 122946211 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.768410 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.402032 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 67085101 54.56% 54.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2067083 1.68% 56.25% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 2985500 2.43% 58.67% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 3997651 3.25% 61.93% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 7978379 6.49% 68.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 5028202 4.09% 72.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 2861375 2.33% 74.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1431598 1.16% 76.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 29511322 24.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 122946211 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.289194 # Number of branch fetches per cycle system.cpu.fetch.rate 1.574417 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 38912587 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 22600530 # Number of cycles decode is blocked system.cpu.decode.RunCycles 48050125 # Number of cycles decode is running system.cpu.decode.UnblockCycles 7147919 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 6235050 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 336030812 # Number of instructions handled by decode system.cpu.rename.SquashCycles 6235050 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 43304200 # Number of cycles rename is idle system.cpu.rename.BlockCycles 3170225 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 8978 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 50645325 # Number of cycles rename is running system.cpu.rename.UnblockCycles 19582433 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 332156996 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 3311 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 17907327 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 182 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 334503257 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 881229115 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 881227036 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 2079 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 55290513 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 484 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 44388140 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 104937995 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 36474446 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 41500364 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5836392 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 323873529 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 307729409 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 216713 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 45479887 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 66424397 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 122946211 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.502960 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.799833 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 21631935 17.59% 17.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 17051158 13.87% 31.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 24526773 19.95% 51.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 23966381 19.49% 70.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 19143829 15.57% 86.48% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9189049 7.47% 93.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 5012385 4.08% 98.03% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 2266917 1.84% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 157784 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 122946211 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 50945 1.97% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1871750 72.23% 74.20% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 668572 25.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33168 0.01% 0.01% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 174887442 56.83% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 52 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 98817076 32.11% 88.95% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 33991671 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 307729409 # Type of FU issued system.cpu.iq.rate 2.502376 # Inst issue rate system.cpu.iq.fu_busy_cnt 2591267 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008421 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 741212334 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 369384855 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 304533759 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 675 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 209 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 310287186 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 322 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 52324197 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 14158611 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 53020 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 31592 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 5034695 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3174 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 6235050 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 247932 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 19449 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 323875287 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 344865 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 104937995 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 36474446 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 247 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 894 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 31592 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 595265 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 583416 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1178681 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 305536893 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 98199399 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 2192516 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 131640830 # number of memory reference insts executed system.cpu.iew.exec_branches 31219911 # Number of branches executed system.cpu.iew.exec_stores 33441431 # Number of stores executed system.cpu.iew.exec_rate 2.484547 # Inst execution rate system.cpu.iew.wb_sent 304949933 # cumulative count of insts sent to commit system.cpu.iew.wb_count 304533968 # cumulative count of insts written-back system.cpu.iew.wb_producers 225863686 # num instructions producing a value system.cpu.iew.wb_consumers 311805704 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.476392 # insts written-back per cycle system.cpu.iew.wb_fanout 0.724373 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 45684582 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1083935 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 116711161 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.383598 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.781080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 38716768 33.17% 33.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 22386952 19.18% 52.35% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 17053265 14.61% 66.97% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 13105313 11.23% 78.20% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 2048873 1.76% 79.95% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 3220721 2.76% 82.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1361336 1.17% 83.88% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 627536 0.54% 84.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 18190397 15.59% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 116711161 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219135 # Number of memory references committed system.cpu.commit.loads 90779384 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 29309705 # Number of branches committed system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 18190397 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 422397808 # The number of ROB reads system.cpu.rob.rob_writes 653994696 # The number of ROB writes system.cpu.timesIdled 646 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 28665 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated system.cpu.cpi 0.778378 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.778378 # CPI: Total CPI of All Threads system.cpu.ipc 1.284722 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.284722 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 598611638 # number of integer regfile reads system.cpu.int_regfile_writes 305159096 # number of integer regfile writes system.cpu.fp_regfile_reads 198 # number of floating regfile reads system.cpu.fp_regfile_writes 109 # number of floating regfile writes system.cpu.misc_regfile_reads 195504004 # number of misc regfile reads system.cpu.icache.replacements 86 # number of replacements system.cpu.icache.tagsinuse 846.025687 # Cycle average of tags in use system.cpu.icache.total_refs 27171094 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1075 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 25275.436279 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 846.025687 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.413098 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.413098 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 27171094 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 27171094 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 27171094 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 27171094 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 27171094 # number of overall hits system.cpu.icache.overall_hits::total 27171094 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1397 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1397 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1397 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1397 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1397 # number of overall misses system.cpu.icache.overall_misses::total 1397 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 49824500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 49824500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 49824500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 49824500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 49824500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 49824500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27172491 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27172491 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27172491 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 27172491 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 27172491 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 27172491 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35665.354331 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 35665.354331 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 35665.354331 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 35665.354331 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 320 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 320 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 320 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 320 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39164500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 39164500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39164500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 39164500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39164500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 39164500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36364.438254 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36364.438254 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2071944 # number of replacements system.cpu.dcache.tagsinuse 4071.467534 # Cycle average of tags in use system.cpu.dcache.total_refs 74936342 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2076040 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 36.095808 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21468323000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4071.467534 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994011 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994011 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 43578741 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 43578741 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31357591 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 31357591 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 74936332 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 74936332 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 74936332 # number of overall hits system.cpu.dcache.overall_hits::total 74936332 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2256554 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2256554 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 82160 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 82160 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 2338714 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2338714 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2338714 # number of overall misses system.cpu.dcache.overall_misses::total 2338714 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 9114703500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 9114703500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1290980000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1290980000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 10405683500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 10405683500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 10405683500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 10405683500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 45835295 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 45835295 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 77275046 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 77275046 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 77275046 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 77275046 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049232 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.049232 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002613 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002613 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.030265 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.030265 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.030265 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.030265 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4039.213553 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 4039.213553 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15712.999026 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 15712.999026 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 4449.318514 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 4449.318514 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2064785 # number of writebacks system.cpu.dcache.writebacks::total 2064785 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262571 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 262571 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 99 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 262670 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 262670 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 262670 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 262670 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993983 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1993983 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82061 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 82061 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2076044 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2076044 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2076044 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2076044 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4061724500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4061724500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125939500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125939500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5187664000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 5187664000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5187664000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5187664000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043503 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043503 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.026866 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026866 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2036.990536 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2036.990536 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13720.762603 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13720.762603 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1463 # number of replacements system.cpu.l2cache.tagsinuse 19632.807637 # Cycle average of tags in use system.cpu.l2cache.total_refs 4026981 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30627 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 131.484670 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 19126.604204 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 278.184174 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 228.019260 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.583698 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.008490 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006959 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.599146 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1993318 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1993325 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2064785 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2064785 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 53145 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 53145 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 2046463 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2046470 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2046463 # number of overall hits system.cpu.l2cache.overall_hits::total 2046470 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 586 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1654 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 28993 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 28993 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 29579 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 30647 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29579 # number of overall misses system.cpu.l2cache.overall_misses::total 30647 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38066500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21080500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 59147000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989282000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 989282000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 38066500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1010362500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 1048429000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 38066500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1010362500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 1048429000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1075 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1993904 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2064785 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2064785 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 82138 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 82138 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2076042 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2077117 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2076042 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2077117 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993488 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000294 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352979 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.352979 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993488 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.014248 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993488 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014248 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35642.790262 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35973.549488 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 35759.975816 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34121.408616 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34121.408616 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 34209.841094 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 34209.841094 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks system.cpu.l2cache.writebacks::total 317 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 586 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1654 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 29579 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 30647 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29579 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30647 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34670500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19225500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53896000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899128500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899128500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34670500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918354000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 953024500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34670500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918354000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 953024500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352979 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352979 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32463.014981 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32808.020478 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32585.247884 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.916670 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.916670 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------