---------- Begin Simulation Statistics ---------- sim_seconds 0.417356 # Number of seconds simulated sim_ticks 417356445500 # Number of ticks simulated final_tick 417356445500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 140228 # Simulator instruction rate (inst/s) host_op_rate 259297 # Simulator op (including micro ops) rate (op/s) host_tick_rate 70778301 # Simulator tick rate (ticks/s) host_mem_usage 373852 # Number of bytes of host memory used host_seconds 5896.67 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 225408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24527104 # Number of bytes read from this memory system.physmem.bytes_read::total 24752512 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 225408 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 225408 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 18881792 # Number of bytes written to this memory system.physmem.bytes_written::total 18881792 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3522 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 383236 # Number of read requests responded to by this memory system.physmem.num_reads::total 386758 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 295028 # Number of write requests responded to by this memory system.physmem.num_writes::total 295028 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 540085 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 58767761 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 59307846 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 540085 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 540085 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 45241405 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 45241405 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 45241405 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 540085 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 58767761 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 104549252 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 386758 # Number of read requests accepted system.physmem.writeReqs 295028 # Number of write requests accepted system.physmem.readBursts 386758 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 295028 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 24731520 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue system.physmem.bytesWritten 18879872 # Total number of bytes written to DRAM system.physmem.bytesReadSys 24752512 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 18881792 # Total written bytes from the system interface side system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 180541 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 24048 # Per bank write bursts system.physmem.perBankRdBursts::1 26419 # Per bank write bursts system.physmem.perBankRdBursts::2 24743 # Per bank write bursts system.physmem.perBankRdBursts::3 24616 # Per bank write bursts system.physmem.perBankRdBursts::4 23512 # Per bank write bursts system.physmem.perBankRdBursts::5 23771 # Per bank write bursts system.physmem.perBankRdBursts::6 24555 # Per bank write bursts system.physmem.perBankRdBursts::7 24371 # Per bank write bursts system.physmem.perBankRdBursts::8 23723 # Per bank write bursts system.physmem.perBankRdBursts::9 23964 # Per bank write bursts system.physmem.perBankRdBursts::10 24762 # Per bank write bursts system.physmem.perBankRdBursts::11 24062 # Per bank write bursts system.physmem.perBankRdBursts::12 23208 # Per bank write bursts system.physmem.perBankRdBursts::13 22939 # Per bank write bursts system.physmem.perBankRdBursts::14 23856 # Per bank write bursts system.physmem.perBankRdBursts::15 23881 # Per bank write bursts system.physmem.perBankWrBursts::0 18611 # Per bank write bursts system.physmem.perBankWrBursts::1 19928 # Per bank write bursts system.physmem.perBankWrBursts::2 18984 # Per bank write bursts system.physmem.perBankWrBursts::3 19007 # Per bank write bursts system.physmem.perBankWrBursts::4 18161 # Per bank write bursts system.physmem.perBankWrBursts::5 18513 # Per bank write bursts system.physmem.perBankWrBursts::6 19135 # Per bank write bursts system.physmem.perBankWrBursts::7 19081 # Per bank write bursts system.physmem.perBankWrBursts::8 18676 # Per bank write bursts system.physmem.perBankWrBursts::9 18213 # Per bank write bursts system.physmem.perBankWrBursts::10 18882 # Per bank write bursts system.physmem.perBankWrBursts::11 17764 # Per bank write bursts system.physmem.perBankWrBursts::12 17392 # Per bank write bursts system.physmem.perBankWrBursts::13 16995 # Per bank write bursts system.physmem.perBankWrBursts::14 17799 # Per bank write bursts system.physmem.perBankWrBursts::15 17857 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 417356409500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 386758 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 295028 # Write request sizes (log2) system.physmem.rdQLenPdf::0 381390 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 4646 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 348 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 6184 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 6581 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 16955 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 17534 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17616 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 17650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 17676 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 17676 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 17730 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 17732 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17722 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 17878 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 17608 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 17538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 147597 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 295.460965 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 174.362046 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 322.835917 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 54868 37.17% 37.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 40138 27.19% 64.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 13644 9.24% 73.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 7534 5.10% 78.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5520 3.74% 82.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3804 2.58% 85.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 3063 2.08% 87.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2761 1.87% 88.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 16265 11.02% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 147597 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 17512 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 22.065726 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 218.880570 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 17501 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 17512 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 17512 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.845477 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.774806 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 2.552021 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 17320 98.90% 98.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 149 0.85% 99.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 19 0.11% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 3 0.02% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 1 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 17512 # Writes before turning the bus around for reads system.physmem.totQLat 4304557750 # Total ticks spent queuing system.physmem.totMemAccLat 11550120250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1932150000 # Total ticks spent in databus transfers system.physmem.avgQLat 11139.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 29889.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 59.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 45.24 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 59.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 45.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing system.physmem.avgWrQLen 22.21 # Average write queue length when enqueuing system.physmem.readRowHits 317938 # Number of row buffer hits during reads system.physmem.writeRowHits 215878 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.17 # Row buffer hit rate for writes system.physmem.avgGap 612151.63 # Average gap between requests system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 570447360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 311256000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1528917000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 980987760 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 27259324560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 63572985495 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 194644842750 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 288868760925 # Total energy per rank (pJ) system.physmem_0.averagePower 692.148188 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 323251825500 # Time in different power states system.physmem_0.memoryStateTime::REF 13936260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 80164105500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 545007960 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 297375375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1484620800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 930178080 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 27259324560 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 61751757690 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 196242411000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 288510675465 # Total energy per rank (pJ) system.physmem_1.averagePower 691.290192 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 325923337000 # Time in different power states system.physmem_1.memoryStateTime::REF 13936260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 77492261000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 230114946 # Number of BP lookups system.cpu.branchPred.condPredicted 230114946 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 9743673 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 131512372 # Number of BTB lookups system.cpu.branchPred.BTBHits 128773549 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 97.917441 # BTB Hit Percentage system.cpu.branchPred.usedRAS 27735823 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1463178 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 834712892 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 185096351 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1269592650 # Number of instructions fetch has processed system.cpu.fetch.Branches 230114946 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 156509372 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 638356055 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 20228139 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 758 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 101258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 840387 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 2737 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 59 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 179448853 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 2721067 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed system.cpu.fetch.rateDist::samples 834511674 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.829795 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.382435 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 426826838 51.15% 51.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 33732277 4.04% 55.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 32850671 3.94% 59.13% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 33472631 4.01% 63.14% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 27169487 3.26% 66.39% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 27713856 3.32% 69.71% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 36968785 4.43% 74.14% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 33631474 4.03% 78.17% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 182145655 21.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 834511674 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.275682 # Number of branch fetches per cycle system.cpu.fetch.rate 1.520993 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 127578782 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 374998054 # Number of cycles decode is blocked system.cpu.decode.RunCycles 240442194 # Number of cycles decode is running system.cpu.decode.UnblockCycles 81378575 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 10114069 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2225413878 # Number of instructions handled by decode system.cpu.rename.SquashCycles 10114069 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 159657843 # Number of cycles rename is idle system.cpu.rename.BlockCycles 159891555 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 40940 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 285656025 # Number of cycles rename is running system.cpu.rename.UnblockCycles 219151242 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 2175196411 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 168463 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 136638961 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 24413812 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 48161068 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 2279427494 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 5501071808 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 3499111667 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 56998 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 665386640 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 3242 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 3006 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 415340463 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 528372676 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 209866939 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 239161343 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 72330795 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 2101128871 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 24703 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1826915153 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 401884 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 572164873 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 974203164 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24151 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 834511674 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.189203 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.071791 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 254614117 30.51% 30.51% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 125714590 15.06% 45.58% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 119295811 14.30% 59.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 111533246 13.37% 73.24% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 92303012 11.06% 84.30% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 61450543 7.36% 91.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 43061191 5.16% 96.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 19136018 2.29% 99.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 7403146 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 834511674 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 11328208 42.57% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.57% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 12223678 45.94% 88.51% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 3056537 11.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2713479 0.15% 0.15% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 1211223502 66.30% 66.45% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 389210 0.02% 66.47% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 3881037 0.21% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 41 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 435016626 23.81% 90.49% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 173690734 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1826915153 # Type of FU issued system.cpu.iq.rate 2.188675 # Inst issue rate system.cpu.iq.fu_busy_cnt 26608423 # FU busy when requested system.cpu.iq.fu_busy_rate 0.014565 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 4515318394 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2673578201 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1796830430 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 33893 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 72228 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7290 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 1850794442 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 15655 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 185328618 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 144273272 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 209540 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 385759 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 60706753 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 19758 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 975 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 10114069 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 106861853 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 6175689 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 2101153574 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 399268 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 528375429 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 209866939 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 7172 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1868361 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3423880 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 385759 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 5745481 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 4570970 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 10316451 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 1805502100 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 428802217 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 21413053 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 598985052 # number of memory reference insts executed system.cpu.iew.exec_branches 171767135 # Number of branches executed system.cpu.iew.exec_stores 170182835 # Number of stores executed system.cpu.iew.exec_rate 2.163022 # Inst execution rate system.cpu.iew.wb_sent 1802089057 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1796837720 # cumulative count of insts written-back system.cpu.iew.wb_producers 1367929108 # num instructions producing a value system.cpu.iew.wb_consumers 2089922877 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.152642 # insts written-back per cycle system.cpu.iew.wb_fanout 0.654536 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 572246174 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 9834163 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 756802524 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.020327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.547122 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 287869845 38.04% 38.04% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 175466926 23.19% 61.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 57310914 7.57% 68.80% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 86374049 11.41% 80.21% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 27151308 3.59% 83.80% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 27112039 3.58% 87.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 9778589 1.29% 88.67% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 8969993 1.19% 89.86% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 76768861 10.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 756802524 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262343 # Number of memory references committed system.cpu.commit.loads 384102157 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction system.cpu.commit.bw_lim_events 76768861 # number cycles where commit BW limit reached system.cpu.rob.rob_reads 2781268538 # The number of ROB reads system.cpu.rob.rob_writes 4280366942 # The number of ROB writes system.cpu.timesIdled 2320 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 201218 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.cpi 1.009476 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.009476 # CPI: Total CPI of All Threads system.cpu.ipc 0.990613 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.990613 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 2761875097 # number of integer regfile reads system.cpu.int_regfile_writes 1464994658 # number of integer regfile writes system.cpu.fp_regfile_reads 7611 # number of floating regfile reads system.cpu.fp_regfile_writes 469 # number of floating regfile writes system.cpu.cc_regfile_reads 600894464 # number of cc regfile reads system.cpu.cc_regfile_writes 409621609 # number of cc regfile writes system.cpu.misc_regfile_reads 990138198 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 2534436 # number of replacements system.cpu.dcache.tags.tagsinuse 4088.023395 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 387994908 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2538532 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 152.842236 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4088.023395 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998053 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998053 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 883 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3160 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 785123968 # Number of tag accesses system.cpu.dcache.tags.data_accesses 785123968 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 239346850 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 239346850 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148188204 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148188204 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 387535054 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 387535054 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 387535054 # number of overall hits system.cpu.dcache.overall_hits::total 387535054 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2785666 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2785666 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 971998 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 971998 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 3757664 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3757664 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3757664 # number of overall misses system.cpu.dcache.overall_misses::total 3757664 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 59489424500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 59489424500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 30574204499 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 30574204499 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 90063628999 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 90063628999 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 90063628999 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 90063628999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 242132516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 242132516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 391292718 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 391292718 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 391292718 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 391292718 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011505 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.011505 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006516 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.006516 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009603 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009603 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009603 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009603 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21355.548188 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 21355.548188 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31455.007622 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 31455.007622 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 23967.983566 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 23967.983566 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 23967.983566 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 23967.983566 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 10943 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 29 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1141 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.590710 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 9.666667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2332856 # number of writebacks system.cpu.dcache.writebacks::total 2332856 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017532 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1017532 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19229 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 19229 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1036761 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1036761 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1036761 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1036761 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768134 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1768134 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952769 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 952769 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2720903 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2720903 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2720903 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2720903 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33612540500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33612540500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29371438000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 29371438000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62983978500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 62983978500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62983978500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 62983978500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007302 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007302 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006388 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006388 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006954 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006954 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006954 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006954 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.177113 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.177113 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30827.449256 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30827.449256 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23148.189590 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 23148.189590 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23148.189590 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 23148.189590 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7110 # number of replacements system.cpu.icache.tags.tagsinuse 1052.499064 # Cycle average of tags in use system.cpu.icache.tags.total_refs 179252042 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8714 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20570.580904 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1052.499064 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.513916 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.513916 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1604 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 315 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1166 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 359088953 # Number of tag accesses system.cpu.icache.tags.data_accesses 359088953 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 179255052 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 179255052 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 179255052 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 179255052 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 179255052 # number of overall hits system.cpu.icache.overall_hits::total 179255052 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 193801 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 193801 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 193801 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 193801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 193801 # number of overall misses system.cpu.icache.overall_misses::total 193801 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 1254302498 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 1254302498 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 1254302498 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 1254302498 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 1254302498 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 1254302498 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 179448853 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 179448853 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 179448853 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 179448853 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 179448853 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 179448853 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001080 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001080 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001080 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001080 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001080 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001080 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6472.115717 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 6472.115717 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 6472.115717 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 6472.115717 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 6472.115717 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 6472.115717 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 986 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 65.733333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2552 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 2552 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 2552 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 2552 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 2552 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 2552 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 191249 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 191249 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 191249 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 191249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 191249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 191249 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 951599499 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 951599499 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 951599499 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 951599499 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 951599499 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 951599499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001066 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4975.709672 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4975.709672 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4975.709672 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 4975.709672 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4975.709672 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 4975.709672 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 354081 # number of replacements system.cpu.l2cache.tags.tagsinuse 29616.814988 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3900447 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 386444 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 10.093175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 197713230000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 20952.734169 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 255.019298 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 8409.061520 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.639427 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.256624 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.903833 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32363 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13367 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18670 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987640 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 43237048 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 43237048 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 2332856 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2332856 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1875 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1875 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 564106 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 564106 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5235 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 5235 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1591146 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 1591146 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 5235 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 2155252 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2160487 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5235 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2155252 # number of overall hits system.cpu.l2cache.overall_hits::total 2160487 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 180497 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 180497 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 206672 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206672 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3524 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 3524 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176608 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 176608 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 3524 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 383280 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 386804 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3524 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 383280 # number of overall misses system.cpu.l2cache.overall_misses::total 386804 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13495500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 13495500 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382667500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 16382667500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 285620500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 285620500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14214752500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 14214752500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 285620500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 30597420000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 30883040500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 285620500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 30597420000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 30883040500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 2332856 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2332856 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 182372 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 182372 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 770778 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 770778 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8759 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 8759 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1767754 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 1767754 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 8759 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2538532 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2547291 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 8759 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2538532 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2547291 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989719 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989719 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268134 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.268134 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.402329 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.402329 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099905 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099905 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.402329 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.150985 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.151849 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.402329 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151849 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 74.768556 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 74.768556 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79268.926124 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79268.926124 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81050.085131 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81050.085131 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80487.591162 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80487.591162 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81050.085131 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79830.463369 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 79841.574803 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81050.085131 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79830.463369 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 79841.574803 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 295028 # number of writebacks system.cpu.l2cache.writebacks::total 295028 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2046 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 2046 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 180497 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 180497 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206672 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206672 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3523 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3523 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176608 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176608 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3523 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 383280 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 386803 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3523 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 383280 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 386803 # number of overall MSHR misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3797038702 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3797038702 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14315947500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14315947500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 250334000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 250334000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12448672500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12448672500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250334000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26764620000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 27014954000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250334000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26764620000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 27014954000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989719 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989719 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268134 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268134 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.402215 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.402215 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099905 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099905 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.402215 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150985 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.151849 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.402215 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151849 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21036.575134 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21036.575134 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69268.926124 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69268.926124 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71057.053647 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71057.053647 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70487.591162 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70487.591162 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71057.053647 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69830.463369 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69841.635148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71057.053647 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69830.463369 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69841.635148 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 1959001 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2627884 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 256223 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 182372 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 182372 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 770778 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 770778 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 191249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767754 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206660 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7965180 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 8171840 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311768832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 312329280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 536571 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5807780 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.060967 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.239269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 5453699 93.90% 93.90% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 354081 6.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5807780 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5086087131 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 286877486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3898984570 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.trans_dist::ReadResp 180129 # Transaction distribution system.membus.trans_dist::Writeback 295028 # Transaction distribution system.membus.trans_dist::CleanEvict 57486 # Transaction distribution system.membus.trans_dist::UpgradeReq 180541 # Transaction distribution system.membus.trans_dist::UpgradeResp 180541 # Transaction distribution system.membus.trans_dist::ReadExReq 206628 # Transaction distribution system.membus.trans_dist::ReadExResp 206628 # Transaction distribution system.membus.trans_dist::ReadSharedReq 180130 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1487111 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1487111 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1487111 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43634240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43634240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 43634240 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 919813 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 919813 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 919813 # Request fanout histogram system.membus.reqLayer0.occupancy 2222161296 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2406907271 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ----------