---------- Begin Simulation Statistics ---------- sim_seconds 0.458513 # Number of seconds simulated sim_ticks 458512999500 # Number of ticks simulated final_tick 458512999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 75448 # Simulator instruction rate (inst/s) host_op_rate 139512 # Simulator op (including micro ops) rate (op/s) host_tick_rate 41836736 # Simulator tick rate (ticks/s) host_mem_usage 384056 # Number of bytes of host memory used host_seconds 10959.58 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 201856 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24474368 # Number of bytes read from this memory system.physmem.bytes_read::total 24676224 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 201856 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 201856 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 18792384 # Number of bytes written to this memory system.physmem.bytes_written::total 18792384 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3154 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 382412 # Number of read requests responded to by this memory system.physmem.num_reads::total 385566 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 293631 # Number of write requests responded to by this memory system.physmem.num_writes::total 293631 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 440241 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 53377697 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 53817938 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 440241 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 440241 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 40985499 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 40985499 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 40985499 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 440241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53377697 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 94803436 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 385568 # Number of read requests accepted system.physmem.writeReqs 293631 # Number of write requests accepted system.physmem.readBursts 385568 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 293631 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 24654400 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue system.physmem.bytesWritten 18790528 # Total number of bytes written to DRAM system.physmem.bytesReadSys 24676352 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 18792384 # Total written bytes from the system interface side system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 136756 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 24002 # Per bank write bursts system.physmem.perBankRdBursts::1 26346 # Per bank write bursts system.physmem.perBankRdBursts::2 24809 # Per bank write bursts system.physmem.perBankRdBursts::3 24514 # Per bank write bursts system.physmem.perBankRdBursts::4 23427 # Per bank write bursts system.physmem.perBankRdBursts::5 23679 # Per bank write bursts system.physmem.perBankRdBursts::6 24437 # Per bank write bursts system.physmem.perBankRdBursts::7 24240 # Per bank write bursts system.physmem.perBankRdBursts::8 23642 # Per bank write bursts system.physmem.perBankRdBursts::9 23833 # Per bank write bursts system.physmem.perBankRdBursts::10 24803 # Per bank write bursts system.physmem.perBankRdBursts::11 23968 # Per bank write bursts system.physmem.perBankRdBursts::12 23115 # Per bank write bursts system.physmem.perBankRdBursts::13 22838 # Per bank write bursts system.physmem.perBankRdBursts::14 23649 # Per bank write bursts system.physmem.perBankRdBursts::15 23923 # Per bank write bursts system.physmem.perBankWrBursts::0 18533 # Per bank write bursts system.physmem.perBankWrBursts::1 19811 # Per bank write bursts system.physmem.perBankWrBursts::2 18961 # Per bank write bursts system.physmem.perBankWrBursts::3 18917 # Per bank write bursts system.physmem.perBankWrBursts::4 18087 # Per bank write bursts system.physmem.perBankWrBursts::5 18414 # Per bank write bursts system.physmem.perBankWrBursts::6 18972 # Per bank write bursts system.physmem.perBankWrBursts::7 18944 # Per bank write bursts system.physmem.perBankWrBursts::8 18562 # Per bank write bursts system.physmem.perBankWrBursts::9 18116 # Per bank write bursts system.physmem.perBankWrBursts::10 18832 # Per bank write bursts system.physmem.perBankWrBursts::11 17714 # Per bank write bursts system.physmem.perBankWrBursts::12 17339 # Per bank write bursts system.physmem.perBankWrBursts::13 16924 # Per bank write bursts system.physmem.perBankWrBursts::14 17682 # Per bank write bursts system.physmem.perBankWrBursts::15 17794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 458512983000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 385568 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 293631 # Write request sizes (log2) system.physmem.rdQLenPdf::0 380696 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 4209 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 6409 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 6808 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 16841 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 17378 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17536 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 17527 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17556 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17556 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 17549 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 17549 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 17561 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 17726 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 17619 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17583 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 17768 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 17495 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 17431 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 146743 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 296.052173 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 174.726027 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 323.657452 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 54056 36.84% 36.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 40668 27.71% 64.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 13398 9.13% 73.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 7234 4.93% 78.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5377 3.66% 82.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3862 2.63% 84.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 3026 2.06% 86.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2779 1.89% 88.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 16343 11.14% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 146743 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 17400 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 22.138621 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 209.351810 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 17386 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 17400 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 17400 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.873678 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.805032 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 2.403017 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 17211 98.91% 98.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 144 0.83% 99.74% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 22 0.13% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 3 0.02% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 2 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 2 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 2 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 2 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 17400 # Writes before turning the bus around for reads system.physmem.totQLat 4188887000 # Total ticks spent queuing system.physmem.totMemAccLat 11411855750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1926125000 # Total ticks spent in databus transfers system.physmem.avgQLat 10873.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 29623.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 53.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 40.98 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 53.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 40.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing system.physmem.avgWrQLen 21.82 # Average write queue length when enqueuing system.physmem.readRowHits 316892 # Number of row buffer hits during reads system.physmem.writeRowHits 215180 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes system.physmem.avgGap 675079.00 # Average gap between requests system.physmem.pageHitRate 78.38 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 318092069500 # Time in different power states system.physmem.memoryStateTime::REF 15310620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 125106520750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 94803436 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 178732 # Transaction distribution system.membus.trans_dist::ReadResp 178730 # Transaction distribution system.membus.trans_dist::Writeback 293631 # Transaction distribution system.membus.trans_dist::UpgradeReq 136756 # Transaction distribution system.membus.trans_dist::UpgradeResp 136756 # Transaction distribution system.membus.trans_dist::ReadExReq 206836 # Transaction distribution system.membus.trans_dist::ReadExResp 206836 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1338277 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1338277 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1338277 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43468608 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43468608 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 43468608 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 43468608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 3392871500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 3899245261 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 205578466 # Number of BP lookups system.cpu.branchPred.condPredicted 205578466 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 9901534 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 117029392 # Number of BTB lookups system.cpu.branchPred.BTBHits 114680074 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 97.992540 # BTB Hit Percentage system.cpu.branchPred.usedRAS 25067972 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1805738 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 917184655 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 167397549 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1131555944 # Number of instructions fetch has processed system.cpu.fetch.Branches 205578466 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 139748046 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 352223186 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 71069558 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 304555909 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 47998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 253720 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 161997167 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 2518791 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 885395126 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.377906 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.324319 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 537236750 60.68% 60.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 23398648 2.64% 63.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 25254202 2.85% 66.17% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 27875613 3.15% 69.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 17735392 2.00% 71.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 22920767 2.59% 73.91% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 29423422 3.32% 77.24% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 26636426 3.01% 80.24% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 174913906 19.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 885395126 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.224141 # Number of branch fetches per cycle system.cpu.fetch.rate 1.233728 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 222654978 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 259567656 # Number of cycles decode is blocked system.cpu.decode.RunCycles 295344640 # Number of cycles decode is running system.cpu.decode.UnblockCycles 46911146 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 60916706 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2071122559 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 60916706 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 256101136 # Number of cycles rename is idle system.cpu.rename.BlockCycles 115302026 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 17668 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 306678759 # Number of cycles rename is running system.cpu.rename.UnblockCycles 146378831 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 2034998452 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 20313 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 24722090 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 106340501 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2137925960 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 5150186774 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 3273147321 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 41991 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 523885106 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1288 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 1219 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 345625652 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 495840221 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 194409464 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 195351813 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 54649414 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 1975275020 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13975 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1772033700 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 489443 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 441377933 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 734704744 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13423 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 885395126 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.001404 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.883479 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 268930520 30.37% 30.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 151513258 17.11% 47.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 137639902 15.55% 63.03% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 131544541 14.86% 77.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 91741507 10.36% 88.25% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 55934371 6.32% 94.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 34425935 3.89% 98.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 11907214 1.34% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1757878 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 885395126 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4908226 32.44% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 7617033 50.35% 82.79% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 2603803 17.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2622809 0.15% 0.15% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 1165654727 65.78% 65.93% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 353604 0.02% 65.95% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 3880790 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 51 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 429257765 24.22% 90.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 170263954 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1772033700 # Type of FU issued system.cpu.iq.rate 1.932036 # Inst issue rate system.cpu.iq.fu_busy_cnt 15129062 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008538 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 4445065609 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2416869316 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1744809668 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15422 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 52952 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 3677 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 1784532643 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7310 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 172476568 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 111739174 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 389536 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 327115 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 45249278 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 14923 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 606 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 60916706 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 67511680 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 7160873 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 1975288995 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 782662 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 495841331 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 194409464 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 3475 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4447984 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 83109 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 327115 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 5905027 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 4421064 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 10326091 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 1752917365 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 424127416 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 19116335 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 590948442 # number of memory reference insts executed system.cpu.iew.exec_branches 167460417 # Number of branches executed system.cpu.iew.exec_stores 166821026 # Number of stores executed system.cpu.iew.exec_rate 1.911194 # Inst execution rate system.cpu.iew.wb_sent 1749660983 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1744813345 # cumulative count of insts written-back system.cpu.iew.wb_producers 1324821434 # num instructions producing a value system.cpu.iew.wb_consumers 1945562364 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.902358 # insts written-back per cycle system.cpu.iew.wb_fanout 0.680945 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 446329306 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 9930052 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 824478420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.854492 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.436428 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 332514113 40.33% 40.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 193200456 23.43% 63.76% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 63249703 7.67% 71.43% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 92516022 11.22% 82.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 24944995 3.03% 85.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 27441019 3.33% 89.01% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 9353308 1.13% 90.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 11434582 1.39% 91.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 69824222 8.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 824478420 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262343 # Number of memory references committed system.cpu.commit.loads 384102157 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction system.cpu.commit.bw_lim_events 69824222 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 2729972205 # The number of ROB reads system.cpu.rob.rob_writes 4011712950 # The number of ROB writes system.cpu.timesIdled 3360559 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 31789529 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.cpi 1.109215 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.109215 # CPI: Total CPI of All Threads system.cpu.ipc 0.901538 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.901538 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 2716307472 # number of integer regfile reads system.cpu.int_regfile_writes 1420359444 # number of integer regfile writes system.cpu.fp_regfile_reads 3689 # number of floating regfile reads system.cpu.fp_regfile_writes 68 # number of floating regfile writes system.cpu.cc_regfile_reads 597203936 # number of cc regfile reads system.cpu.cc_regfile_writes 405421760 # number of cc regfile writes system.cpu.misc_regfile_reads 964666021 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 699262879 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1907311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1907308 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2330645 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 138184 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 138184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 771752 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 771752 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 151977 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7674879 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7826856 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 438272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311332928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 311771200 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 311771200 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 8849920 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4908820525 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 218162491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3952575691 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 5306 # number of replacements system.cpu.icache.tags.tagsinuse 1035.768369 # Cycle average of tags in use system.cpu.icache.tags.total_refs 161848074 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6885 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 23507.345534 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1035.768369 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.505746 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.505746 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1579 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 250 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1221 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.770996 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 324139462 # Number of tag accesses system.cpu.icache.tags.data_accesses 324139462 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 161850058 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 161850058 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 161850058 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 161850058 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 161850058 # number of overall hits system.cpu.icache.overall_hits::total 161850058 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 147109 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 147109 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 147109 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 147109 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 147109 # number of overall misses system.cpu.icache.overall_misses::total 147109 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 933905482 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 933905482 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 933905482 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 933905482 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 933905482 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 933905482 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 161997167 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 161997167 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 161997167 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 161997167 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 161997167 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 161997167 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000908 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000908 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000908 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000908 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000908 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000908 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.391207 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 6348.391207 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 6348.391207 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 6348.391207 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 55.555556 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1980 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 1980 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 1980 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 1980 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1980 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1980 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 145129 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 145129 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 145129 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 145129 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 145129 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 145129 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558373758 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 558373758 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558373758 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 558373758 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558373758 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 558373758 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000896 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000896 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000896 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3847.430617 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.430617 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 352885 # number of replacements system.cpu.l2cache.tags.tagsinuse 29666.734110 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3697072 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 385254 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.596453 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 198759422000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 21121.357308 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 222.494139 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.882663 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.644573 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006790 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.253994 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.905357 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32369 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11715 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20331 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987823 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41235634 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41235634 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 3694 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1586604 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1590298 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2330645 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2330645 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1450 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1450 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 564894 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 564894 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 3694 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 2151498 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2155192 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3694 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2151498 # number of overall hits system.cpu.l2cache.overall_hits::total 2155192 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3155 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 175578 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 178733 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 136734 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 136734 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 206858 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206858 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3155 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 382436 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 385591 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3155 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 382436 # number of overall misses system.cpu.l2cache.overall_misses::total 385591 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234254750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12845252206 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 13079506956 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6557218 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 6557218 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14818754478 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 14818754478 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 234254750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 27664006684 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 27898261434 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 234254750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 27664006684 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 27898261434 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6849 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1762182 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1769031 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2330645 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2330645 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 138184 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 138184 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 771752 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 771752 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 6849 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2533934 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2540783 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 6849 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2533934 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2540783 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.460651 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099637 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.101034 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989507 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989507 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268037 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.268037 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.460651 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.150926 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.151761 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.460651 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150926 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151761 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74248.732171 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73159.804793 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 73179.026570 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.956017 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.956017 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71637.328399 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71637.328399 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74248.732171 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72336.303810 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 72351.951768 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74248.732171 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72336.303810 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 72351.951768 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 293631 # number of writebacks system.cpu.l2cache.writebacks::total 293631 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3155 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175578 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 178733 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 136734 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 136734 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206858 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206858 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3155 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 382436 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 385591 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3155 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 382436 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 385591 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 194803750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10608113206 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10802916956 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1371755972 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1371755972 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12195917522 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12195917522 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194803750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22804030728 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 22998834478 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194803750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22804030728 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 22998834478 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099637 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989507 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989507 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268037 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268037 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.151761 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151761 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61744.453249 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60418.236943 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60441.647351 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.296079 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.296079 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58957.920516 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58957.920516 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 2529836 # number of replacements system.cpu.dcache.tags.tagsinuse 4088.247019 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 396128893 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2533932 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 156.329725 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1791176250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247019 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 741 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3311 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 801380064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 801380064 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 247376910 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 247376910 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148233547 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148233547 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 395610457 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 395610457 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 395610457 # number of overall hits system.cpu.dcache.overall_hits::total 395610457 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2885954 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2885954 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 926655 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 926655 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 3812609 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3812609 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3812609 # number of overall misses system.cpu.dcache.overall_misses::total 3812609 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 57615846746 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 57615846746 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 26561972442 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 26561972442 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 84177819188 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 84177819188 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 84177819188 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 84177819188 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250262864 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250262864 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 399423066 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 399423066 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 399423066 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 399423066 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011532 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.011532 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006212 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.006212 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19964.229072 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19964.229072 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28664.359920 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 28664.359920 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 22078.796747 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 22078.796747 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 6778 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 684 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.909357 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2330645 # number of writebacks system.cpu.dcache.writebacks::total 2330645 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123517 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1123517 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16974 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 16974 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1140491 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1140491 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1140491 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1140491 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762437 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1762437 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909681 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 909681 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2672118 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2672118 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2672118 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2672118 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30508505001 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 30508505001 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24438286308 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 24438286308 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54946791309 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 54946791309 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54946791309 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 54946791309 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007042 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007042 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006690 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006690 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17310.408827 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17310.408827 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26864.677077 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26864.677077 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------