---------- Begin Simulation Statistics ---------- sim_seconds 0.226866 # Number of seconds simulated sim_ticks 226865901500 # Number of ticks simulated final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 324605 # Simulator instruction rate (inst/s) host_op_rate 324605 # Simulator op (including micro ops) rate (op/s) host_tick_rate 184721178 # Simulator tick rate (ticks/s) host_mem_usage 301676 # Number of bytes of host memory used host_seconds 1228.15 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 551 # Per bank write bursts system.physmem.perBankRdBursts::1 676 # Per bank write bursts system.physmem.perBankRdBursts::2 471 # Per bank write bursts system.physmem.perBankRdBursts::3 633 # Per bank write bursts system.physmem.perBankRdBursts::4 475 # Per bank write bursts system.physmem.perBankRdBursts::5 478 # Per bank write bursts system.physmem.perBankRdBursts::6 563 # Per bank write bursts system.physmem.perBankRdBursts::7 560 # Per bank write bursts system.physmem.perBankRdBursts::8 469 # Per bank write bursts system.physmem.perBankRdBursts::9 437 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts system.physmem.perBankRdBursts::11 323 # Per bank write bursts system.physmem.perBankRdBursts::12 430 # Per bank write bursts system.physmem.perBankRdBursts::13 556 # Per bank write bursts system.physmem.perBankRdBursts::14 473 # Per bank write bursts system.physmem.perBankRdBursts::15 424 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts system.physmem.perBankWrBursts::4 0 # Per bank write bursts system.physmem.perBankWrBursts::5 0 # Per bank write bursts system.physmem.perBankWrBursts::6 0 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts system.physmem.perBankWrBursts::10 0 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 226865813000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 7873 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation system.physmem.totQLat 54380250 # Total ticks spent queuing system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 6303 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28815675.47 # Average gap between requests system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ) system.physmem_0.averagePower 668.682686 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ) system.physmem_1.averagePower 668.490749 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 46273750 # Number of BP lookups system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 95585469 # DTB read hits system.cpu.dtb.read_misses 115 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 95585584 # DTB read accesses system.cpu.dtb.write_hits 73606437 # DTB write hits system.cpu.dtb.write_misses 857 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 73607294 # DTB write accesses system.cpu.dtb.data_hits 169191906 # DTB hits system.cpu.dtb.data_misses 972 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 169192878 # DTB accesses system.cpu.itb.fetch_hits 98781212 # ITB hits system.cpu.itb.fetch_misses 1236 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_accesses 98782448 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls system.cpu.numCycles 453731803 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.138129 # CPI: cycles per instruction system.cpu.ipc 0.878635 # IPC: instructions per cycle system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits system.cpu.dcache.overall_hits::total 168028622 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses system.cpu.dcache.overall_misses::total 7112 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 168035734 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 168035734 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits system.cpu.icache.overall_hits::total 98776038 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses system.cpu.icache.overall_misses::total 5174 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 320697250 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 320697250 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 320697250 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 320697250 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 320697250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 320697250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 98781212 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 98781212 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 98781212 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61982.460379 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 61982.460379 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 61982.460379 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 61982.460379 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5174 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 5174 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 5174 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311289750 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 311289750 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311289750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 311289750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311289750 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 311289750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60164.234635 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60164.234635 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4426.526265 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 373.084024 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.466195 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 641.976046 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 88415 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 88415 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 1279 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1466 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1279 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits system.cpu.l2cache.overall_hits::total 1466 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3895 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 841 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4736 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 292685750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 68346250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 361032000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 236421750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 236421750 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 292685750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 304768000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 597453750 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 292685750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 304768000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 597453750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 5174 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9339 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 5174 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9339 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752802 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.771210 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752802 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75143.966624 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81267.835910 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 76231.418919 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75365.556264 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75365.556264 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 75886.415598 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 75886.415598 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3895 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 4736 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 243926750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 57790750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301717500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 197209250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 197209250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 243926750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 255000000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 498926750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 243926750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 255000000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 498926750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10348 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 19332 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 639552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 9993 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 9993 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 7873 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ----------