---------- Begin Simulation Statistics ---------- sim_seconds 0.112624 # Number of seconds simulated sim_ticks 112623767500 # Number of ticks simulated final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 123996 # Simulator instruction rate (inst/s) host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) host_tick_rate 51146556 # Simulator tick rate (ticks/s) host_mem_usage 325020 # Number of bytes of host memory used host_seconds 2201.98 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory system.physmem.bytes_read::total 469120 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7330 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 589 # Per bank write bursts system.physmem.perBankRdBursts::1 789 # Per bank write bursts system.physmem.perBankRdBursts::2 601 # Per bank write bursts system.physmem.perBankRdBursts::3 519 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts system.physmem.perBankRdBursts::7 257 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 291 # Per bank write bursts system.physmem.perBankRdBursts::10 316 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts system.physmem.perBankRdBursts::14 615 # Per bank write bursts system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts system.physmem.perBankWrBursts::4 0 # Per bank write bursts system.physmem.perBankWrBursts::5 0 # Per bank write bursts system.physmem.perBankWrBursts::6 0 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts system.physmem.perBankWrBursts::10 0 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 112623613500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 7330 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation system.physmem.totQLat 100359280 # Total ticks spent queuing system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 5950 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 15364749.45 # Average gap between requests system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) system.physmem_0.averagePower 669.161673 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) system.physmem_1.averagePower 669.228880 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 37762202 # Number of BP lookups system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls system.cpu.numCycles 225247536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued system.cpu.iq.rate 1.537271 # Inst issue rate system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 868 # number of nop insts executed system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed system.cpu.iew.exec_branches 31752029 # Number of branches executed system.cpu.iew.exec_stores 84582492 # Number of stores executed system.cpu.iew.exec_rate 1.519678 # Inst execution rate system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back system.cpu.iew.wb_producers 153542130 # num instructions producing a value system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037831 # Number of instructions committed system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168107892 # Number of memory references committed system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed system.cpu.commit.branches 30563525 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 561683936 # The number of ROB reads system.cpu.rob.rob_writes 705354391 # The number of ROB writes system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037219 # Number of Instructions Simulated system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 331186150 # number of integer regfile reads system.cpu.int_regfile_writes 136908474 # number of integer regfile writes system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes system.cpu.dcache.tags.replacements 1533739 # number of replacements system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits system.cpu.dcache.overall_hits::total 163782096 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses system.cpu.dcache.overall_misses::total 3771380 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks system.cpu.dcache.writebacks::total 966281 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 715275 # number of replacements system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 315060000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.840362 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999688 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999688 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 68 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 178935006 # Number of tag accesses system.cpu.icache.tags.data_accesses 178935006 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 88389408 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88389408 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88389408 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 88389408 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 88389408 # number of overall hits system.cpu.icache.overall_hits::total 88389408 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 720201 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 720201 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 720201 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 720201 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 720201 # number of overall misses system.cpu.icache.overall_misses::total 720201 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 5943843584 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 5943843584 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 5943843584 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 5943843584 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 5943843584 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 5943843584 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 89109609 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 89109609 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 89109609 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 89109609 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 89109609 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 89109609 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008082 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.008082 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.008082 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.008082 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.008082 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.008082 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8253.034339 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 8253.034339 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 8253.034339 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 8253.034339 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 51882 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 52 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1935 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 26.812403 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 17.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4413 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 4413 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 4413 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 4413 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 4413 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 4413 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715788 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 715788 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 715788 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 715788 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 715788 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 715788 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4812391061 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 4812391061 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4812391061 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 4812391061 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4812391061 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 4812391061 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008033 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008033 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6723.207236 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6723.207236 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 406270 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 406521 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 191 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 28111 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 5993.755359 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2805980 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 7304 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 384.170318 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 2575.357550 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.182450 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 614.569855 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 123.645504 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.157187 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163585 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.037510 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007547 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.365830 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 515 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 6789 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5746 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031433 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414368 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 51674481 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 51674481 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 711950 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1312705 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2024655 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 966281 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 966281 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 219662 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 219662 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 711950 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1532367 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2244317 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 711950 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1532367 # number of overall hits system.cpu.l2cache.overall_hits::total 2244317 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2934 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1059 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3993 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 825 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 825 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2934 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1884 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 4818 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2934 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1884 # number of overall misses system.cpu.l2cache.overall_misses::total 4818 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 179619250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70145000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 249764250 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 50824468 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 50824468 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 179619250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 120969468 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 300588718 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 179619250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 120969468 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 300588718 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 714884 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1313764 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2028648 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 966281 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 966281 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 220487 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 220487 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 714884 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1534251 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2249135 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 714884 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1534251 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2249135 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004104 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001968 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003742 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.003742 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004104 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.001228 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.002142 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004104 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.001228 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.002142 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61219.921609 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66237.016053 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 62550.525920 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61605.415758 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61605.415758 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 62388.691988 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 62388.691988 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 98 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::total 98 # number of ReadExReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 131 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 131 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 142 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1026 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 3949 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30530 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 30530 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59960500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 213858750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 204942291 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41351500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41351500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 153898250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101312000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 33002 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 6603 # Transaction distribution system.membus.trans_dist::ReadResp 6603 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 727 # Transaction distribution system.membus.trans_dist::ReadExResp 727 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 7331 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7331 # Request fanout histogram system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ----------