---------- Begin Simulation Statistics ---------- sim_seconds 0.022637 # Number of seconds simulated sim_ticks 22637068500 # Number of ticks simulated final_tick 22637068500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 222882 # Simulator instruction rate (inst/s) host_op_rate 222882 # Simulator op (including micro ops) rate (op/s) host_tick_rate 63391012 # Simulator tick rate (ticks/s) host_mem_usage 306268 # Number of bytes of host memory used host_seconds 357.10 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 472384 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10153088 # Number of bytes read from this memory system.physmem.bytes_read::total 10625472 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 472384 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 472384 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7318784 # Number of bytes written to this memory system.physmem.bytes_written::total 7318784 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 7381 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158642 # Number of read requests responded to by this memory system.physmem.num_reads::total 166023 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114356 # Number of write requests responded to by this memory system.physmem.num_writes::total 114356 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 20867720 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 448516026 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 469383746 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 20867720 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 20867720 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 323309708 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 323309708 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 323309708 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 20867720 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 448516026 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 792693453 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 166023 # Number of read requests accepted system.physmem.writeReqs 114356 # Number of write requests accepted system.physmem.readBursts 166023 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 114356 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 10625216 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue system.physmem.bytesWritten 7317504 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10625472 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7318784 # Total written bytes from the system interface side system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10427 # Per bank write bursts system.physmem.perBankRdBursts::1 10469 # Per bank write bursts system.physmem.perBankRdBursts::2 10285 # Per bank write bursts system.physmem.perBankRdBursts::3 10058 # Per bank write bursts system.physmem.perBankRdBursts::4 10410 # Per bank write bursts system.physmem.perBankRdBursts::5 10383 # Per bank write bursts system.physmem.perBankRdBursts::6 9823 # Per bank write bursts system.physmem.perBankRdBursts::7 10285 # Per bank write bursts system.physmem.perBankRdBursts::8 10562 # Per bank write bursts system.physmem.perBankRdBursts::9 10635 # Per bank write bursts system.physmem.perBankRdBursts::10 10512 # Per bank write bursts system.physmem.perBankRdBursts::11 10227 # Per bank write bursts system.physmem.perBankRdBursts::12 10266 # Per bank write bursts system.physmem.perBankRdBursts::13 10590 # Per bank write bursts system.physmem.perBankRdBursts::14 10475 # Per bank write bursts system.physmem.perBankRdBursts::15 10612 # Per bank write bursts system.physmem.perBankWrBursts::0 7161 # Per bank write bursts system.physmem.perBankWrBursts::1 7270 # Per bank write bursts system.physmem.perBankWrBursts::2 7294 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts system.physmem.perBankWrBursts::5 7175 # Per bank write bursts system.physmem.perBankWrBursts::6 6835 # Per bank write bursts system.physmem.perBankWrBursts::7 7095 # Per bank write bursts system.physmem.perBankWrBursts::8 7221 # Per bank write bursts system.physmem.perBankWrBursts::9 6995 # Per bank write bursts system.physmem.perBankWrBursts::10 7100 # Per bank write bursts system.physmem.perBankWrBursts::11 6989 # Per bank write bursts system.physmem.perBankWrBursts::12 6993 # Per bank write bursts system.physmem.perBankWrBursts::13 7294 # Per bank write bursts system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 22637037500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 166023 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 114356 # Write request sizes (log2) system.physmem.rdQLenPdf::0 52265 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 42988 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 38514 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 32235 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 814 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1941 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4841 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6515 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6908 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 7305 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 7526 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7916 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 7717 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 8226 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 10106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 8309 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 9772 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 8092 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 382 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 108 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 52301 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 343.050573 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 202.162039 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 342.313279 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 18282 34.96% 34.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 10576 20.22% 55.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 5922 11.32% 66.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2988 5.71% 72.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3062 5.85% 78.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1483 2.84% 80.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1989 3.80% 84.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1021 1.95% 86.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6978 13.34% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 52301 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 23.736917 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 336.159441 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 6991 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.347727 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.319415 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 1.025091 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 6123 87.55% 87.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 26 0.37% 87.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 468 6.69% 94.61% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 194 2.77% 97.38% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 92 1.32% 98.70% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 55 0.79% 99.49% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 18 0.26% 99.74% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 10 0.14% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 6 0.09% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads system.physmem.totQLat 5783499750 # Total ticks spent queuing system.physmem.totMemAccLat 8896356000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 830095000 # Total ticks spent in databus transfers system.physmem.avgQLat 34836.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 53586.37 # Average memory access latency per DRAM burst system.physmem.avgRdBW 469.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 323.25 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 469.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 323.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 6.19 # Data bus utilization in percentage system.physmem.busUtilRead 3.67 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 2.53 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing system.physmem.readRowHits 145949 # Number of row buffer hits during reads system.physmem.writeRowHits 82096 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes system.physmem.avgGap 80737.28 # Average gap between requests system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 190852200 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 104135625 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 640543800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 368925840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 6748287570 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 7661408250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 17192537205 # Total energy per rank (pJ) system.physmem_0.averagePower 759.557739 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12661521500 # Time in different power states system.physmem_0.memoryStateTime::REF 755820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 9217738000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 204354360 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 111502875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 654108000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 6845140260 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 7576424250 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 17241677745 # Total energy per rank (pJ) system.physmem_1.averagePower 761.730174 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 12521267250 # Time in different power states system.physmem_1.memoryStateTime::REF 755820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 9357815250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 16666171 # Number of BP lookups system.cpu.branchPred.condPredicted 10777513 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 373740 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 11097684 # Number of BTB lookups system.cpu.branchPred.BTBHits 7405754 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 66.732428 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1996658 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2898 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 22620977 # DTB read hits system.cpu.dtb.read_misses 226849 # DTB read misses system.cpu.dtb.read_acv 27 # DTB read access violations system.cpu.dtb.read_accesses 22847826 # DTB read accesses system.cpu.dtb.write_hits 15870488 # DTB write hits system.cpu.dtb.write_misses 45057 # DTB write misses system.cpu.dtb.write_acv 4 # DTB write access violations system.cpu.dtb.write_accesses 15915545 # DTB write accesses system.cpu.dtb.data_hits 38491465 # DTB hits system.cpu.dtb.data_misses 271906 # DTB misses system.cpu.dtb.data_acv 31 # DTB access violations system.cpu.dtb.data_accesses 38763371 # DTB accesses system.cpu.itb.fetch_hits 13971550 # ITB hits system.cpu.itb.fetch_misses 35700 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_accesses 14007250 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls system.cpu.numCycles 45274140 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 15840684 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 106412182 # Number of instructions fetch has processed system.cpu.fetch.Branches 16666171 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9402412 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 27820247 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 987192 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 787 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 5202 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 343767 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 13971550 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 209132 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed system.cpu.fetch.rateDist::samples 44504386 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.391049 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.126296 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 24724412 55.56% 55.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 1545163 3.47% 59.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1406842 3.16% 62.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1520478 3.42% 65.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 4242713 9.53% 75.14% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 1851895 4.16% 79.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 685374 1.54% 80.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1070742 2.41% 83.24% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 7456767 16.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 44504386 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.368117 # Number of branch fetches per cycle system.cpu.fetch.rate 2.350397 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 15190182 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 9797968 # Number of cycles decode is blocked system.cpu.decode.RunCycles 18517517 # Number of cycles decode is running system.cpu.decode.UnblockCycles 603822 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 394897 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3753615 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 100898 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 104278713 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 316536 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 394897 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 15562376 # Number of cycles rename is idle system.cpu.rename.BlockCycles 4515044 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 96153 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 18732590 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5203326 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 103086111 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 6702 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 93508 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 341438 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 4700364 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 62061981 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 124384146 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 124055114 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 329031 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 9515100 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 5718 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2349661 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 23316234 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 16465365 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1246740 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 545757 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 91441079 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 5553 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 89167924 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 83024 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 11854875 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 4801848 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 970 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 44504386 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.003576 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.243462 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 17850579 40.11% 40.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 5788896 13.01% 53.12% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 5155949 11.59% 64.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 4393297 9.87% 74.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 4359248 9.80% 84.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 2645472 5.94% 90.31% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1941559 4.36% 94.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1381555 3.10% 97.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 987831 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 44504386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 244058 9.64% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1174802 46.40% 56.04% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 1112961 43.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 49705550 55.74% 55.74% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 44198 0.05% 55.79% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.79% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 121960 0.14% 55.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 121539 0.14% 56.07% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.07% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 39076 0.04% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.11% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 23058691 25.86% 81.97% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 16076765 18.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 89167924 # Type of FU issued system.cpu.iq.rate 1.969511 # Inst issue rate system.cpu.iq.fu_busy_cnt 2531821 # FU busy when requested system.cpu.iq.fu_busy_rate 0.028394 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 224839378 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 102887543 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 87218101 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 615701 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 435266 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 300894 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 91391726 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 308019 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1669932 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 3039596 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21688 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 1851988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3150 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 205518 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 394897 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1352665 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 2733681 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 100982224 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 167502 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 23316234 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16465365 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 5553 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3853 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2732159 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21688 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 162395 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 158558 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 320953 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 88354535 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 22848688 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 813389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9535592 # number of nop insts executed system.cpu.iew.exec_refs 38764588 # number of memory reference insts executed system.cpu.iew.exec_branches 15181336 # Number of branches executed system.cpu.iew.exec_stores 15915900 # Number of stores executed system.cpu.iew.exec_rate 1.951545 # Inst execution rate system.cpu.iew.wb_sent 87941007 # cumulative count of insts sent to commit system.cpu.iew.wb_count 87518995 # cumulative count of insts written-back system.cpu.iew.wb_producers 33890392 # num instructions producing a value system.cpu.iew.wb_consumers 44346264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.933090 # insts written-back per cycle system.cpu.iew.wb_fanout 0.764222 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 9432406 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 275041 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 43112835 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.049057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.870632 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 21537439 49.96% 49.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 6339258 14.70% 64.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 2938097 6.81% 71.47% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 1767481 4.10% 75.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1703049 3.95% 79.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1136594 2.64% 82.16% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1201073 2.79% 84.95% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 797579 1.85% 86.80% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 5692265 13.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 43112835 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed system.cpu.commit.loads 20276638 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 13754477 # Number of branches committed system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction system.cpu.commit.bw_lim_events 5692265 # number cycles where commit BW limit reached system.cpu.rob.rob_reads 133876306 # The number of ROB reads system.cpu.rob.rob_writes 196941310 # The number of ROB writes system.cpu.timesIdled 47582 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 769754 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.568830 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.568830 # CPI: Total CPI of All Threads system.cpu.ipc 1.757996 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.757996 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 116950893 # number of integer regfile reads system.cpu.int_regfile_writes 57974920 # number of integer regfile writes system.cpu.fp_regfile_reads 255771 # number of floating regfile reads system.cpu.fp_regfile_writes 241359 # number of floating regfile writes system.cpu.misc_regfile_reads 38164 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 201397 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.850359 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34098493 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 205493 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 165.935059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 231077500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4070.850359 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993860 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993860 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2777 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1229 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 71045365 # Number of tag accesses system.cpu.dcache.tags.data_accesses 71045365 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 20537317 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20537317 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13561115 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 13561115 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.demand_hits::cpu.data 34098432 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 34098432 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 34098432 # number of overall hits system.cpu.dcache.overall_hits::total 34098432 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 269180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 269180 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1052262 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1052262 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 1321442 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1321442 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1321442 # number of overall misses system.cpu.dcache.overall_misses::total 1321442 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 17386725500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 17386725500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 89260696666 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 89260696666 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 106647422166 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 106647422166 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 106647422166 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 106647422166 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20806497 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20806497 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 35419874 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 35419874 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 35419874 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 35419874 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012937 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012937 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072007 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.072007 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016129 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016129 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.037308 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.037308 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037308 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037308 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64591.446244 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 64591.446244 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84827.444749 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 84827.444749 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 80705.337174 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 80705.337174 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 6894813 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 88842 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.607584 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168840 # number of writebacks system.cpu.dcache.writebacks::total 168840 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207085 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 207085 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908865 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 908865 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1115950 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1115950 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1115950 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1115950 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62095 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 62095 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 205492 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 205492 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 205492 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 205492 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3215385000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 3215385000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14267732202 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 14267732202 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483117202 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 17483117202 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17483117202 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 17483117202 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.016129 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.016129 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005802 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005802 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005802 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005802 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51781.705451 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51781.705451 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99498.122011 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99498.122011 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98000 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85079.308207 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 85079.308207 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85079.308207 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 85079.308207 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 93160 # number of replacements system.cpu.icache.tags.tagsinuse 1916.318628 # Cycle average of tags in use system.cpu.icache.tags.total_refs 13863089 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 95208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 145.608447 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 19085068500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1916.318628 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.935702 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.935702 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1486 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 371 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 28038306 # Number of tag accesses system.cpu.icache.tags.data_accesses 28038306 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 13863089 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13863089 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13863089 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 13863089 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 13863089 # number of overall hits system.cpu.icache.overall_hits::total 13863089 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 108460 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 108460 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 108460 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 108460 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 108460 # number of overall misses system.cpu.icache.overall_misses::total 108460 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 2048888998 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 2048888998 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 2048888998 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 2048888998 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 2048888998 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 2048888998 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 13971549 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 13971549 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 13971549 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 13971549 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 13971549 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13971549 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007763 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.007763 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.007763 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.007763 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.007763 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.007763 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18890.733893 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 18890.733893 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 18890.733893 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 18890.733893 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 18890.733893 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 18890.733893 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1159 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 82.785714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13251 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 13251 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 13251 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 13251 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 13251 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 13251 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95209 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 95209 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 95209 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 95209 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 95209 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 95209 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1668176000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 1668176000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1668176000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 1668176000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1668176000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 1668176000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006814 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006814 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006814 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006814 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006814 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17521.200727 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17521.200727 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17521.200727 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 17521.200727 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17521.200727 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17521.200727 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 132107 # number of replacements system.cpu.l2cache.tags.tagsinuse 30604.111406 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 285364 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 164184 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.738074 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26463.213686 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 2221.858475 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 1919.039245 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.807593 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067806 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.058564 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.933963 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32077 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3041 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28427 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 365 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978912 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 5069653 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 5069653 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 168840 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 168840 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12616 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12616 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 87827 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 87827 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34235 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 34235 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 87827 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 46851 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 134678 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 87827 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 46851 # number of overall hits system.cpu.l2cache.overall_hits::total 134678 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 130781 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 130781 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 7382 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 7382 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27861 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 27861 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 7382 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 158642 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 166024 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7382 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158642 # number of overall misses system.cpu.l2cache.overall_misses::total 166024 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13916068500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 13916068500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 602620000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 602620000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2758143500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 2758143500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 602620000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 16674212000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 17276832000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 602620000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 16674212000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 17276832000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 168840 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168840 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143397 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143397 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 95209 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 95209 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62096 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 62096 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 95209 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 205493 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 300702 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 95209 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 205493 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 300702 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912020 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.912020 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.077535 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.077535 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.448676 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.448676 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.077535 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.772007 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.552121 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.077535 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.772007 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.552121 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106407.417744 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106407.417744 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81633.703603 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81633.703603 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98996.572269 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98996.572269 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81633.703603 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105105.911423 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 104062.256059 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81633.703603 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105105.911423 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 104062.256059 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 114356 # number of writebacks system.cpu.l2cache.writebacks::total 114356 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2054 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 2054 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130781 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130781 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 7382 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 7382 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27861 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27861 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 7382 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158642 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 166024 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7382 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158642 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 166024 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12608258500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12608258500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 528810000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 528810000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2479533500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2479533500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 528810000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15087792000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 15616602000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 528810000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15087792000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 15616602000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912020 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912020 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077535 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448676 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448676 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772007 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.552121 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772007 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.552121 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96407.417744 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96407.417744 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71635.058250 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71635.058250 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88996.572269 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88996.572269 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71635.058250 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95105.911423 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94062.316292 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71635.058250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95105.911423 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94062.316292 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 157304 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 283196 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 143468 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 95209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 62096 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 283577 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612383 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 895960 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6093312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23957312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 30050624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 132107 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 727366 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.181624 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.385534 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 595259 81.84% 81.84% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 132107 18.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 727366 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 466469500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 142819485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 308243991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.trans_dist::ReadResp 35242 # Transaction distribution system.membus.trans_dist::Writeback 114356 # Transaction distribution system.membus.trans_dist::CleanEvict 15775 # Transaction distribution system.membus.trans_dist::ReadExReq 130781 # Transaction distribution system.membus.trans_dist::ReadExResp 130781 # Transaction distribution system.membus.trans_dist::ReadSharedReq 35242 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462177 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 462177 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17944256 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 17944256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 296154 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 296154 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 296154 # Request fanout histogram system.membus.reqLayer0.occupancy 778878000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) system.membus.respLayer1.occupancy 857917500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ----------