---------- Begin Simulation Statistics ---------- sim_seconds 0.022357 # Number of seconds simulated sim_ticks 22356634500 # Number of ticks simulated final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 213363 # Simulator instruction rate (inst/s) host_op_rate 213363 # Simulator op (including micro ops) rate (op/s) host_tick_rate 59931818 # Simulator tick rate (ticks/s) host_mem_usage 308400 # Number of bytes of host memory used host_seconds 373.03 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 471552 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10150720 # Number of bytes read from this memory system.physmem.bytes_read::total 10622272 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 471552 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 471552 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7318272 # Number of bytes written to this memory system.physmem.bytes_written::total 7318272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 7368 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158605 # Number of read requests responded to by this memory system.physmem.num_reads::total 165973 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114348 # Number of write requests responded to by this memory system.physmem.num_writes::total 114348 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 21092262 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 454036139 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 475128401 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 21092262 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 21092262 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 327342293 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 327342293 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 327342293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 21092262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 454036139 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 802470694 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165973 # Number of read requests accepted system.physmem.writeReqs 114348 # Number of write requests accepted system.physmem.readBursts 165973 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 114348 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 10621952 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue system.physmem.bytesWritten 7316672 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10622272 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7318272 # Total written bytes from the system interface side system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10420 # Per bank write bursts system.physmem.perBankRdBursts::1 10451 # Per bank write bursts system.physmem.perBankRdBursts::2 10285 # Per bank write bursts system.physmem.perBankRdBursts::3 10056 # Per bank write bursts system.physmem.perBankRdBursts::4 10402 # Per bank write bursts system.physmem.perBankRdBursts::5 10375 # Per bank write bursts system.physmem.perBankRdBursts::6 9822 # Per bank write bursts system.physmem.perBankRdBursts::7 10280 # Per bank write bursts system.physmem.perBankRdBursts::8 10559 # Per bank write bursts system.physmem.perBankRdBursts::9 10640 # Per bank write bursts system.physmem.perBankRdBursts::10 10517 # Per bank write bursts system.physmem.perBankRdBursts::11 10228 # Per bank write bursts system.physmem.perBankRdBursts::12 10263 # Per bank write bursts system.physmem.perBankRdBursts::13 10582 # Per bank write bursts system.physmem.perBankRdBursts::14 10475 # Per bank write bursts system.physmem.perBankRdBursts::15 10613 # Per bank write bursts system.physmem.perBankWrBursts::0 7161 # Per bank write bursts system.physmem.perBankWrBursts::1 7267 # Per bank write bursts system.physmem.perBankWrBursts::2 7294 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts system.physmem.perBankWrBursts::5 7171 # Per bank write bursts system.physmem.perBankWrBursts::6 6835 # Per bank write bursts system.physmem.perBankWrBursts::7 7095 # Per bank write bursts system.physmem.perBankWrBursts::8 7219 # Per bank write bursts system.physmem.perBankWrBursts::9 6995 # Per bank write bursts system.physmem.perBankWrBursts::10 7101 # Per bank write bursts system.physmem.perBankWrBursts::11 6988 # Per bank write bursts system.physmem.perBankWrBursts::12 6991 # Per bank write bursts system.physmem.perBankWrBursts::13 7292 # Per bank write bursts system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 22356603500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 165973 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 114348 # Write request sizes (log2) system.physmem.rdQLenPdf::0 52267 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 43039 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 38487 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 32162 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 835 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1884 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3491 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6088 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6570 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6911 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7144 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 7274 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 7548 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7865 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 7671 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 8321 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 10150 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 8291 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 9778 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 8126 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 370 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 52288 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 343.051408 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 202.164629 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 342.365120 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 18284 34.97% 34.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 10551 20.18% 55.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 5984 11.44% 66.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2964 5.67% 72.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2982 5.70% 77.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1592 3.04% 81.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1956 3.74% 84.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 963 1.84% 86.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7012 13.41% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 52288 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6989 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 23.745743 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 338.273336 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 6986 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6989 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6989 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.357562 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.328073 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 1.050353 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 6097 87.24% 87.24% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 30 0.43% 87.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 474 6.78% 94.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 201 2.88% 97.32% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 97 1.39% 98.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 49 0.70% 99.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 24 0.34% 99.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 8 0.11% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 5 0.07% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6989 # Writes before turning the bus around for reads system.physmem.totQLat 5746744750 # Total ticks spent queuing system.physmem.totMemAccLat 8858644750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 829840000 # Total ticks spent in databus transfers system.physmem.avgQLat 34625.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 53375.62 # Average memory access latency per DRAM burst system.physmem.avgRdBW 475.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 327.27 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 475.13 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 327.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 6.27 # Data bus utilization in percentage system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing system.physmem.readRowHits 145973 # Number of row buffer hits during reads system.physmem.writeRowHits 82020 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate 71.73 # Row buffer hit rate for writes system.physmem.avgGap 79753.58 # Average gap between requests system.physmem.pageHitRate 81.33 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 190882440 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 104152125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 640161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 6647542920 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 7581572250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 16993287015 # Total energy per rank (pJ) system.physmem_0.averagePower 760.170138 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12528806000 # Time in different power states system.physmem_0.memoryStateTime::REF 746460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 9079331500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 204271200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 111457500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 654100200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 371699280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 6857633520 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 7397282250 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 17056519710 # Total energy per rank (pJ) system.physmem_1.averagePower 762.998761 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 12224344750 # Time in different power states system.physmem_1.memoryStateTime::REF 746460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 9383970250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 16500558 # Number of BP lookups system.cpu.branchPred.condPredicted 10689411 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 329507 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 9043813 # Number of BTB lookups system.cpu.branchPred.BTBHits 7288978 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.596293 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1974529 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2931 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 22520885 # DTB read hits system.cpu.dtb.read_misses 225850 # DTB read misses system.cpu.dtb.read_acv 12 # DTB read access violations system.cpu.dtb.read_accesses 22746735 # DTB read accesses system.cpu.dtb.write_hits 15825785 # DTB write hits system.cpu.dtb.write_misses 44675 # DTB write misses system.cpu.dtb.write_acv 5 # DTB write access violations system.cpu.dtb.write_accesses 15870460 # DTB write accesses system.cpu.dtb.data_hits 38346670 # DTB hits system.cpu.dtb.data_misses 270525 # DTB misses system.cpu.dtb.data_acv 17 # DTB access violations system.cpu.dtb.data_accesses 38617195 # DTB accesses system.cpu.itb.fetch_hits 13761847 # ITB hits system.cpu.itb.fetch_misses 29330 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_accesses 13791177 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls system.cpu.numCycles 44713274 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 15584768 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 105191572 # Number of instructions fetch has processed system.cpu.fetch.Branches 16500558 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9263507 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 27593237 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 896542 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 162 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 4764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 325871 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 13761847 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 191924 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed system.cpu.fetch.rateDist::samples 43957183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.393046 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.127676 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 24416716 55.55% 55.55% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 1522401 3.46% 59.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1379227 3.14% 62.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1505485 3.42% 65.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 4199085 9.55% 75.13% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 1828470 4.16% 79.28% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 669319 1.52% 80.81% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1052182 2.39% 83.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 7384298 16.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 43957183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.369030 # Number of branch fetches per cycle system.cpu.fetch.rate 2.352580 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 14931500 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 9767964 # Number of cycles decode is blocked system.cpu.decode.RunCycles 18310970 # Number of cycles decode is running system.cpu.decode.UnblockCycles 595597 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 351152 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3708003 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 98860 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 103215952 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 311866 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 351152 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 15279451 # Number of cycles rename is idle system.cpu.rename.BlockCycles 4431592 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 96231 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 18542963 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5255794 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 102192828 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 5698 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 95463 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 341437 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 4753642 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 61435412 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 123253139 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 122935807 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 317331 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 8888531 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 5692 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 5745 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2361848 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 23156457 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 16385404 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1258348 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 502815 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 90834629 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 5552 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 88691609 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 70456 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 11248424 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 4497706 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 969 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 43957183 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.017682 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.245665 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 17476881 39.76% 39.76% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 5730177 13.04% 52.79% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 5107740 11.62% 64.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 4380373 9.97% 74.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 4328154 9.85% 84.23% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 2635103 5.99% 90.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1947598 4.43% 94.65% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1378142 3.14% 97.79% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 973015 2.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 43957183 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 243362 9.64% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1165216 46.16% 55.81% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 1115524 44.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 49430492 55.73% 55.73% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 43978 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 121147 0.14% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 120628 0.14% 56.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 39084 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 22917985 25.84% 81.94% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 16018139 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 88691609 # Type of FU issued system.cpu.iq.rate 1.983563 # Inst issue rate system.cpu.iq.fu_busy_cnt 2524102 # FU busy when requested system.cpu.iq.fu_busy_rate 0.028459 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 223325364 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 101690449 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 86898361 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 609595 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 418176 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 299341 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 90910760 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 304951 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1670602 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 2879819 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5660 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20258 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 1772027 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3047 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 205936 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 351152 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1286887 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 2706445 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 100341607 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 125884 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 23156457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16385404 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 5552 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3769 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2705021 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20258 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 121859 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 151192 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 273051 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 87981340 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 22747403 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 710269 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9501426 # number of nop insts executed system.cpu.iew.exec_refs 38618193 # number of memory reference insts executed system.cpu.iew.exec_branches 15127263 # Number of branches executed system.cpu.iew.exec_stores 15870790 # Number of stores executed system.cpu.iew.exec_rate 1.967678 # Inst execution rate system.cpu.iew.wb_sent 87600358 # cumulative count of insts sent to commit system.cpu.iew.wb_count 87197702 # cumulative count of insts written-back system.cpu.iew.wb_producers 33849535 # num instructions producing a value system.cpu.iew.wb_consumers 44277575 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.950152 # insts written-back per cycle system.cpu.iew.wb_fanout 0.764485 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 8791000 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 232388 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 42666920 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.070472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.884283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 21190783 49.67% 49.67% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 6285871 14.73% 64.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 2905995 6.81% 71.21% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 1744112 4.09% 75.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1680276 3.94% 79.23% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1128586 2.65% 81.88% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1203447 2.82% 84.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 797041 1.87% 86.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 5730809 13.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 42666920 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed system.cpu.commit.loads 20276638 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 13754477 # Number of branches committed system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction system.cpu.commit.bw_lim_events 5730809 # number cycles where commit BW limit reached system.cpu.rob.rob_reads 132750441 # The number of ROB reads system.cpu.rob.rob_writes 195556891 # The number of ROB writes system.cpu.timesIdled 46372 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 756091 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.561783 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.561783 # CPI: Total CPI of All Threads system.cpu.ipc 1.780048 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.780048 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 116466074 # number of integer regfile reads system.cpu.int_regfile_writes 57713698 # number of integer regfile writes system.cpu.fp_regfile_reads 255059 # number of floating regfile reads system.cpu.fp_regfile_writes 240376 # number of floating regfile writes system.cpu.misc_regfile_reads 38265 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 201297 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.745765 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 33997888 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 205393 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 165.526031 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 229746500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4070.745765 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993834 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993834 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2788 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1232 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 70843209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 70843209 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 20436554 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20436554 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13561278 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 13561278 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits system.cpu.dcache.demand_hits::cpu.data 33997832 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 33997832 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 33997832 # number of overall hits system.cpu.dcache.overall_hits::total 33997832 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 268921 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 268921 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1052099 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1052099 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 1321020 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1321020 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1321020 # number of overall misses system.cpu.dcache.overall_misses::total 1321020 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 17355062000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 17355062000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 89131929604 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 89131929604 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 106486991604 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 106486991604 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 106486991604 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 106486991604 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20705475 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20705475 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 35318852 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 35318852 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 35318852 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 35318852 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012988 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012988 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071996 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.071996 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.037403 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.037403 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037403 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037403 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64535.912034 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 64535.912034 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84718.196295 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 84718.196295 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 80609.674043 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 80609.674043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 6869550 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 88969 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.212849 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168788 # number of writebacks system.cpu.dcache.writebacks::total 168788 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206925 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 206925 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908702 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 908702 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1115627 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1115627 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1115627 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1115627 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61996 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61996 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 205393 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 205393 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 205393 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 205393 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3212836500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 3212836500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14233206202 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 14233206202 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17446042702 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 17446042702 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17446042702 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 17446042702 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002994 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005815 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005815 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51823.286986 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51823.286986 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99257.349889 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99257.349889 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 91498 # number of replacements system.cpu.icache.tags.tagsinuse 1915.935564 # Cycle average of tags in use system.cpu.icache.tags.total_refs 13655300 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 93546 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 145.974173 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 18815415500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1915.935564 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.935515 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.935515 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1476 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 380 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 27617236 # Number of tag accesses system.cpu.icache.tags.data_accesses 27617236 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 13655300 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13655300 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13655300 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 13655300 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 13655300 # number of overall hits system.cpu.icache.overall_hits::total 13655300 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 106545 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 106545 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 106545 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 106545 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 106545 # number of overall misses system.cpu.icache.overall_misses::total 106545 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 2015171999 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 2015171999 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 2015171999 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 2015171999 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 2015171999 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 2015171999 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 13761845 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 13761845 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 13761845 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 13761845 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 13761845 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13761845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007742 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.007742 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.007742 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.007742 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.007742 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.007742 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18913.811056 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 18913.811056 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 18913.811056 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 18913.811056 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 18913.811056 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 18913.811056 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1468 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 77.263158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12998 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 12998 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 12998 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 12998 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 12998 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 12998 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93547 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 93547 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 93547 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 93547 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 93547 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 93547 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1645041500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 1645041500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1645041500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 1645041500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1645041500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 1645041500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006798 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006798 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006798 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17585.187125 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17585.187125 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17585.187125 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 17585.187125 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17585.187125 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17585.187125 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 132064 # number of replacements system.cpu.l2cache.tags.tagsinuse 30597.382084 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 281892 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 164129 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.717503 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26451.406117 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 2221.195572 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 1924.780395 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.807233 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067786 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.058740 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.933758 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32065 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3040 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28434 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978546 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 5041408 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 5041408 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 168788 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 168788 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12616 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12616 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86178 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 86178 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34172 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 34172 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 86178 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 46788 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 132966 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 86178 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 46788 # number of overall hits system.cpu.l2cache.overall_hits::total 132966 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 130783 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 130783 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 7369 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 7369 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27822 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 27822 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 7369 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 158605 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 165974 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7369 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158605 # number of overall misses system.cpu.l2cache.overall_misses::total 165974 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13881530500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 13881530500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 599246500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 599246500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2756158500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 2756158500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 599246500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 16637689000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 17236935500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 599246500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 16637689000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 17236935500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 168788 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168788 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143399 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143399 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 93547 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 93547 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61994 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 61994 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 93547 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 205393 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 298940 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 93547 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 205393 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 298940 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912022 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.912022 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.078773 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.078773 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.448785 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.448785 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.078773 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.772203 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.555208 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.078773 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.772203 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.555208 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106141.704197 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106141.704197 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81319.921292 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81319.921292 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99063.996118 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99063.996118 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81319.921292 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104900.154472 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 103853.227011 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81319.921292 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104900.154472 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 103853.227011 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 114348 # number of writebacks system.cpu.l2cache.writebacks::total 114348 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2056 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 2056 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130783 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130783 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 7369 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 7369 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27822 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27822 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 7369 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158605 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 165974 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7369 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158605 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165974 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12573700500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12573700500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 525566500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 525566500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2477938500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2477938500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 525566500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15051639000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 15577205500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 525566500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15051639000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 15577205500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912022 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912022 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078773 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448785 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448785 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.555208 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.555208 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96141.704197 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96141.704197 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71321.278328 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71321.278328 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89063.996118 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89063.996118 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 591735 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 292795 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 93547 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 61994 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278591 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612083 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 890674 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5986944 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23947584 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 132064 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.005561 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.074364 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 719774 99.44% 99.44% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 4025 0.56% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 140327982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 308097983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.trans_dist::ReadResp 35190 # Transaction distribution system.membus.trans_dist::Writeback 114348 # Transaction distribution system.membus.trans_dist::CleanEvict 15746 # Transaction distribution system.membus.trans_dist::ReadExReq 130783 # Transaction distribution system.membus.trans_dist::ReadExResp 130783 # Transaction distribution system.membus.trans_dist::ReadSharedReq 35190 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462040 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 462040 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 296067 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 296067 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 296067 # Request fanout histogram system.membus.reqLayer0.occupancy 778875000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) system.membus.respLayer1.occupancy 857731250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ----------