---------- Begin Simulation Statistics ---------- sim_seconds 0.056986 # Number of seconds simulated sim_ticks 56986224500 # Number of ticks simulated final_tick 56986224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 135704 # Simulator instruction rate (inst/s) host_op_rate 173546 # Simulator op (including micro ops) rate (op/s) host_tick_rate 109049636 # Simulator tick rate (ticks/s) host_mem_usage 317176 # Number of bytes of host memory used host_seconds 522.57 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 318720 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7923904 # Number of bytes read from this memory system.physmem.bytes_read::total 8242624 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 318720 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 318720 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5514048 # Number of bytes written to this memory system.physmem.bytes_written::total 5514048 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4980 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123811 # Number of read requests responded to by this memory system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 5592931 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 139049464 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 144642395 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 5592931 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 5592931 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 96761069 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 96761069 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 96761069 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 5592931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 139049464 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 241403464 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128791 # Number of read requests accepted system.physmem.writeReqs 86157 # Number of write requests accepted system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue system.physmem.bytesWritten 5512000 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8144 # Per bank write bursts system.physmem.perBankRdBursts::1 8370 # Per bank write bursts system.physmem.perBankRdBursts::2 8248 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts system.physmem.perBankRdBursts::4 8315 # Per bank write bursts system.physmem.perBankRdBursts::5 8436 # Per bank write bursts system.physmem.perBankRdBursts::6 8084 # Per bank write bursts system.physmem.perBankRdBursts::7 7955 # Per bank write bursts system.physmem.perBankRdBursts::8 8060 # Per bank write bursts system.physmem.perBankRdBursts::9 7629 # Per bank write bursts system.physmem.perBankRdBursts::10 7815 # Per bank write bursts system.physmem.perBankRdBursts::11 7829 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7878 # Per bank write bursts system.physmem.perBankRdBursts::14 7975 # Per bank write bursts system.physmem.perBankRdBursts::15 7995 # Per bank write bursts system.physmem.perBankWrBursts::0 5393 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts system.physmem.perBankWrBursts::2 5463 # Per bank write bursts system.physmem.perBankWrBursts::3 5328 # Per bank write bursts system.physmem.perBankWrBursts::4 5352 # Per bank write bursts system.physmem.perBankWrBursts::5 5545 # Per bank write bursts system.physmem.perBankWrBursts::6 5246 # Per bank write bursts system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts system.physmem.perBankWrBursts::10 5289 # Per bank write bursts system.physmem.perBankWrBursts::11 5270 # Per bank write bursts system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts system.physmem.perBankWrBursts::14 5703 # Per bank write bursts system.physmem.perBankWrBursts::15 5431 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 56986193500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 128791 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86157 # Write request sizes (log2) system.physmem.rdQLenPdf::0 116559 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 12202 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 656 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4080 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5286 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5311 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5306 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 5318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5350 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5376 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5428 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5451 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5897 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5469 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 38656 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 355.735099 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 216.399320 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 335.915140 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12161 31.46% 31.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 8166 21.12% 52.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4096 10.60% 63.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2818 7.29% 70.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2687 6.95% 77.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1672 4.33% 81.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1300 3.36% 85.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1153 2.98% 88.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4603 11.91% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 38656 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5291 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 24.313362 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 352.121472 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5289 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5291 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5291 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.277641 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.260577 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 0.779844 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 4640 87.70% 87.70% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 6 0.11% 87.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 513 9.70% 97.51% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 107 2.02% 99.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 4 0.08% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5291 # Writes before turning the bus around for reads system.physmem.totQLat 1688662500 # Total ticks spent queuing system.physmem.totMemAccLat 4103362500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers system.physmem.avgQLat 13112.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 31862.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 144.63 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 144.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.89 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing system.physmem.readRowHits 112105 # Number of row buffer hits during reads system.physmem.writeRowHits 64137 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.44 # Row buffer hit rate for writes system.physmem.avgGap 265116.18 # Average gap between requests system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 512194800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 11693696490 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 23930394000 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 40371922185 # Total energy per rank (pJ) system.physmem_0.averagePower 708.527477 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 39682710000 # Time in different power states system.physmem_0.memoryStateTime::REF 1902680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15394661250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 140086800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 76436250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 491673000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 11090732535 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 24459309750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 40259019375 # Total energy per rank (pJ) system.physmem_1.averagePower 706.546032 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 40563908250 # Time in different power states system.physmem_1.memoryStateTime::REF 1902680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14513554250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 14800511 # Number of BP lookups system.cpu.branchPred.condPredicted 9905691 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 381680 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 9439152 # Number of BTB lookups system.cpu.branchPred.BTBHits 6732150 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 71.321555 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1714112 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 113972449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed system.cpu.discardedOps 1144886 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.607167 # CPI: cycles per instruction system.cpu.ipc 0.622213 # IPC: instructions per cycle system.cpu.tickCycles 95596263 # Number of cycles that the object actually ticked system.cpu.idleCycles 18376186 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 156435 # number of replacements system.cpu.dcache.tags.tagsinuse 4067.140403 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42624247 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 265.520348 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822680500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4067.140403 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992954 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2936 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86016733 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86016733 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 22866807 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22866807 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642189 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19642189 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83413 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 83413 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 42508996 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 42508996 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 42592409 # number of overall hits system.cpu.dcache.overall_hits::total 42592409 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 51550 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 51550 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 207712 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 207712 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 44592 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 44592 # number of SoftPFReq misses system.cpu.dcache.demand_misses::cpu.data 259262 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 259262 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 303854 # number of overall misses system.cpu.dcache.overall_misses::total 303854 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489104500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 1489104500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 16802314000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 16802314000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 18291418500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 18291418500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 18291418500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 18291418500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348361 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.348361 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28886.605238 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 28886.605238 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80892.360576 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80892.360576 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 70551.868380 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 70551.868380 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 60198.050709 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 60198.050709 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks system.cpu.dcache.writebacks::total 128400 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22032 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 22032 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100684 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 100684 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 122716 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 122716 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 122716 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 122716 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 136546 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 574723500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 574723500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8485443000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8485443000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719503000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719503000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9060166500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9060166500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779669500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10779669500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19470.272376 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19470.272376 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79282.458796 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79282.458796 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71690.765061 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71690.765061 # average SoftPFReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66352.485609 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66352.485609 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67150.080047 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67150.080047 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42865 # number of replacements system.cpu.icache.tags.tagsinuse 1852.538301 # Cycle average of tags in use system.cpu.icache.tags.total_refs 24941041 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 44907 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 555.393168 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1852.538301 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.904560 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.904560 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 50016805 # Number of tag accesses system.cpu.icache.tags.data_accesses 50016805 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 24941041 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 24941041 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 24941041 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 24941041 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 24941041 # number of overall hits system.cpu.icache.overall_hits::total 24941041 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 44908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 44908 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 44908 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 44908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 44908 # number of overall misses system.cpu.icache.overall_misses::total 44908 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 926324500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 926324500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 926324500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 926324500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 926324500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 926324500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 24985949 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 24985949 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 24985949 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 24985949 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 24985949 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 24985949 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20627.159971 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 20627.159971 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 20627.159971 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 20627.159971 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44908 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 44908 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 44908 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 44908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 44908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 44908 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 881417500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 881417500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 881417500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 881417500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 881417500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 881417500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19627.182239 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19627.182239 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95654 # number of replacements system.cpu.l2cache.tags.tagsinuse 29860.809495 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 161643 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.275069 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26579.265460 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.835593 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.708442 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.811135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049464 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.050681 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.911280 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1806 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12714 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15870 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3409200 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3409200 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 128400 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39917 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 39917 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31903 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 31903 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 39917 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 76572 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 39917 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits system.cpu.l2cache.overall_hits::total 76572 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4991 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 4991 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21600 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 21600 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 4991 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 123876 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 128867 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 4991 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123876 # number of overall misses system.cpu.l2cache.overall_misses::total 128867 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8274960000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8274960000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394876000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 394876000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1878573500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 1878573500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 394876000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10153533500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 10548409500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 394876000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10153533500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 10548409500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44908 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 44908 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 44908 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 160531 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 205439 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 44908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 160531 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 205439 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111138 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111138 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111138 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.627276 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111138 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.627276 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80908.130940 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80908.130940 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79117.611701 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79117.611701 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86970.995370 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86970.995370 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 81855.009428 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 81855.009428 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 86157 # number of writebacks system.cpu.l2cache.writebacks::total 86157 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 10 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 10 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 65 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1374 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 1374 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4981 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4981 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21535 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21535 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123811 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 128792 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7252200000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7252200000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 344388000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 344388000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658643500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658643500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 344388000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8910843500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 9255231500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 344388000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8910843500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 9255231500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110916 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.626911 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.626911 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70908.130940 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70908.130940 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69140.333266 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69140.333266 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77020.826561 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77020.826561 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 98410 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 72583 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 44908 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129101 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 602363 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 21365632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 95654 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 500393 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.191158 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.393213 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 404739 80.88% 80.88% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 95654 19.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 500393 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 330769500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 67366488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 240828935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.trans_dist::ReadResp 26515 # Transaction distribution system.membus.trans_dist::Writeback 86157 # Transaction distribution system.membus.trans_dist::CleanEvict 7510 # Transaction distribution system.membus.trans_dist::ReadExReq 102276 # Transaction distribution system.membus.trans_dist::ReadExResp 102276 # Transaction distribution system.membus.trans_dist::ReadSharedReq 26515 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351249 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 351249 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13756672 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 13756672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 222458 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 222458 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 222458 # Request fanout histogram system.membus.reqLayer0.occupancy 591536000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) system.membus.respLayer1.occupancy 679701000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ----------