---------- Begin Simulation Statistics ---------- sim_seconds 0.056991 # Number of seconds simulated sim_ticks 56991022500 # Number of ticks simulated final_tick 56991022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 186679 # Simulator instruction rate (inst/s) host_op_rate 238735 # Simulator op (including micro ops) rate (op/s) host_tick_rate 150024942 # Simulator tick rate (ticks/s) host_mem_usage 325676 # Number of bytes of host memory used host_seconds 379.88 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 318720 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7923904 # Number of bytes read from this memory system.physmem.bytes_read::total 8242624 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 318720 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 318720 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5514048 # Number of bytes written to this memory system.physmem.bytes_written::total 5514048 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4980 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123811 # Number of read requests responded to by this memory system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 5592460 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 139037758 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 144630218 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 5592460 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 5592460 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 96752923 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 96752923 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 96752923 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 5592460 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 139037758 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 241383141 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128791 # Number of read requests accepted system.physmem.writeReqs 86157 # Number of write requests accepted system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue system.physmem.bytesWritten 5512640 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8144 # Per bank write bursts system.physmem.perBankRdBursts::1 8370 # Per bank write bursts system.physmem.perBankRdBursts::2 8248 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts system.physmem.perBankRdBursts::4 8315 # Per bank write bursts system.physmem.perBankRdBursts::5 8436 # Per bank write bursts system.physmem.perBankRdBursts::6 8084 # Per bank write bursts system.physmem.perBankRdBursts::7 7955 # Per bank write bursts system.physmem.perBankRdBursts::8 8060 # Per bank write bursts system.physmem.perBankRdBursts::9 7629 # Per bank write bursts system.physmem.perBankRdBursts::10 7815 # Per bank write bursts system.physmem.perBankRdBursts::11 7829 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7878 # Per bank write bursts system.physmem.perBankRdBursts::14 7975 # Per bank write bursts system.physmem.perBankRdBursts::15 7995 # Per bank write bursts system.physmem.perBankWrBursts::0 5393 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts system.physmem.perBankWrBursts::2 5464 # Per bank write bursts system.physmem.perBankWrBursts::3 5326 # Per bank write bursts system.physmem.perBankWrBursts::4 5352 # Per bank write bursts system.physmem.perBankWrBursts::5 5547 # Per bank write bursts system.physmem.perBankWrBursts::6 5252 # Per bank write bursts system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts system.physmem.perBankWrBursts::10 5292 # Per bank write bursts system.physmem.perBankWrBursts::11 5270 # Per bank write bursts system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts system.physmem.perBankWrBursts::14 5703 # Per bank write bursts system.physmem.perBankWrBursts::15 5431 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 56990990500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 128791 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86157 # Write request sizes (log2) system.physmem.rdQLenPdf::0 116650 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 12110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4071 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5170 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5285 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5306 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5310 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5310 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5367 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5452 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5431 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5478 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5464 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 38662 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 355.683203 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 216.343519 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 336.125731 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12148 31.42% 31.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 8177 21.15% 52.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4090 10.58% 63.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2852 7.38% 70.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2693 6.97% 77.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1623 4.20% 81.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1296 3.35% 85.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1161 3.00% 88.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4622 11.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 38662 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 24.322124 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 352.056892 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.273380 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.256688 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 0.768255 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 4654 87.93% 87.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 4 0.08% 88.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 500 9.45% 97.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 109 2.06% 99.51% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 18 0.34% 99.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 5 0.09% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads system.physmem.totQLat 1683428000 # Total ticks spent queuing system.physmem.totMemAccLat 4098128000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers system.physmem.avgQLat 13071.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 31821.72 # Average memory access latency per DRAM burst system.physmem.avgRdBW 144.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 144.63 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 96.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.89 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing system.physmem.readRowHits 112096 # Number of row buffer hits during reads system.physmem.writeRowHits 64153 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.04 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.46 # Row buffer hit rate for writes system.physmem.avgGap 265138.50 # Average gap between requests system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 151963560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 82916625 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 512397600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 278957520 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 11726025750 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 23906742000 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 40381153695 # Total energy per rank (pJ) system.physmem_0.averagePower 708.591931 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 39643767750 # Time in different power states system.physmem_0.memoryStateTime::REF 1902940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15441187500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 140313600 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 76560000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 491751000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 11059172775 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 24491665500 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 40260752475 # Total energy per rank (pJ) system.physmem_1.averagePower 706.479908 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 40617302250 # Time in different power states system.physmem_1.memoryStateTime::REF 1902940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14467595250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 14800541 # Number of BP lookups system.cpu.branchPred.condPredicted 9905717 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 381681 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 9438549 # Number of BTB lookups system.cpu.branchPred.BTBHits 6732145 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 71.326059 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1714124 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 113982045 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed system.cpu.discardedOps 1144890 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.607302 # CPI: cycles per instruction system.cpu.ipc 0.622161 # IPC: instructions per cycle system.cpu.tickCycles 95587829 # Number of cycles that the object actually ticked system.cpu.idleCycles 18394216 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 156435 # number of replacements system.cpu.dcache.tags.tagsinuse 4067.142814 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42624094 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 265.519395 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4067.142814 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1110 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86016729 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86016729 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 22866654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22866654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642187 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19642187 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83415 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 83415 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 42508841 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 42508841 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 42592256 # number of overall hits system.cpu.dcache.overall_hits::total 42592256 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 51701 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 51701 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 207714 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 207714 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses system.cpu.dcache.demand_misses::cpu.data 259415 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 259415 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 304005 # number of overall misses system.cpu.dcache.overall_misses::total 304005 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 1492164500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 1492164500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 16804934500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 16804934500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 18297099000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 18297099000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 18297099000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 18297099000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22918355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22918355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 42768256 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42768256 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 42896261 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42896261 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002256 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348346 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.348346 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 70532.155041 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 60186.835743 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks system.cpu.dcache.writebacks::total 128400 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22183 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 22183 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100686 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 100686 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 122869 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 122869 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 122869 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 122869 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 136546 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578376000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 578376000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8484284000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8484284000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1716349500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1716349500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9062660000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9062660000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779009500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10779009500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054 # average SoftPFReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42866 # number of replacements system.cpu.icache.tags.tagsinuse 1852.547846 # Cycle average of tags in use system.cpu.icache.tags.total_refs 24941084 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 44908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 555.381758 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1852.547846 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.904564 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.904564 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 50016894 # Number of tag accesses system.cpu.icache.tags.data_accesses 50016894 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 24941084 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 24941084 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 24941084 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 24941084 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 24941084 # number of overall hits system.cpu.icache.overall_hits::total 24941084 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 44909 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 44909 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 44909 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 44909 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 44909 # number of overall misses system.cpu.icache.overall_misses::total 44909 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 929470000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 929470000 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 929470000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 929470000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 929470000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 929470000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 24985993 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 24985993 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 24985993 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 24985993 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 24985993 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 24985993 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 20696.742301 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 20696.742301 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44909 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 44909 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 44909 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 44909 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 44909 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 44909 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 884562000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 884562000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 884562000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 884562000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 884562000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 884562000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19696.764568 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19696.764568 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95654 # number of replacements system.cpu.l2cache.tags.tagsinuse 29860.905704 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 161645 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.275084 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26579.253739 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.855600 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.796365 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.811134 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049465 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.050683 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.911283 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1809 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12704 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15880 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3409216 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3409216 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 128400 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39918 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 39918 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31903 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 31903 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 39918 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 76573 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 39918 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits system.cpu.l2cache.overall_hits::total 76573 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4991 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 4991 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21600 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 21600 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 4991 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 123876 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 128867 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 4991 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123876 # number of overall misses system.cpu.l2cache.overall_misses::total 128867 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8273802000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8273802000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394300500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 394300500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1875098000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 1875098000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 394300500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10148900000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 10543200500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 394300500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10148900000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 10543200500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128400 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44909 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 44909 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 44909 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 160531 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 205440 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 44909 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 160531 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 205440 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111136 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111136 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111136 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.627273 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111136 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.627273 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80896.808635 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80896.808635 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79002.304147 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79002.304147 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86810.092593 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86810.092593 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 81814.587908 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 81814.587908 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 86157 # number of writebacks system.cpu.l2cache.writebacks::total 86157 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 10 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 10 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 65 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1374 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 1374 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4981 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4981 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21535 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21535 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123811 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 128792 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7251042000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7251042000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 343845500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 343845500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655136500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655136500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 343845500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8906178500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 9250024000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 343845500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8906178500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 9250024000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110913 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.626908 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.626908 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 404741 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 199337 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 98411 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 72584 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 44909 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129104 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 602366 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 21365696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 95654 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 500395 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.038076 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.191682 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 481371 96.20% 96.20% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 18995 3.80% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 500395 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 330770500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 67369485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 240829933 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.trans_dist::ReadResp 26515 # Transaction distribution system.membus.trans_dist::Writeback 86157 # Transaction distribution system.membus.trans_dist::CleanEvict 7510 # Transaction distribution system.membus.trans_dist::ReadExReq 102276 # Transaction distribution system.membus.trans_dist::ReadExResp 102276 # Transaction distribution system.membus.trans_dist::ReadSharedReq 26515 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351249 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 351249 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13756672 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 13756672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 222458 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 222458 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 222458 # Request fanout histogram system.membus.reqLayer0.occupancy 591531500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) system.membus.respLayer1.occupancy 679686000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ----------