---------- Begin Simulation Statistics ---------- sim_seconds 0.026781 # Number of seconds simulated sim_ticks 26780535000 # Number of ticks simulated final_tick 26780535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 149394 # Simulator instruction rate (inst/s) host_op_rate 211994 # Simulator op (including micro ops) rate (op/s) host_tick_rate 56410244 # Simulator tick rate (ticks/s) host_mem_usage 261852 # Number of bytes of host memory used host_seconds 474.75 # Real time elapsed on the host sim_insts 70924159 # Number of instructions simulated sim_ops 100643406 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 300160 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7944448 # Number of bytes read from this memory system.physmem.bytes_read::total 8244608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 300160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 300160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372672 # Number of bytes written to this memory system.physmem.bytes_written::total 5372672 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4690 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 124132 # Number of read requests responded to by this memory system.physmem.num_reads::total 128822 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83948 # Number of write requests responded to by this memory system.physmem.num_writes::total 83948 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 11208141 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 296650086 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 307858226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 11208141 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 11208141 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 200618546 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 200618546 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 200618546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 11208141 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 296650086 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 508476772 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128823 # Total number of read requests seen system.physmem.writeReqs 83948 # Total number of write requests seen system.physmem.cpureqs 213079 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 8244608 # Total number of bytes read from memory system.physmem.bytesWritten 5372672 # Total number of bytes written to memory system.physmem.bytesConsumedRd 8244608 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 5372672 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 308 # Reqs where no action is needed system.physmem.perBankRdReqs::0 8176 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 8046 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 7891 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 7930 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 8032 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 7950 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 7992 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 8193 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 8188 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 8163 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 8063 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 7981 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 5174 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 5233 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 5374 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 5287 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 5126 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 5148 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.totGap 26780515500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 128823 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes system.physmem.writePktSize::2 0 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes system.physmem.writePktSize::6 83948 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes system.physmem.neitherpktsize::1 0 # categorize neither packet sizes system.physmem.neitherpktsize::2 0 # categorize neither packet sizes system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes system.physmem.neitherpktsize::6 308 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 71083 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 55295 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 2364 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 3587 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 4847041699 # Total cycles spent in queuing delays system.physmem.totMemAccLat 6735959699 # Sum of mem lat for all requests system.physmem.totBusLat 515280000 # Total cycles spent in databus access system.physmem.totBankLat 1373638000 # Total cycles spent in bank access system.physmem.avgQLat 37626.47 # Average queueing delay per request system.physmem.avgBankLat 10663.24 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgMemAccLat 52289.70 # Average memory access latency system.physmem.avgRdBW 307.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 200.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 307.86 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 200.62 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.18 # Data bus utilization in percentage system.physmem.avgRdQLen 0.25 # Average read queue length over time system.physmem.avgWrQLen 9.64 # Average write queue length over time system.physmem.readRowHits 118946 # Number of row buffer hits during reads system.physmem.writeRowHits 27105 # Number of row buffer hits during writes system.physmem.readRowHitRate 92.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate 32.29 # Row buffer hit rate for writes system.physmem.avgGap 125865.44 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 53561071 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 16989438 # Number of BP lookups system.cpu.BPredUnit.condPredicted 12991194 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 680202 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 11755292 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 8009849 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 1851785 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 114363 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 12914479 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 87008149 # Number of instructions fetch has processed system.cpu.fetch.Branches 16989438 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9861634 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 21655288 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2666634 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 10515039 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 571 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 11971869 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 198806 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 47045662 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.589318 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.332778 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 25412140 54.02% 54.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2169507 4.61% 58.63% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 2024864 4.30% 62.93% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2094897 4.45% 67.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 1497374 3.18% 70.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 1417625 3.01% 73.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 986770 2.10% 75.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1225872 2.61% 78.28% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 10216613 21.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 47045662 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.317198 # Number of branch fetches per cycle system.cpu.fetch.rate 1.624466 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 15025286 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 8880734 # Number of cycles decode is blocked system.cpu.decode.RunCycles 19918391 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1367786 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1853465 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3434521 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 108932 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 119105730 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 372945 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1853465 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 16780714 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2530019 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 932679 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 19483180 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5465605 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 116933277 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 14375 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 4623545 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 215 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 117254635 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 538431443 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 538426294 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 5149 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 18095515 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25625 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25611 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 12984960 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 29963650 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 22702028 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3806099 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4346835 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 113028204 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 41641 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 108286515 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 316116 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 12256138 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 28707838 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 4549 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 47045662 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.301732 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.993875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 11469393 24.38% 24.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 8159881 17.34% 41.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 7486298 15.91% 57.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 7193710 15.29% 72.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 5478307 11.64% 84.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 3936871 8.37% 92.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1856294 3.95% 96.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 881703 1.87% 98.76% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 583205 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 47045662 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 112009 4.47% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1372514 54.80% 59.28% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 1019865 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 57275495 52.89% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 91732 0.08% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 181 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.98% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 29138143 26.91% 79.89% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 21780957 20.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 108286515 # Type of FU issued system.cpu.iq.rate 2.021739 # Inst issue rate system.cpu.iq.fu_busy_cnt 2504390 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023127 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 266438684 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 125354112 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 106381358 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 110790645 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2168801 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 2653236 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 7465 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 30261 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 2142984 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 473 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1853465 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1042007 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 44975 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 113079657 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 348290 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29963650 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 22702028 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 25073 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6129 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 5511 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30261 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 453510 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 204690 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 658200 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 107104018 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 28789803 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1182497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9812 # number of nop insts executed system.cpu.iew.exec_refs 50259028 # number of memory reference insts executed system.cpu.iew.exec_branches 14733119 # Number of branches executed system.cpu.iew.exec_stores 21469225 # Number of stores executed system.cpu.iew.exec_rate 1.999662 # Inst execution rate system.cpu.iew.wb_sent 106622925 # cumulative count of insts sent to commit system.cpu.iew.wb_count 106381514 # cumulative count of insts written-back system.cpu.iew.wb_producers 53628948 # num instructions producing a value system.cpu.iew.wb_consumers 104196549 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.986172 # insts written-back per cycle system.cpu.iew.wb_fanout 0.514690 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 12431579 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 573556 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 45192198 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.227131 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.747743 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 15976760 35.35% 35.35% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 11724717 25.94% 61.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 3516948 7.78% 69.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2892652 6.40% 75.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1888504 4.18% 79.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1974510 4.37% 84.03% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 692586 1.53% 85.56% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 573861 1.27% 86.83% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 5951660 13.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 45192198 # Number of insts commited each cycle system.cpu.commit.committedInsts 70929711 # Number of instructions committed system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 47869458 # Number of memory references committed system.cpu.commit.loads 27310414 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed system.cpu.commit.branches 13744811 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.bw_lim_events 5951660 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 152295776 # The number of ROB reads system.cpu.rob.rob_writes 228025366 # The number of ROB writes system.cpu.timesIdled 74466 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 6515409 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70924159 # Number of Instructions Simulated system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated system.cpu.cpi 0.755188 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.755188 # CPI: Total CPI of All Threads system.cpu.ipc 1.324174 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.324174 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 515451838 # number of integer regfile reads system.cpu.int_regfile_writes 104231541 # number of integer regfile writes system.cpu.fp_regfile_reads 698 # number of floating regfile reads system.cpu.fp_regfile_writes 610 # number of floating regfile writes system.cpu.misc_regfile_reads 145512549 # number of misc regfile reads system.cpu.misc_regfile_writes 38452 # number of misc regfile writes system.cpu.icache.replacements 31300 # number of replacements system.cpu.icache.tagsinuse 1822.220766 # Cycle average of tags in use system.cpu.icache.total_refs 11934433 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 33335 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 358.015089 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 1822.220766 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.889756 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.889756 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 11934443 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 11934443 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 11934443 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 11934443 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 11934443 # number of overall hits system.cpu.icache.overall_hits::total 11934443 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 37425 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 37425 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 37425 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 37425 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 37425 # number of overall misses system.cpu.icache.overall_misses::total 37425 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 718344999 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 718344999 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 718344999 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 718344999 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 718344999 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 718344999 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 11971868 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 11971868 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 11971868 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 11971868 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 11971868 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 11971868 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003126 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003126 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003126 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.003126 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.003126 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.003126 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19194.255150 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 19194.255150 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 19194.255150 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 19194.255150 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 55.157895 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33651 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 33651 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 33651 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 33651 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 33651 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 33651 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 589350499 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 589350499 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 589350499 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 589350499 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 589350499 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 589350499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002811 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.002811 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002811 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17513.610264 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17513.610264 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158507 # number of replacements system.cpu.dcache.tagsinuse 4072.917720 # Cycle average of tags in use system.cpu.dcache.total_refs 44563863 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 162603 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 274.065442 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 285154000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4072.917720 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994365 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994365 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 26258448 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 26258448 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18265067 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18265067 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 44523515 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 44523515 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 44523515 # number of overall hits system.cpu.dcache.overall_hits::total 44523515 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 125393 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 125393 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1584834 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1584834 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 1710227 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1710227 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1710227 # number of overall misses system.cpu.dcache.overall_misses::total 1710227 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 4597179000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4597179000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 120104513482 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 120104513482 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 949000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 949000 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 124701692482 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 124701692482 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 124701692482 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 124701692482 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 26383841 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 26383841 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20499 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 20499 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 46233742 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 46233742 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 46233742 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 46233742 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.036991 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.036991 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036991 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036991 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36662.166150 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 36662.166150 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75783.655248 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 75783.655248 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21568.181818 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21568.181818 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 72915.286966 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 72915.286966 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2506 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 608 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.418803 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 129149 # number of writebacks system.cpu.dcache.writebacks::total 129149 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69778 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 69778 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477521 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1477521 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1547299 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1547299 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1547299 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1547299 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55615 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55615 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107313 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107313 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 162928 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 162928 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 162928 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 162928 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2039094000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2039094000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257233993 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257233993 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10296327993 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 10296327993 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10296327993 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10296327993 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003524 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003524 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36664.461027 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36664.461027 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76945.328087 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76945.328087 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 95689 # number of replacements system.cpu.l2cache.tagsinuse 30139.737825 # Cycle average of tags in use system.cpu.l2cache.total_refs 90978 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 126809 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.717441 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 26886.974949 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1383.020531 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 1869.742346 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.820525 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.042206 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.057060 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.919792 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 28461 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 62098 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 129149 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 129149 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4769 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4769 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 28461 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 38406 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 66867 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 28461 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 38406 # number of overall hits system.cpu.l2cache.overall_hits::total 66867 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 4707 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 21944 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 26651 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 102253 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102253 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 4707 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124197 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 128904 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 4707 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124197 # number of overall misses system.cpu.l2cache.overall_misses::total 128904 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 270210000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1641574500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1911784500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 45500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 45500 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8095497000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8095497000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 270210000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9737071500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 10007281500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 270210000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9737071500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 10007281500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 33168 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55581 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 88749 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 129149 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 129149 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 325 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 325 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107022 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107022 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 33168 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 162603 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 195771 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 33168 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 162603 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 195771 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.141914 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.394811 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.300296 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947692 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947692 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955439 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955439 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141914 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.763805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.658443 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141914 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.763805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.658443 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57405.991077 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74807.441670 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 71734.062512 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.727273 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.727273 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79171.241920 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79171.241920 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57405.991077 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78400.214981 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 77633.599423 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57405.991077 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78400.214981 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 77633.599423 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 83948 # number of writebacks system.cpu.l2cache.writebacks::total 83948 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21879 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 26570 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102253 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102253 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 4691 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 124132 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 128823 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 4691 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124132 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128823 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210199490 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1366008240 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1576207730 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3082308 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3082308 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6824605081 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6824605081 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210199490 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8190613321 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 8400812811 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210199490 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8190613321 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 8400812811 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.393642 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299384 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955439 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955439 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.658029 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.658029 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44809.100405 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62434.674345 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59322.835152 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10007.493506 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10007.493506 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66742.345760 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66742.345760 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44809.100405 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65983.093167 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65212.056939 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44809.100405 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65983.093167 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65212.056939 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------