---------- Begin Simulation Statistics ---------- sim_seconds 1.222275 # Number of seconds simulated sim_ticks 1222274983500 # Number of ticks simulated final_tick 1222274983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 407632 # Simulator instruction rate (inst/s) host_op_rate 407632 # Simulator op (including micro ops) rate (op/s) host_tick_rate 272801132 # Simulator tick rate (ticks/s) host_mem_usage 256700 # Number of bytes of host memory used host_seconds 4480.46 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 61440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 126177664 # Number of bytes read from this memory system.physmem.bytes_read::total 126239104 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 61440 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 61440 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 66092544 # Number of bytes written to this memory system.physmem.bytes_written::total 66092544 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 960 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1971526 # Number of read requests responded to by this memory system.physmem.num_reads::total 1972486 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1032696 # Number of write requests responded to by this memory system.physmem.num_writes::total 1032696 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 50267 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 103231814 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 103282081 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 50267 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 50267 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 54073384 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 54073384 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 54073384 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 50267 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 103231814 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 157355465 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1972486 # Number of read requests accepted system.physmem.writeReqs 1032696 # Number of write requests accepted system.physmem.readBursts 1972486 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1032696 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 126156992 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue system.physmem.bytesWritten 66090816 # Total number of bytes written to DRAM system.physmem.bytesReadSys 126239104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 66092544 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 119355 # Per bank write bursts system.physmem.perBankRdBursts::1 114736 # Per bank write bursts system.physmem.perBankRdBursts::2 116711 # Per bank write bursts system.physmem.perBankRdBursts::3 118315 # Per bank write bursts system.physmem.perBankRdBursts::4 118360 # Per bank write bursts system.physmem.perBankRdBursts::5 118227 # Per bank write bursts system.physmem.perBankRdBursts::6 120694 # Per bank write bursts system.physmem.perBankRdBursts::7 125539 # Per bank write bursts system.physmem.perBankRdBursts::8 127875 # Per bank write bursts system.physmem.perBankRdBursts::9 130856 # Per bank write bursts system.physmem.perBankRdBursts::10 129453 # Per bank write bursts system.physmem.perBankRdBursts::11 131175 # Per bank write bursts system.physmem.perBankRdBursts::12 126741 # Per bank write bursts system.physmem.perBankRdBursts::13 125953 # Per bank write bursts system.physmem.perBankRdBursts::14 123325 # Per bank write bursts system.physmem.perBankRdBursts::15 123888 # Per bank write bursts system.physmem.perBankWrBursts::0 62004 # Per bank write bursts system.physmem.perBankWrBursts::1 62322 # Per bank write bursts system.physmem.perBankWrBursts::2 61319 # Per bank write bursts system.physmem.perBankWrBursts::3 62011 # Per bank write bursts system.physmem.perBankWrBursts::4 62436 # Per bank write bursts system.physmem.perBankWrBursts::5 63988 # Per bank write bursts system.physmem.perBankWrBursts::6 65064 # Per bank write bursts system.physmem.perBankWrBursts::7 66489 # Per bank write bursts system.physmem.perBankWrBursts::8 66234 # Per bank write bursts system.physmem.perBankWrBursts::9 66705 # Per bank write bursts system.physmem.perBankWrBursts::10 66339 # Per bank write bursts system.physmem.perBankWrBursts::11 66709 # Per bank write bursts system.physmem.perBankWrBursts::12 65174 # Per bank write bursts system.physmem.perBankWrBursts::13 65212 # Per bank write bursts system.physmem.perBankWrBursts::14 65629 # Per bank write bursts system.physmem.perBankWrBursts::15 65034 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 1222274866500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 1972486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1032696 # Write request sizes (log2) system.physmem.rdQLenPdf::0 1847755 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 123438 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 30048 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 31196 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 55895 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 61015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 61109 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 61152 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 61095 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 61085 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 61106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 61082 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 61071 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 61082 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 61067 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 61245 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 61296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 60829 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 60715 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 60557 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1846311 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 104.123632 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 81.172382 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 131.523418 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 1463397 79.26% 79.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 266113 14.41% 93.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 48771 2.64% 96.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 20101 1.09% 97.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 12770 0.69% 98.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 7489 0.41% 98.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 5280 0.29% 98.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 4734 0.26% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 17656 0.96% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1846311 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 60557 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 32.510131 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::gmean 23.099317 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 136.122575 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 60389 99.72% 99.72% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 130 0.21% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 8 0.01% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3583 1 0.00% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3584-4095 4 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 60557 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 60557 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.052843 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.021089 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 1.041900 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 29161 48.15% 48.15% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 1164 1.92% 50.08% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 28160 46.50% 96.58% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 2021 3.34% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 45 0.07% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 6 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 60557 # Writes before turning the bus around for reads system.physmem.totQLat 36942736250 # Total ticks spent queuing system.physmem.totMemAccLat 73902792500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 9856015000 # Total ticks spent in databus transfers system.physmem.avgQLat 18741.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 37491.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 103.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 54.07 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 103.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 54.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing system.physmem.readRowHits 727606 # Number of row buffer hits during reads system.physmem.writeRowHits 429946 # Number of row buffer hits during writes system.physmem.readRowHitRate 36.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes system.physmem.avgGap 406722.41 # Average gap between requests system.physmem.pageHitRate 38.53 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6766986240 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3692304000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 7425061800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 3276501840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 416045775330 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 368409693000 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 885449053890 # Total energy per rank (pJ) system.physmem_0.averagePower 724.429872 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 610096075500 # Time in different power states system.physmem_0.memoryStateTime::REF 40814280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 571360638500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 7191102240 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 3923716500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 7949838000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 3415193280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 427319070030 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 358520838000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 888152489730 # Total energy per rank (pJ) system.physmem_1.averagePower 726.641687 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 593574305750 # Time in different power states system.physmem_1.memoryStateTime::REF 40814280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 587881640500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 246953326 # Number of BP lookups system.cpu.branchPred.condPredicted 186908369 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15587365 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 168276583 # Number of BTB lookups system.cpu.branchPred.BTBHits 165592346 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 98.404866 # BTB Hit Percentage system.cpu.branchPred.usedRAS 18556185 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 105918 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 63 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 252 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 453405484 # DTB read hits system.cpu.dtb.read_misses 5001335 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 458406819 # DTB read accesses system.cpu.dtb.write_hits 161377349 # DTB write hits system.cpu.dtb.write_misses 1709149 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 163086498 # DTB write accesses system.cpu.dtb.data_hits 614782833 # DTB hits system.cpu.dtb.data_misses 6710484 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 621493317 # DTB accesses system.cpu.itb.fetch_hits 600105517 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_accesses 600105536 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls system.cpu.pwrStateResidencyTicks::ON 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2444549967 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed system.cpu.discardedOps 55126564 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.338468 # CPI: cycles per instruction system.cpu.ipc 0.747123 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1826378509 # Class of committed instruction system.cpu.tickCycles 2082292947 # Number of cycles that the object actually ticked system.cpu.idleCycles 362257020 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9121995 # number of replacements system.cpu.dcache.tags.tagsinuse 4080.838657 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 602779955 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9126091 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 66.050180 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16887433500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4080.838657 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996299 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996299 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2420 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1233656307 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1233656307 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 444297476 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 444297476 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158482479 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 158482479 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 602779955 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 602779955 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 602779955 # number of overall hits system.cpu.dcache.overall_hits::total 602779955 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7239130 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7239130 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2246023 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2246023 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 9485153 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9485153 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9485153 # number of overall misses system.cpu.dcache.overall_misses::total 9485153 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 185791393500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 185791393500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 110650401500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 110650401500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 296441795000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 296441795000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 296441795000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 296441795000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 451536606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 451536606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 612265108 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 612265108 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 612265108 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 612265108 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013974 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013974 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015492 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015492 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015492 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015492 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25664.878722 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 25664.878722 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49265.034908 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 49265.034908 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 31253.243358 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 31253.243358 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 3671998 # number of writebacks system.cpu.dcache.writebacks::total 3671998 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 362 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 358700 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 358700 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 359062 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 359062 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 359062 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 359062 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238768 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7238768 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 9126091 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9126091 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9126091 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9126091 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 178546113500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 178546113500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85195528000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 85195528000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263741641500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 263741641500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263741641500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 263741641500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24665.262583 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24665.262583 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45140.936660 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45140.936660 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 752.723923 # Cycle average of tags in use system.cpu.icache.tags.total_refs 600104557 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 960 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 625108.913542 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 752.723923 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.367541 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.367541 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.467285 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1200211994 # Number of tag accesses system.cpu.icache.tags.data_accesses 1200211994 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 600104557 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 600104557 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 600104557 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 600104557 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 600104557 # number of overall hits system.cpu.icache.overall_hits::total 600104557 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 960 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 960 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 960 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 960 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 960 # number of overall misses system.cpu.icache.overall_misses::total 960 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 77923500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 77923500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 77923500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 77923500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 77923500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 77923500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 600105517 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 600105517 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 600105517 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 600105517 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 600105517 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 600105517 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81170.312500 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 81170.312500 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 81170.312500 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 81170.312500 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 81170.312500 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 81170.312500 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 3 # number of writebacks system.cpu.icache.writebacks::total 3 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 960 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 960 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 960 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 960 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 960 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76963500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 76963500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76963500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 76963500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76963500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 76963500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80170.312500 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80170.312500 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80170.312500 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 80170.312500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80170.312500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 80170.312500 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1940039 # number of replacements system.cpu.l2cache.tags.tagsinuse 31449.191087 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 16276000 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1972807 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 8.250173 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 89114668000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 7.970416 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.267708 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 31398.952962 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000243 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001290 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.958220 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.959753 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1022 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2732 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7097 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21795 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 147965199 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 147965199 # Number of data accesses system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3671998 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3671998 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1095273 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1095273 # number of ReadExReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6059292 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6059292 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.data 7154565 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7154565 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.data 7154565 # number of overall hits system.cpu.l2cache.overall_hits::total 7154565 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 792050 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 792050 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 960 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 960 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1179476 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1179476 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 960 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1971526 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 1972486 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 960 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1971526 # number of overall misses system.cpu.l2cache.overall_misses::total 1972486 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70794470500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 70794470500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75521000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 75521000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104049458500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 104049458500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 75521000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 174843929000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 174919450000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 75521000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 174843929000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 174919450000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 3671998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 3671998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887323 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1887323 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 960 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 960 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238768 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 7238768 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 960 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9126091 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9127051 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 960 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9126091 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9127051 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419668 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.419668 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162939 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162939 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.216032 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.216114 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.216032 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.216114 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89381.314942 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89381.314942 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78667.708333 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78667.708333 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88216.681391 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88216.681391 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78667.708333 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88684.566676 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 88679.691516 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78667.708333 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88684.566676 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 88679.691516 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 1032696 # number of writebacks system.cpu.l2cache.writebacks::total 1032696 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792050 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 792050 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 960 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 960 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1179476 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1179476 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 960 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1971526 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 1972486 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 960 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1971526 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1972486 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62873970500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62873970500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65921000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65921000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 92254698500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 92254698500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65921000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 155128669000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 155194590000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65921000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 155128669000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 155194590000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419668 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419668 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162939 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162939 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.216114 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.216114 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79381.314942 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79381.314942 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68667.708333 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68667.708333 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78216.681391 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78216.681391 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18249049 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121998 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1439 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7239728 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4704694 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6357340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 960 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238768 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374177 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27376100 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819077696 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 819139328 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 1940039 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 66092544 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 11067090 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.011402 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 11065651 99.99% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1439 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 11067090 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12796525500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1440000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13689136500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.snoop_filter.tot_requests 3911328 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 1938842 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1180436 # Transaction distribution system.membus.trans_dist::WritebackDirty 1032696 # Transaction distribution system.membus.trans_dist::CleanEvict 906146 # Transaction distribution system.membus.trans_dist::ReadExReq 792050 # Transaction distribution system.membus.trans_dist::ReadExResp 792050 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1180436 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883814 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 5883814 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192331648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 192331648 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1972486 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 1972486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1972486 # Request fanout histogram system.membus.reqLayer0.occupancy 8508050000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 10787775250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ----------