---------- Begin Simulation Statistics ---------- sim_seconds 1.116876 # Number of seconds simulated sim_ticks 1116876142500 # Number of ticks simulated final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 161785 # Simulator instruction rate (inst/s) host_op_rate 174299 # Simulator op (including micro ops) rate (op/s) host_tick_rate 116987267 # Simulator tick rate (ticks/s) host_mem_usage 309392 # Number of bytes of host memory used host_seconds 9546.99 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 2046592 # Number of read requests accepted system.physmem.writeReqs 1050124 # Number of write requests accepted system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 127284 # Per bank write bursts system.physmem.perBankRdBursts::1 124662 # Per bank write bursts system.physmem.perBankRdBursts::2 121597 # Per bank write bursts system.physmem.perBankRdBursts::3 123658 # Per bank write bursts system.physmem.perBankRdBursts::4 122617 # Per bank write bursts system.physmem.perBankRdBursts::5 122675 # Per bank write bursts system.physmem.perBankRdBursts::6 123246 # Per bank write bursts system.physmem.perBankRdBursts::7 123759 # Per bank write bursts system.physmem.perBankRdBursts::8 131397 # Per bank write bursts system.physmem.perBankRdBursts::9 133511 # Per bank write bursts system.physmem.perBankRdBursts::10 132080 # Per bank write bursts system.physmem.perBankRdBursts::11 133309 # Per bank write bursts system.physmem.perBankRdBursts::12 133252 # Per bank write bursts system.physmem.perBankRdBursts::13 133368 # Per bank write bursts system.physmem.perBankRdBursts::14 129308 # Per bank write bursts system.physmem.perBankRdBursts::15 129546 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts system.physmem.perBankWrBursts::2 62576 # Per bank write bursts system.physmem.perBankWrBursts::3 63006 # Per bank write bursts system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts system.physmem.perBankWrBursts::7 65435 # Per bank write bursts system.physmem.perBankWrBursts::8 67311 # Per bank write bursts system.physmem.perBankWrBursts::9 67795 # Per bank write bursts system.physmem.perBankWrBursts::10 67548 # Per bank write bursts system.physmem.perBankWrBursts::11 67883 # Per bank write bursts system.physmem.perBankWrBursts::12 67328 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts system.physmem.perBankWrBursts::14 66483 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 1116876049000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 2046592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1050124 # Write request sizes (log2) system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads system.physmem.totQLat 38139021250 # Total ticks spent queuing system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.39 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing system.physmem.readRowHits 773003 # Number of row buffer hits during reads system.physmem.writeRowHits 411872 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes system.physmem.avgGap 360664.67 # Average gap between requests system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ) system.physmem_0.averagePower 731.183278 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ) system.physmem_1.averagePower 733.276976 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 239639069 # Number of BP lookups system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 2233752285 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.446203 # CPI: cycles per instruction system.cpu.ipc 0.691466 # IPC: instructions per cycle system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 9221039 # number of replacements system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits system.cpu.dcache.overall_hits::total 624218783 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses system.cpu.dcache.overall_misses::total 9589485 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3684564 # number of writebacks system.cpu.dcache.writebacks::total 3684564 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364134 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 364134 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 364349 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 364349 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 364349 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 364349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890852 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84766639000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 84766639000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 268376457500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 268376531500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements system.cpu.icache.tags.tagsinuse 661.386126 # Cycle average of tags in use system.cpu.icache.tags.total_refs 465281345 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 567416.274390 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 661.386126 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 930565150 # Number of tag accesses system.cpu.icache.tags.data_accesses 930565150 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 465281345 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 465281345 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 465281345 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 465281345 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 465281345 # number of overall hits system.cpu.icache.overall_hits::total 465281345 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 62363500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 62363500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 62363500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 62363500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 62363500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 62363500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 465282165 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 465282165 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 465282165 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 465282165 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 465282165 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 465282165 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 76053.048780 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 76053.048780 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61543500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 61543500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61543500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 61543500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61543500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 61543500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 2013891 # number of replacements system.cpu.l2cache.tags.tagsinuse 31258.308104 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14509189 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2043666 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.099589 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588444 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.452649 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151497950 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151497950 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1089696 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1089696 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 7179326 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7179358 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 7179326 # number of overall hits system.cpu.l2cache.overall_hits::total 7179358 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 801156 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 801156 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 788 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 788 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 2045809 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2045809 # number of overall misses system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70430633500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 70430633500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59976000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 59976000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108661637000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 59976000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 179152246500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 59976000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 179152246500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3684564 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890852 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1890852 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 820 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 820 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334283 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 7334283 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9225135 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9225955 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9225135 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9225955 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423701 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.423701 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.960976 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.960976 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169703 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169703 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1050124 # number of writebacks system.cpu.l2cache.writebacks::total 1050124 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801156 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 801156 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52090500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52090500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96214883500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96214883500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52090500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52090500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423701 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.959756 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334283 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669715 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27671384 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 2013891 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 1245436 # Transaction distribution system.membus.trans_dist::Writeback 1050124 # Transaction distribution system.membus.trans_dist::CleanEvict 962723 # Transaction distribution system.membus.trans_dist::ReadExReq 801156 # Transaction distribution system.membus.trans_dist::ReadExResp 801156 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 4059439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 4059439 # Request fanout histogram system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ----------