---------- Begin Simulation Statistics ---------- sim_seconds 0.074057 # Number of seconds simulated sim_ticks 74056845500 # Number of ticks simulated final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 115398 # Simulator instruction rate (inst/s) host_op_rate 126351 # Simulator op (including micro ops) rate (op/s) host_tick_rate 49598898 # Simulator tick rate (ticks/s) host_mem_usage 265028 # Number of bytes of host memory used host_seconds 1493.11 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory system.physmem.bytes_read::total 244032 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3814 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 307 # Per bank write bursts system.physmem.perBankRdBursts::1 215 # Per bank write bursts system.physmem.perBankRdBursts::2 134 # Per bank write bursts system.physmem.perBankRdBursts::3 310 # Per bank write bursts system.physmem.perBankRdBursts::4 299 # Per bank write bursts system.physmem.perBankRdBursts::5 300 # Per bank write bursts system.physmem.perBankRdBursts::6 265 # Per bank write bursts system.physmem.perBankRdBursts::7 223 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts system.physmem.perBankRdBursts::9 213 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts system.physmem.perBankRdBursts::11 196 # Per bank write bursts system.physmem.perBankRdBursts::12 190 # Per bank write bursts system.physmem.perBankRdBursts::13 207 # Per bank write bursts system.physmem.perBankRdBursts::14 219 # Per bank write bursts system.physmem.perBankRdBursts::15 201 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts system.physmem.perBankWrBursts::4 0 # Per bank write bursts system.physmem.perBankWrBursts::5 0 # Per bank write bursts system.physmem.perBankWrBursts::6 0 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts system.physmem.perBankWrBursts::10 0 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 74056827000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 3814 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation system.physmem.totQLat 30109750 # Total ticks spent queuing system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 3033 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 19417101.99 # Average gap between requests system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states system.physmem.memoryStateTime::REF 2472860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 861203250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 3295198 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2737 # Transaction distribution system.membus.trans_dist::ReadResp 2736 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 1077 # Transaction distribution system.membus.trans_dist::ReadExResp 1077 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 244032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 95688557 # Number of BP lookups system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 148113692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued system.cpu.iq.rate 1.695316 # Inst issue rate system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 17056 # number of nop insts executed system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed system.cpu.iew.exec_branches 53733408 # Number of branches executed system.cpu.iew.exec_stores 13766008 # Number of stores executed system.cpu.iew.exec_rate 1.652154 # Inst execution rate system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back system.cpu.iew.wb_producers 150213875 # num instructions producing a value system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 42494118 # Number of memory references committed system.cpu.commit.loads 29849484 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed system.cpu.commit.branches 40300311 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 144055022 76.35% 76.35% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 908940 0.48% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 76.83% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 76.85% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 76.85% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.08% 76.93% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.06% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.23% 77.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 452847863 # The number of ROB reads system.cpu.rob.rob_writes 690972129 # The number of ROB writes system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads system.cpu.int_regfile_writes 386673292 # number of integer regfile writes system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2387 # number of replacements system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.846680 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 74789015 # Number of tag accesses system.cpu.icache.tags.data_accesses 74789015 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 37387126 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 37387126 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 37387126 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 37387126 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 37387126 # number of overall hits system.cpu.icache.overall_hits::total 37387126 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5320 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5320 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5320 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5320 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5320 # number of overall misses system.cpu.icache.overall_misses::total 5320 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 224799997 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 224799997 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 224799997 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 224799997 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 224799997 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 224799997 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 37392446 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 37392446 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 37392446 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 37392446 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 37392446 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 37392446 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42255.638534 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 42255.638534 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 42255.638534 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 42255.638534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1071 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1196 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 1196 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 1196 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 1196 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1196 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1196 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168596253 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 168596253 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168596253 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 168596253 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168596253 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 168596253 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000110 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000110 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000110 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40881.729631 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40881.729631 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 1967.769315 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2148 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2745 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.782514 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 4.017679 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1427.875766 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 535.875870 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043575 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.016354 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.060052 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2745 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 608 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083771 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 51829 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 51829 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2058 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 89 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2147 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 2058 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2154 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2058 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits system.cpu.l2cache.overall_hits::total 2154 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2064 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 687 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 2751 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1077 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1077 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2064 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1764 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 3828 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2064 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1764 # number of overall misses system.cpu.l2cache.overall_misses::total 3828 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143880250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49531000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 193411250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74080000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 74080000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 143880250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 123611000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 267491250 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 143880250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 123611000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 267491250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4122 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 776 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4898 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1084 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1084 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 4122 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1860 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 5982 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4122 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1860 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 5982 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.500728 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885309 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.561658 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993542 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.993542 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.500728 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.948387 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.639920 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.500728 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948387 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.639920 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69709.423450 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72097.525473 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 70305.797892 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68783.658310 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68783.658310 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69709.423450 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70074.263039 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 69877.547022 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69709.423450 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70074.263039 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 69877.547022 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2061 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 676 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 2737 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1077 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1077 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2061 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3814 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2061 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3814 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117822250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40424500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158246750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60589000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60589000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117822250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101013500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 218835750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117822250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101013500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 218835750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.558800 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993542 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993542 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.637579 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.637579 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57167.515769 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59799.556213 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57817.592254 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56257.195915 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56257.195915 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 56 # number of replacements system.cpu.dcache.tags.tagsinuse 1410.171492 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 47073011 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1860 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25308.070430 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.440430 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 94167216 # Number of tag accesses system.cpu.dcache.tags.data_accesses 94167216 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 34671591 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits system.cpu.dcache.overall_hits::total 47028125 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses system.cpu.dcache.overall_misses::total 9667 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------