---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated sim_ticks 9834500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 38040 # Simulator instruction rate (inst/s) host_tick_rate 65174027 # Simulator tick rate (ticks/s) host_mem_usage 253652 # Number of bytes of host memory used host_seconds 0.15 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls system.cpu.numCycles 19670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 2538 # Number of BP lookups system.cpu.BPredUnit.condPredicted 1884 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 1886 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 760 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 6290 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12764 # Number of instructions fetch has processed system.cpu.fetch.Branches 2538 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1028 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2852 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1670 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1030 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2054 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 11334 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.423857 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.772019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 8482 74.84% 74.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 284 2.51% 77.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 192 1.69% 79.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 246 2.17% 81.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 242 2.14% 83.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 324 2.86% 86.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 124 1.09% 87.29% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 120 1.06% 88.35% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1320 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 11334 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.129029 # Number of branch fetches per cycle system.cpu.fetch.rate 0.648907 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6573 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1079 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2654 # Number of cycles decode is running system.cpu.decode.UnblockCycles 60 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 14169 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 6862 # Number of cycles rename is idle system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2422 # Number of cycles rename is running system.cpu.rename.UnblockCycles 183 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 13321 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12898 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 60750 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 59430 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 7209 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2701 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1759 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11506 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 9339 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5207 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14048 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 11334 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.823981 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.484525 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 7613 67.17% 67.17% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1341 11.83% 79.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 855 7.54% 86.54% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 564 4.98% 91.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 476 4.20% 95.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 284 2.51% 98.23% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 147 1.30% 99.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 42 0.37% 99.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 11334 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.79% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 138 64.19% 66.98% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 5727 61.32% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7 0.07% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2324 24.88% 86.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1278 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 9339 # Type of FU issued system.cpu.iq.rate 0.474784 # Inst issue rate system.cpu.iq.fu_busy_cnt 215 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023022 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 30256 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16705 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8361 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 9514 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1500 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 11534 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 218 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2701 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1759 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8897 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 3 # number of nop insts executed system.cpu.iew.exec_refs 3351 # number of memory reference insts executed system.cpu.iew.exec_branches 1479 # Number of branches executed system.cpu.iew.exec_stores 1222 # Number of stores executed system.cpu.iew.exec_rate 0.452313 # Inst execution rate system.cpu.iew.wb_sent 8556 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8377 # cumulative count of insts written-back system.cpu.iew.wb_producers 3980 # num instructions producing a value system.cpu.iew.wb_consumers 7830 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.425877 # insts written-back per cycle system.cpu.iew.wb_fanout 0.508301 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions system.cpu.commit.commitSquashedInsts 5640 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 351 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 10367 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.553583 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.355703 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 8010 77.26% 77.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1098 10.59% 87.86% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 433 4.18% 92.03% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 284 2.74% 94.77% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 184 1.77% 96.55% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 168 1.62% 98.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 67 0.65% 98.81% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 39 0.38% 99.19% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 84 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 10367 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed system.cpu.commit.loads 1201 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed system.cpu.commit.branches 945 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 21505 # The number of ROB reads system.cpu.rob.rob_writes 23748 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 8336 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated system.cpu.cpi 3.427426 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.427426 # CPI: Total CPI of All Threads system.cpu.ipc 0.291764 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.291764 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 40468 # number of integer regfile reads system.cpu.int_regfile_writes 8226 # number of integer regfile writes system.cpu.fp_regfile_reads 29 # number of floating regfile reads system.cpu.misc_regfile_reads 15801 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.tagsinuse 150.859133 # Cycle average of tags in use system.cpu.icache.total_refs 1688 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.702703 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::0 150.859133 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.073662 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits 1688 # number of ReadReq hits system.cpu.icache.demand_hits 1688 # number of demand (read+write) hits system.cpu.icache.overall_hits 1688 # number of overall hits system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses system.cpu.icache.demand_misses 366 # number of demand (read+write) misses system.cpu.icache.overall_misses 366 # number of overall misses system.cpu.icache.ReadReq_miss_latency 12656500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency 12656500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 12656500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses 2054 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses 2054 # number of demand (read+write) accesses system.cpu.icache.overall_accesses 2054 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.178189 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.178189 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.178189 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency 34580.601093 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency 34580.601093 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 34580.601093 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency 9940500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 9940500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 9940500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.144109 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.144109 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.144109 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 33582.770270 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 92.281770 # Cycle average of tags in use system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.512821 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 92.281770 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.022530 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1791 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits 2400 # number of demand (read+write) hits system.cpu.dcache.overall_hits 2400 # number of overall hits system.cpu.dcache.ReadReq_misses 178 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses system.cpu.dcache.overall_misses 482 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 5526000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency 16231500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency 16231500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1969 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses 2882 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 2882 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.090401 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.167245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.167245 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 31044.943820 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency 33675.311203 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 33675.311203 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits 326 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits 326 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.057897 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.054129 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.054129 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 190.940380 # Cycle average of tags in use system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::0 190.940380 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.005827 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 43 # number of overall hits system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 409 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 12612500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency 14063000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 14063000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses 452 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.895122 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency 34366.485014 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency 34383.863081 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 34383.863081 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency 11305500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 12622500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 12622500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31230.662983 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------