---------- Begin Simulation Statistics ---------- host_inst_rate 739167 # Simulator instruction rate (inst/s) host_mem_usage 360776 # Number of bytes of host memory used host_seconds 68.93 # Real time elapsed on the host host_tick_rate 374609475 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 50949504 # Number of instructions simulated sim_seconds 0.025821 # Number of seconds simulated sim_ticks 25821310500 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses::0 96794 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 96794 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits::0 91895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 91895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses::0 4899 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4899 # number of LoadLockedReq misses system.cpu.dcache.ReadReq_accesses::0 7714516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 7714516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_hits::0 7482193 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7482193 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_rate::0 0.030115 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses::0 232323 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 232323 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses::0 96793 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 96793 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits::0 96793 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 96793 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses::0 6604860 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6604860 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_hits::0 6433311 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6433311 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_rate::0 0.025973 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses::0 171549 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 171549 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 34.663994 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses::0 14319376 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 14319376 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.demand_hits::0 13915504 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 13915504 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate::0 0.028205 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dcache.demand_misses::0 403872 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 403872 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999475 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 511.731250 # Average occupied blocks per context system.cpu.dcache.overall_accesses::0 14319376 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 14319376 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits::0 13915504 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits system.cpu.dcache.overall_hits::total 13915504 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate::0 0.028205 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dcache.overall_misses::0 403872 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses system.cpu.dcache.overall_misses::total 403872 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 406424 # number of replacements system.cpu.dcache.sampled_refs 406936 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 511.731250 # Cycle average of tags in use system.cpu.dcache.total_refs 14106027 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21760000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 379025 # number of writebacks system.cpu.dtb.accesses 15336291 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 2242 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 15330762 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 5529 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 768 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 8622893 # DTB read accesses system.cpu.dtb.read_hits 8618361 # DTB read hits system.cpu.dtb.read_misses 4532 # DTB read misses system.cpu.dtb.write_accesses 6713398 # DTB write accesses system.cpu.dtb.write_hits 6712401 # DTB write hits system.cpu.dtb.write_misses 997 # DTB write misses system.cpu.icache.ReadReq_accesses::0 41172623 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 41172623 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_hits::0 40741841 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 40741841 # number of ReadReq hits system.cpu.icache.ReadReq_miss_rate::0 0.010463 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses::0 430782 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 430782 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 94.576690 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses::0 41172623 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 41172623 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.demand_hits::0 40741841 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 40741841 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate::0 0.010463 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.icache.demand_misses::0 430782 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 430782 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.929162 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 475.731149 # Average occupied blocks per context system.cpu.icache.overall_accesses::0 41172623 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 41172623 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits::0 40741841 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits system.cpu.icache.overall_hits::total 40741841 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate::0 0.010463 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.icache.overall_misses::0 430782 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses system.cpu.icache.overall_misses::total 430782 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 430269 # number of replacements system.cpu.icache.sampled_refs 430781 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 475.731149 # Cycle average of tags in use system.cpu.icache.total_refs 40741841 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 4544230000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 33727 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.itb.accesses 41173750 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 41170928 # DTB hits system.cpu.itb.inst_accesses 41173750 # ITB inst accesses system.cpu.itb.inst_hits 41170928 # ITB inst hits system.cpu.itb.inst_misses 2822 # ITB inst misses system.cpu.itb.misses 2822 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 51642622 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 51642622 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses system.cpu.num_fp_insts 6059 # number of float instructions system.cpu.num_fp_register_reads 4227 # number of times the floating registers were read system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 50949504 # Number of instructions executed system.cpu.num_int_alu_accesses 41395090 # Number of integer alu accesses system.cpu.num_int_insts 41395090 # number of integer instructions system.cpu.num_int_register_reads 128438705 # number of times the integer registers were read system.cpu.num_int_register_writes 33973128 # number of times the integer registers were written system.cpu.num_load_insts 9082722 # Number of load instructions system.cpu.num_mem_refs 16092645 # number of memory refs system.cpu.num_store_insts 7009923 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses system.iocache.demand_misses::1 0 # number of demand (read+write) misses system.iocache.demand_misses::total 0 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 0 # number of overall misses system.iocache.overall_misses::total 0 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.replacements 0 # number of replacements system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks system.l2c.ReadExReq_accesses::0 169714 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 169714 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_hits::0 60310 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 60310 # number of ReadExReq hits system.l2c.ReadExReq_miss_rate::0 0.644637 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses::0 109404 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 109404 # number of ReadExReq misses system.l2c.ReadReq_accesses::0 665898 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::1 6073 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 671971 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_hits::0 648226 # number of ReadReq hits system.l2c.ReadReq_hits::1 6049 # number of ReadReq hits system.l2c.ReadReq_hits::total 654275 # number of ReadReq hits system.l2c.ReadReq_miss_rate::0 0.026539 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::1 0.003952 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.030491 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 17672 # number of ReadReq misses system.l2c.ReadReq_misses::1 24 # number of ReadReq misses system.l2c.ReadReq_misses::total 17696 # number of ReadReq misses system.l2c.UpgradeReq_accesses::0 1835 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits system.l2c.UpgradeReq_miss_rate::0 0.990736 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses::0 1818 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 1818 # number of UpgradeReq misses system.l2c.Writeback_accesses::0 412752 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 412752 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 412752 # number of Writeback hits system.l2c.Writeback_hits::total 412752 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 6.885433 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses::0 835612 # number of demand (read+write) accesses system.l2c.demand_accesses::1 6073 # number of demand (read+write) accesses system.l2c.demand_accesses::total 841685 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.demand_hits::0 708536 # number of demand (read+write) hits system.l2c.demand_hits::1 6049 # number of demand (read+write) hits system.l2c.demand_hits::total 714585 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate::0 0.152075 # miss rate for demand accesses system.l2c.demand_miss_rate::1 0.003952 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.156027 # miss rate for demand accesses system.l2c.demand_misses::0 127076 # number of demand (read+write) misses system.l2c.demand_misses::1 24 # number of demand (read+write) misses system.l2c.demand_misses::total 127100 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.occ_%::0 0.072507 # Average percentage of cache occupancy system.l2c.occ_%::1 0.478199 # Average percentage of cache occupancy system.l2c.occ_blocks::0 4751.792305 # Average occupied blocks per context system.l2c.occ_blocks::1 31339.221407 # Average occupied blocks per context system.l2c.overall_accesses::0 835612 # number of overall (read+write) accesses system.l2c.overall_accesses::1 6073 # number of overall (read+write) accesses system.l2c.overall_accesses::total 841685 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits::0 708536 # number of overall hits system.l2c.overall_hits::1 6049 # number of overall hits system.l2c.overall_hits::total 714585 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate::0 0.152075 # miss rate for overall accesses system.l2c.overall_miss_rate::1 0.003952 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.156027 # miss rate for overall accesses system.l2c.overall_misses::0 127076 # number of overall misses system.l2c.overall_misses::1 24 # number of overall misses system.l2c.overall_misses::total 127100 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 95922 # number of replacements system.l2c.sampled_refs 125830 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.tagsinuse 36091.013712 # Cycle average of tags in use system.l2c.total_refs 866394 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 90126 # number of writebacks ---------- End Simulation Statistics ----------