================ Begin RubySystem Configuration Print ================ RubySystem config: random_seed: 1234 randomization: 1 cycle_period: 1 block_size_bytes: 64 block_size_bits: 6 memory_size_bytes: 134217728 memory_size_bits: 27 Network Configuration --------------------- network: SIMPLE_NETWORK topology: virtual_net_0: active, ordered virtual_net_1: active, ordered virtual_net_2: active, unordered virtual_net_3: active, unordered virtual_net_4: active, unordered virtual_net_5: active, unordered virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive virtual_net_9: inactive Profiler Configuration ---------------------- periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ Real time: Apr/28/2011 15:12:18 Profiler Stats -------------- Elapsed_time_in_seconds: 0 Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 Virtual_time_in_seconds: 0.47 Virtual_time_in_minutes: 0.00783333 Virtual_time_in_hours: 0.000130556 Virtual_time_in_days: 5.43981e-06 Ruby_current_time: 218861 Ruby_start_time: 0 Ruby_cycles: 218861 mbytes_resident: 35.7695 mbytes_total: 219.633 resident_ratio: 0.162914 ruby_cycles_executed: [ 218862 ] Busy Controller Counts: L1Cache-0:0 Directory-0:0 Busy Bank Count:0 sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1005 average: 15.808 | standard deviation: 1.13264 | 0 1 1 1 1 1 1 1 1 1 1 1 1 2 4 65 922 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 128 max: 15144 count: 990 average: 3497.61 | standard deviation: 1761.96 | 94 4 26 34 22 11 5 2 0 0 2 0 0 2 0 0 1 0 1 0 0 1 3 1 3 8 16 24 44 55 84 62 81 68 73 52 45 41 35 22 24 22 9 3 1 2 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 32 max: 5449 count: 40 average: 3885.72 | standard deviation: 1329.57 | 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 2 1 0 4 1 0 0 1 1 0 1 0 0 0 0 2 0 1 0 0 1 0 1 1 0 0 0 3 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 ] miss_latency_ST: [binsize: 128 max: 15144 count: 890 average: 3688.06 | standard deviation: 1639.42 | 83 2 16 13 12 4 3 1 0 0 2 0 0 2 0 0 1 0 1 0 0 1 3 1 2 8 14 24 42 51 78 60 80 66 71 50 42 38 34 21 22 21 8 3 1 2 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH: [binsize: 8 max: 999 count: 60 average: 413.883 | standard deviation: 232.639 | 6 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 5 1 1 0 0 1 0 1 0 0 0 0 0 1 3 4 3 0 2 1 0 0 1 0 0 0 2 1 1 2 0 1 1 0 1 0 0 0 0 1 2 1 3 0 0 0 0 1 0 0 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 13.2051 | standard deviation: 32.1294 | 0 21 15 17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 0 1 1 0 0 0 0 1 0 1 ] miss_latency_L2Cache: [binsize: 128 max: 15144 count: 38 average: 3161.37 | standard deviation: 3572.78 | 16 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 2 1 1 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_Directory: [binsize: 32 max: 5926 count: 874 average: 3823.2 | standard deviation: 1334.21 | 0 0 0 0 0 2 2 0 9 7 2 8 16 4 3 11 4 1 10 6 1 5 4 1 0 2 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 1 0 1 0 1 1 2 1 1 4 3 2 6 4 2 7 7 8 8 9 15 10 13 13 8 20 17 18 24 23 18 9 19 15 21 21 16 22 24 8 21 13 24 18 15 15 16 12 12 10 9 11 11 12 12 5 11 13 7 10 10 8 2 9 8 3 5 10 6 3 9 4 5 4 6 1 2 0 2 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_wCC_Times: 0 miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 874 miss_latency_LD_L1Cache: [binsize: 1 max: 115 count: 2 average: 59 | standard deviation: 79.196 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_LD_Directory: [binsize: 32 max: 5449 count: 38 average: 4087.13 | standard deviation: 1014.85 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 2 1 0 4 1 0 0 1 1 0 1 0 0 0 0 2 0 1 0 0 1 0 1 1 0 0 0 3 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 ] miss_latency_ST_L1Cache: [binsize: 1 max: 113 count: 75 average: 12.1333 | standard deviation: 30.4935 | 0 21 14 16 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 0 1 1 0 0 0 0 1 ] miss_latency_ST_L2Cache: [binsize: 128 max: 15144 count: 30 average: 3999.4 | standard deviation: 3582.58 | 8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 2 1 1 2 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_ST_Directory: [binsize: 32 max: 5926 count: 785 average: 4027.37 | standard deviation: 1077.58 | 0 0 0 0 0 1 1 0 3 5 1 7 6 1 2 4 2 0 6 3 0 2 2 0 0 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 1 0 0 0 1 1 2 1 1 4 2 2 5 4 2 7 7 8 7 9 14 10 11 13 8 18 16 18 20 22 18 9 18 14 21 20 16 22 24 8 19 13 23 18 15 14 16 11 11 10 9 11 8 12 11 4 10 13 7 9 10 8 2 9 8 2 5 9 5 3 9 3 5 4 6 1 1 0 2 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 1 average: 2 | standard deviation: 0 | 0 0 1 ] miss_latency_IFETCH_L2Cache: [binsize: 1 max: 108 count: 8 average: 18.75 | standard deviation: 36.0912 | 0 0 0 0 1 2 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_IFETCH_Directory: [binsize: 8 max: 999 count: 51 average: 483.941 | standard deviation: 174.07 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 5 1 1 0 0 1 0 1 0 0 0 0 0 1 3 4 3 0 2 1 0 0 1 0 0 0 2 1 1 2 0 1 1 0 1 0 0 0 0 1 2 1 3 0 0 0 0 1 0 0 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Request vs. RubySystem State Profile -------------------------------- filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 user_time: 0 system_time: 0 page_reclaims: 10373 page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 Network Stats ------------- total_msg_count_Request_Control: 2625 21000 total_msg_count_Response_Data: 2622 188784 total_msg_count_Writeback_Data: 2342 168624 total_msg_count_Writeback_Control: 5451 43608 total_msg_count_Unblock_Control: 2615 20920 total_msgs: 15655 total_bytes: 442936 switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 2.10979 links_utilized_percent_switch_0_link_0: 1.99487 bw: 16000 base_latency: 1 links_utilized_percent_switch_0_link_1: 2.2247 bw: 16000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Request_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Data: 782 56304 [ 0 0 0 0 0 782 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Unblock_Control: 873 6984 [ 0 0 0 0 0 873 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 links_utilized_percent_switch_1: 2.10727 links_utilized_percent_switch_1_link_0: 2.21967 bw: 16000 base_latency: 1 links_utilized_percent_switch_1_link_1: 1.99487 bw: 16000 base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 874 6992 [ 0 0 874 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 780 56160 [ 0 0 0 0 0 780 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Unblock_Control: 871 6968 [ 0 0 0 0 0 871 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 links_utilized_percent_switch_2: 2.10739 links_utilized_percent_switch_2_link_0: 1.99487 bw: 16000 base_latency: 1 links_utilized_percent_switch_2_link_1: 2.2199 bw: 16000 base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 874 62928 [ 0 0 0 0 874 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 866 6928 [ 0 0 0 866 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Request_Control: 875 7000 [ 0 0 875 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Writeback_Data: 780 56160 [ 0 0 0 0 0 780 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Writeback_Control: 951 7608 [ 0 0 867 0 0 84 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 871 6968 [ 0 0 0 0 0 871 0 0 0 0 ] base_latency: 1 Cache Stats: system.ruby.cpu_ruby_ports.icache system.ruby.cpu_ruby_ports.icache_total_misses: 59 system.ruby.cpu_ruby_ports.icache_total_demand_misses: 59 system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 59 100% Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_total_misses: 872 system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 872 system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 system.ruby.cpu_ruby_ports.dcache_request_type_LD: 4.58716% system.ruby.cpu_ruby_ports.dcache_request_type_ST: 95.4128% system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 872 100% Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_total_misses: 931 system.l1_cntrl0.L2cacheMemory_total_demand_misses: 931 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.29646% system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.3663% system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.33727% system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 931 100% --- L1Cache --- - Event Counts - Load [42 ] 42 Ifetch [61 ] 61 Store [922 ] 922 L2_Replacement [869 ] 869 L1_to_L2 [16473 ] 16473 Trigger_L2_to_L1D [47 ] 47 Trigger_L2_to_L1I [8 ] 8 Complete_L2_to_L1 [55 ] 55 Other_GETX [0 ] 0 Other_GETS [0 ] 0 Merged_GETS [0 ] 0 Other_GETS_No_Mig [0 ] 0 NC_DMA_GETS [0 ] 0 Invalidate [0 ] 0 Ack [0 ] 0 Shared_Ack [0 ] 0 Data [0 ] 0 Shared_Data [0 ] 0 Exclusive_Data [874 ] 874 Writeback_Ack [866 ] 866 Writeback_Nack [0 ] 0 All_acks [0 ] 0 All_acks_no_sharers [873 ] 873 Flush_line [0 ] 0 Block_Ack [0 ] 0 - Transitions - I Load [39 ] 39 I Ifetch [51 ] 51 I Store [786 ] 786 I L2_Replacement [0 ] 0 I L1_to_L2 [0 ] 0 I Trigger_L2_to_L1D [0 ] 0 I Trigger_L2_to_L1I [0 ] 0 I Other_GETX [0 ] 0 I Other_GETS [0 ] 0 I Other_GETS_No_Mig [0 ] 0 I NC_DMA_GETS [0 ] 0 I Invalidate [0 ] 0 I Flush_line [0 ] 0 S Load [0 ] 0 S Ifetch [0 ] 0 S Store [0 ] 0 S L2_Replacement [0 ] 0 S L1_to_L2 [0 ] 0 S Trigger_L2_to_L1D [0 ] 0 S Trigger_L2_to_L1I [0 ] 0 S Other_GETX [0 ] 0 S Other_GETS [0 ] 0 S Other_GETS_No_Mig [0 ] 0 S NC_DMA_GETS [0 ] 0 S Invalidate [0 ] 0 S Flush_line [0 ] 0 O Load [0 ] 0 O Ifetch [0 ] 0 O Store [0 ] 0 O L2_Replacement [0 ] 0 O L1_to_L2 [0 ] 0 O Trigger_L2_to_L1D [0 ] 0 O Trigger_L2_to_L1I [0 ] 0 O Other_GETX [0 ] 0 O Other_GETS [0 ] 0 O Merged_GETS [0 ] 0 O Other_GETS_No_Mig [0 ] 0 O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 O Flush_line [0 ] 0 M Load [0 ] 0 M Ifetch [0 ] 0 M Store [2 ] 2 M L2_Replacement [85 ] 85 M L1_to_L2 [93 ] 93 M Trigger_L2_to_L1D [8 ] 8 M Trigger_L2_to_L1I [0 ] 0 M Other_GETX [0 ] 0 M Other_GETS [0 ] 0 M Merged_GETS [0 ] 0 M Other_GETS_No_Mig [0 ] 0 M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 M Flush_line [0 ] 0 MM Load [2 ] 2 MM Ifetch [9 ] 9 MM Store [102 ] 102 MM L2_Replacement [784 ] 784 MM L1_to_L2 [833 ] 833 MM Trigger_L2_to_L1D [39 ] 39 MM Trigger_L2_to_L1I [8 ] 8 MM Other_GETX [0 ] 0 MM Other_GETS [0 ] 0 MM Merged_GETS [0 ] 0 MM Other_GETS_No_Mig [0 ] 0 MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 MM Flush_line [0 ] 0 IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 IM L2_Replacement [0 ] 0 IM L1_to_L2 [10256 ] 10256 IM Other_GETX [0 ] 0 IM Other_GETS [0 ] 0 IM Other_GETS_No_Mig [0 ] 0 IM NC_DMA_GETS [0 ] 0 IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 IM Exclusive_Data [785 ] 785 IM Flush_line [0 ] 0 SM Load [0 ] 0 SM Ifetch [0 ] 0 SM Store [0 ] 0 SM L2_Replacement [0 ] 0 SM L1_to_L2 [0 ] 0 SM Other_GETX [0 ] 0 SM Other_GETS [0 ] 0 SM Other_GETS_No_Mig [0 ] 0 SM NC_DMA_GETS [0 ] 0 SM Invalidate [0 ] 0 SM Ack [0 ] 0 SM Data [0 ] 0 SM Exclusive_Data [0 ] 0 SM Flush_line [0 ] 0 OM Load [0 ] 0 OM Ifetch [0 ] 0 OM Store [0 ] 0 OM L2_Replacement [0 ] 0 OM L1_to_L2 [0 ] 0 OM Other_GETX [0 ] 0 OM Other_GETS [0 ] 0 OM Merged_GETS [0 ] 0 OM Other_GETS_No_Mig [0 ] 0 OM NC_DMA_GETS [0 ] 0 OM Invalidate [0 ] 0 OM Ack [0 ] 0 OM All_acks [0 ] 0 OM All_acks_no_sharers [0 ] 0 OM Flush_line [0 ] 0 ISM Load [0 ] 0 ISM Ifetch [0 ] 0 ISM Store [0 ] 0 ISM L2_Replacement [0 ] 0 ISM L1_to_L2 [0 ] 0 ISM Ack [0 ] 0 ISM All_acks_no_sharers [0 ] 0 ISM Flush_line [0 ] 0 M_W Load [0 ] 0 M_W Ifetch [0 ] 0 M_W Store [0 ] 0 M_W L2_Replacement [0 ] 0 M_W L1_to_L2 [292 ] 292 M_W Ack [0 ] 0 M_W All_acks_no_sharers [88 ] 88 M_W Flush_line [0 ] 0 MM_W Load [0 ] 0 MM_W Ifetch [0 ] 0 MM_W Store [1 ] 1 MM_W L2_Replacement [0 ] 0 MM_W L1_to_L2 [4281 ] 4281 MM_W Ack [0 ] 0 MM_W All_acks_no_sharers [785 ] 785 MM_W Flush_line [0 ] 0 IS Load [0 ] 0 IS Ifetch [0 ] 0 IS Store [0 ] 0 IS L2_Replacement [0 ] 0 IS L1_to_L2 [576 ] 576 IS Other_GETX [0 ] 0 IS Other_GETS [0 ] 0 IS Other_GETS_No_Mig [0 ] 0 IS NC_DMA_GETS [0 ] 0 IS Invalidate [0 ] 0 IS Ack [0 ] 0 IS Shared_Ack [0 ] 0 IS Data [0 ] 0 IS Shared_Data [0 ] 0 IS Exclusive_Data [89 ] 89 IS Flush_line [0 ] 0 SS Load [0 ] 0 SS Ifetch [0 ] 0 SS Store [0 ] 0 SS L2_Replacement [0 ] 0 SS L1_to_L2 [0 ] 0 SS Ack [0 ] 0 SS Shared_Ack [0 ] 0 SS All_acks [0 ] 0 SS All_acks_no_sharers [0 ] 0 SS Flush_line [0 ] 0 OI Load [0 ] 0 OI Ifetch [0 ] 0 OI Store [0 ] 0 OI L2_Replacement [0 ] 0 OI L1_to_L2 [0 ] 0 OI Other_GETX [0 ] 0 OI Other_GETS [0 ] 0 OI Merged_GETS [0 ] 0 OI Other_GETS_No_Mig [0 ] 0 OI NC_DMA_GETS [0 ] 0 OI Invalidate [0 ] 0 OI Writeback_Ack [0 ] 0 OI Flush_line [0 ] 0 MI Load [0 ] 0 MI Ifetch [0 ] 0 MI Store [2 ] 2 MI L2_Replacement [0 ] 0 MI L1_to_L2 [0 ] 0 MI Other_GETX [0 ] 0 MI Other_GETS [0 ] 0 MI Merged_GETS [0 ] 0 MI Other_GETS_No_Mig [0 ] 0 MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 MI Writeback_Ack [866 ] 866 MI Flush_line [0 ] 0 II Load [0 ] 0 II Ifetch [0 ] 0 II Store [0 ] 0 II L2_Replacement [0 ] 0 II L1_to_L2 [0 ] 0 II Other_GETX [0 ] 0 II Other_GETS [0 ] 0 II Other_GETS_No_Mig [0 ] 0 II NC_DMA_GETS [0 ] 0 II Invalidate [0 ] 0 II Writeback_Ack [0 ] 0 II Writeback_Nack [0 ] 0 II Flush_line [0 ] 0 IT Load [0 ] 0 IT Ifetch [0 ] 0 IT Store [0 ] 0 IT L2_Replacement [0 ] 0 IT L1_to_L2 [0 ] 0 IT Complete_L2_to_L1 [0 ] 0 IT Other_GETX [0 ] 0 IT Other_GETS [0 ] 0 IT Merged_GETS [0 ] 0 IT Other_GETS_No_Mig [0 ] 0 IT NC_DMA_GETS [0 ] 0 IT Invalidate [0 ] 0 IT Flush_line [0 ] 0 ST Load [0 ] 0 ST Ifetch [0 ] 0 ST Store [0 ] 0 ST L2_Replacement [0 ] 0 ST L1_to_L2 [0 ] 0 ST Complete_L2_to_L1 [0 ] 0 ST Other_GETX [0 ] 0 ST Other_GETS [0 ] 0 ST Merged_GETS [0 ] 0 ST Other_GETS_No_Mig [0 ] 0 ST NC_DMA_GETS [0 ] 0 ST Invalidate [0 ] 0 ST Flush_line [0 ] 0 OT Load [0 ] 0 OT Ifetch [0 ] 0 OT Store [0 ] 0 OT L2_Replacement [0 ] 0 OT L1_to_L2 [0 ] 0 OT Complete_L2_to_L1 [0 ] 0 OT Other_GETX [0 ] 0 OT Other_GETS [0 ] 0 OT Merged_GETS [0 ] 0 OT Other_GETS_No_Mig [0 ] 0 OT NC_DMA_GETS [0 ] 0 OT Invalidate [0 ] 0 OT Flush_line [0 ] 0 MT Load [1 ] 1 MT Ifetch [0 ] 0 MT Store [1 ] 1 MT L2_Replacement [0 ] 0 MT L1_to_L2 [25 ] 25 MT Complete_L2_to_L1 [8 ] 8 MT Other_GETX [0 ] 0 MT Other_GETS [0 ] 0 MT Merged_GETS [0 ] 0 MT Other_GETS_No_Mig [0 ] 0 MT NC_DMA_GETS [0 ] 0 MT Invalidate [0 ] 0 MT Flush_line [0 ] 0 MMT Load [0 ] 0 MMT Ifetch [1 ] 1 MMT Store [28 ] 28 MMT L2_Replacement [0 ] 0 MMT L1_to_L2 [117 ] 117 MMT Complete_L2_to_L1 [47 ] 47 MMT Other_GETX [0 ] 0 MMT Other_GETS [0 ] 0 MMT Merged_GETS [0 ] 0 MMT Other_GETS_No_Mig [0 ] 0 MMT NC_DMA_GETS [0 ] 0 MMT Invalidate [0 ] 0 MMT Flush_line [0 ] 0 MI_F Load [0 ] 0 MI_F Ifetch [0 ] 0 MI_F Store [0 ] 0 MI_F L1_to_L2 [0 ] 0 MI_F Writeback_Ack [0 ] 0 MI_F Flush_line [0 ] 0 MM_F Load [0 ] 0 MM_F Ifetch [0 ] 0 MM_F Store [0 ] 0 MM_F L1_to_L2 [0 ] 0 MM_F Other_GETX [0 ] 0 MM_F Other_GETS [0 ] 0 MM_F Merged_GETS [0 ] 0 MM_F Other_GETS_No_Mig [0 ] 0 MM_F NC_DMA_GETS [0 ] 0 MM_F Invalidate [0 ] 0 MM_F Ack [0 ] 0 MM_F All_acks [0 ] 0 MM_F All_acks_no_sharers [0 ] 0 MM_F Flush_line [0 ] 0 MM_F Block_Ack [0 ] 0 IM_F Load [0 ] 0 IM_F Ifetch [0 ] 0 IM_F Store [0 ] 0 IM_F L2_Replacement [0 ] 0 IM_F L1_to_L2 [0 ] 0 IM_F Other_GETX [0 ] 0 IM_F Other_GETS [0 ] 0 IM_F Other_GETS_No_Mig [0 ] 0 IM_F NC_DMA_GETS [0 ] 0 IM_F Invalidate [0 ] 0 IM_F Ack [0 ] 0 IM_F Data [0 ] 0 IM_F Exclusive_Data [0 ] 0 IM_F Flush_line [0 ] 0 ISM_F Load [0 ] 0 ISM_F Ifetch [0 ] 0 ISM_F Store [0 ] 0 ISM_F L2_Replacement [0 ] 0 ISM_F L1_to_L2 [0 ] 0 ISM_F Ack [0 ] 0 ISM_F All_acks_no_sharers [0 ] 0 ISM_F Flush_line [0 ] 0 SM_F Load [0 ] 0 SM_F Ifetch [0 ] 0 SM_F Store [0 ] 0 SM_F L2_Replacement [0 ] 0 SM_F L1_to_L2 [0 ] 0 SM_F Other_GETX [0 ] 0 SM_F Other_GETS [0 ] 0 SM_F Other_GETS_No_Mig [0 ] 0 SM_F NC_DMA_GETS [0 ] 0 SM_F Invalidate [0 ] 0 SM_F Ack [0 ] 0 SM_F Data [0 ] 0 SM_F Exclusive_Data [0 ] 0 SM_F Flush_line [0 ] 0 OM_F Load [0 ] 0 OM_F Ifetch [0 ] 0 OM_F Store [0 ] 0 OM_F L2_Replacement [0 ] 0 OM_F L1_to_L2 [0 ] 0 OM_F Other_GETX [0 ] 0 OM_F Other_GETS [0 ] 0 OM_F Merged_GETS [0 ] 0 OM_F Other_GETS_No_Mig [0 ] 0 OM_F NC_DMA_GETS [0 ] 0 OM_F Invalidate [0 ] 0 OM_F Ack [0 ] 0 OM_F All_acks [0 ] 0 OM_F All_acks_no_sharers [0 ] 0 OM_F Flush_line [0 ] 0 MM_WF Load [0 ] 0 MM_WF Ifetch [0 ] 0 MM_WF Store [0 ] 0 MM_WF L2_Replacement [0 ] 0 MM_WF L1_to_L2 [0 ] 0 MM_WF Ack [0 ] 0 MM_WF All_acks_no_sharers [0 ] 0 MM_WF Flush_line [0 ] 0 Cache Stats: system.dir_cntrl0.probeFilter system.dir_cntrl0.probeFilter_total_misses: 0 system.dir_cntrl0.probeFilter_total_demand_misses: 0 system.dir_cntrl0.probeFilter_total_prefetches: 0 system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1654 memory_reads: 874 memory_writes: 780 memory_refreshes: 456 memory_total_request_delays: 1201 memory_delays_per_request: 0.726119 memory_delays_in_input_queue: 157 memory_delays_behind_head_of_bank_queue: 3 memory_delays_stalled_at_head_of_bank_queue: 1041 memory_stalls_for_bank_busy: 197 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 memory_stalls_for_arbitration: 94 memory_stalls_for_bus: 428 memory_stalls_for_tfaw: 0 memory_stalls_for_read_write_turnaround: 194 memory_stalls_for_read_read_turnaround: 128 accesses_per_bank: 53 40 52 100 61 73 71 45 32 60 50 44 54 57 43 49 54 47 51 56 44 55 51 40 46 56 45 41 40 49 48 47 --- Directory --- - Event Counts - GETX [785 ] 785 GETS [89 ] 89 PUT [923 ] 923 Unblock [0 ] 0 UnblockS [0 ] 0 UnblockM [871 ] 871 Writeback_Clean [0 ] 0 Writeback_Dirty [0 ] 0 Writeback_Exclusive_Clean [84 ] 84 Writeback_Exclusive_Dirty [780 ] 780 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 Memory_Data [874 ] 874 Memory_Ack [780 ] 780 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 Data [0 ] 0 Exclusive_Data [0 ] 0 All_acks_and_shared_data [0 ] 0 All_acks_and_owner_data [0 ] 0 All_acks_and_data_no_sharers [0 ] 0 All_Unblocks [0 ] 0 GETF [0 ] 0 PUTF [0 ] 0 - Transitions - NX GETX [0 ] 0 NX GETS [0 ] 0 NX PUT [0 ] 0 NX Pf_Replacement [0 ] 0 NX DMA_READ [0 ] 0 NX DMA_WRITE [0 ] 0 NX GETF [0 ] 0 NO GETX [0 ] 0 NO GETS [0 ] 0 NO PUT [867 ] 867 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 NO GETF [0 ] 0 S GETX [0 ] 0 S GETS [0 ] 0 S PUT [0 ] 0 S Pf_Replacement [0 ] 0 S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 S GETF [0 ] 0 O GETX [0 ] 0 O GETS [0 ] 0 O PUT [0 ] 0 O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O GETF [0 ] 0 E GETX [785 ] 785 E GETS [89 ] 89 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 E GETF [0 ] 0 O_R GETX [0 ] 0 O_R GETS [0 ] 0 O_R PUT [0 ] 0 O_R Pf_Replacement [0 ] 0 O_R DMA_READ [0 ] 0 O_R DMA_WRITE [0 ] 0 O_R Ack [0 ] 0 O_R All_acks_and_data_no_sharers [0 ] 0 O_R GETF [0 ] 0 S_R GETX [0 ] 0 S_R GETS [0 ] 0 S_R PUT [0 ] 0 S_R Pf_Replacement [0 ] 0 S_R DMA_READ [0 ] 0 S_R DMA_WRITE [0 ] 0 S_R Ack [0 ] 0 S_R Data [0 ] 0 S_R All_acks_and_data_no_sharers [0 ] 0 S_R GETF [0 ] 0 NO_R GETX [0 ] 0 NO_R GETS [0 ] 0 NO_R PUT [0 ] 0 NO_R Pf_Replacement [0 ] 0 NO_R DMA_READ [0 ] 0 NO_R DMA_WRITE [0 ] 0 NO_R Ack [0 ] 0 NO_R Data [0 ] 0 NO_R Exclusive_Data [0 ] 0 NO_R All_acks_and_data_no_sharers [0 ] 0 NO_R GETF [0 ] 0 NO_B GETX [0 ] 0 NO_B GETS [0 ] 0 NO_B PUT [56 ] 56 NO_B UnblockS [0 ] 0 NO_B UnblockM [871 ] 871 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 NO_B GETF [0 ] 0 NO_B_X GETX [0 ] 0 NO_B_X GETS [0 ] 0 NO_B_X PUT [0 ] 0 NO_B_X UnblockS [0 ] 0 NO_B_X UnblockM [0 ] 0 NO_B_X Pf_Replacement [0 ] 0 NO_B_X DMA_READ [0 ] 0 NO_B_X DMA_WRITE [0 ] 0 NO_B_X GETF [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 NO_B_S PUT [0 ] 0 NO_B_S UnblockS [0 ] 0 NO_B_S UnblockM [0 ] 0 NO_B_S Pf_Replacement [0 ] 0 NO_B_S DMA_READ [0 ] 0 NO_B_S DMA_WRITE [0 ] 0 NO_B_S GETF [0 ] 0 NO_B_S_W GETX [0 ] 0 NO_B_S_W GETS [0 ] 0 NO_B_S_W PUT [0 ] 0 NO_B_S_W UnblockS [0 ] 0 NO_B_S_W Pf_Replacement [0 ] 0 NO_B_S_W DMA_READ [0 ] 0 NO_B_S_W DMA_WRITE [0 ] 0 NO_B_S_W All_Unblocks [0 ] 0 NO_B_S_W GETF [0 ] 0 O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 O_B UnblockS [0 ] 0 O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 O_B GETF [0 ] 0 NO_B_W GETX [0 ] 0 NO_B_W GETS [0 ] 0 NO_B_W PUT [0 ] 0 NO_B_W UnblockS [0 ] 0 NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 NO_B_W Memory_Data [874 ] 874 NO_B_W GETF [0 ] 0 O_B_W GETX [0 ] 0 O_B_W GETS [0 ] 0 O_B_W PUT [0 ] 0 O_B_W UnblockS [0 ] 0 O_B_W Pf_Replacement [0 ] 0 O_B_W DMA_READ [0 ] 0 O_B_W DMA_WRITE [0 ] 0 O_B_W Memory_Data [0 ] 0 O_B_W GETF [0 ] 0 NO_W GETX [0 ] 0 NO_W GETS [0 ] 0 NO_W PUT [0 ] 0 NO_W Pf_Replacement [0 ] 0 NO_W DMA_READ [0 ] 0 NO_W DMA_WRITE [0 ] 0 NO_W Memory_Data [0 ] 0 NO_W GETF [0 ] 0 O_W GETX [0 ] 0 O_W GETS [0 ] 0 O_W PUT [0 ] 0 O_W Pf_Replacement [0 ] 0 O_W DMA_READ [0 ] 0 O_W DMA_WRITE [0 ] 0 O_W Memory_Data [0 ] 0 O_W GETF [0 ] 0 NO_DW_B_W GETX [0 ] 0 NO_DW_B_W GETS [0 ] 0 NO_DW_B_W PUT [0 ] 0 NO_DW_B_W Pf_Replacement [0 ] 0 NO_DW_B_W DMA_READ [0 ] 0 NO_DW_B_W DMA_WRITE [0 ] 0 NO_DW_B_W Ack [0 ] 0 NO_DW_B_W Data [0 ] 0 NO_DW_B_W Exclusive_Data [0 ] 0 NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 NO_DW_B_W GETF [0 ] 0 NO_DR_B_W GETX [0 ] 0 NO_DR_B_W GETS [0 ] 0 NO_DR_B_W PUT [0 ] 0 NO_DR_B_W Pf_Replacement [0 ] 0 NO_DR_B_W DMA_READ [0 ] 0 NO_DR_B_W DMA_WRITE [0 ] 0 NO_DR_B_W Memory_Data [0 ] 0 NO_DR_B_W Ack [0 ] 0 NO_DR_B_W Shared_Ack [0 ] 0 NO_DR_B_W Shared_Data [0 ] 0 NO_DR_B_W Data [0 ] 0 NO_DR_B_W Exclusive_Data [0 ] 0 NO_DR_B_W GETF [0 ] 0 NO_DR_B_D GETX [0 ] 0 NO_DR_B_D GETS [0 ] 0 NO_DR_B_D PUT [0 ] 0 NO_DR_B_D Pf_Replacement [0 ] 0 NO_DR_B_D DMA_READ [0 ] 0 NO_DR_B_D DMA_WRITE [0 ] 0 NO_DR_B_D Ack [0 ] 0 NO_DR_B_D Shared_Ack [0 ] 0 NO_DR_B_D Shared_Data [0 ] 0 NO_DR_B_D Data [0 ] 0 NO_DR_B_D Exclusive_Data [0 ] 0 NO_DR_B_D All_acks_and_shared_data [0 ] 0 NO_DR_B_D All_acks_and_owner_data [0 ] 0 NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 NO_DR_B_D GETF [0 ] 0 NO_DR_B GETX [0 ] 0 NO_DR_B GETS [0 ] 0 NO_DR_B PUT [0 ] 0 NO_DR_B Pf_Replacement [0 ] 0 NO_DR_B DMA_READ [0 ] 0 NO_DR_B DMA_WRITE [0 ] 0 NO_DR_B Ack [0 ] 0 NO_DR_B Shared_Ack [0 ] 0 NO_DR_B Shared_Data [0 ] 0 NO_DR_B Data [0 ] 0 NO_DR_B Exclusive_Data [0 ] 0 NO_DR_B All_acks_and_shared_data [0 ] 0 NO_DR_B All_acks_and_owner_data [0 ] 0 NO_DR_B All_acks_and_data_no_sharers [0 ] 0 NO_DR_B GETF [0 ] 0 NO_DW_W GETX [0 ] 0 NO_DW_W GETS [0 ] 0 NO_DW_W PUT [0 ] 0 NO_DW_W Pf_Replacement [0 ] 0 NO_DW_W DMA_READ [0 ] 0 NO_DW_W DMA_WRITE [0 ] 0 NO_DW_W Memory_Ack [0 ] 0 NO_DW_W GETF [0 ] 0 O_DR_B_W GETX [0 ] 0 O_DR_B_W GETS [0 ] 0 O_DR_B_W PUT [0 ] 0 O_DR_B_W Pf_Replacement [0 ] 0 O_DR_B_W DMA_READ [0 ] 0 O_DR_B_W DMA_WRITE [0 ] 0 O_DR_B_W Memory_Data [0 ] 0 O_DR_B_W Ack [0 ] 0 O_DR_B_W Shared_Ack [0 ] 0 O_DR_B_W GETF [0 ] 0 O_DR_B GETX [0 ] 0 O_DR_B GETS [0 ] 0 O_DR_B PUT [0 ] 0 O_DR_B Pf_Replacement [0 ] 0 O_DR_B DMA_READ [0 ] 0 O_DR_B DMA_WRITE [0 ] 0 O_DR_B Ack [0 ] 0 O_DR_B Shared_Ack [0 ] 0 O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 O_DR_B GETF [0 ] 0 WB GETX [0 ] 0 WB GETS [0 ] 0 WB PUT [0 ] 0 WB Unblock [0 ] 0 WB Writeback_Clean [0 ] 0 WB Writeback_Dirty [0 ] 0 WB Writeback_Exclusive_Clean [84 ] 84 WB Writeback_Exclusive_Dirty [780 ] 780 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 WB GETF [0 ] 0 WB_O_W GETX [0 ] 0 WB_O_W GETS [0 ] 0 WB_O_W PUT [0 ] 0 WB_O_W Pf_Replacement [0 ] 0 WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 WB_O_W Memory_Ack [0 ] 0 WB_O_W GETF [0 ] 0 WB_E_W GETX [0 ] 0 WB_E_W GETS [0 ] 0 WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 WB_E_W Memory_Ack [780 ] 780 WB_E_W GETF [0 ] 0 NO_F GETX [0 ] 0 NO_F GETS [0 ] 0 NO_F PUT [0 ] 0 NO_F UnblockM [0 ] 0 NO_F Pf_Replacement [0 ] 0 NO_F GETF [0 ] 0 NO_F PUTF [0 ] 0 NO_F_W GETX [0 ] 0 NO_F_W GETS [0 ] 0 NO_F_W PUT [0 ] 0 NO_F_W Pf_Replacement [0 ] 0 NO_F_W DMA_READ [0 ] 0 NO_F_W DMA_WRITE [0 ] 0 NO_F_W Memory_Data [0 ] 0 NO_F_W GETF