---------- Begin Simulation Statistics ---------- sim_seconds 5.184750 # Number of seconds simulated sim_ticks 5184749789500 # Number of ticks simulated final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 858252 # Simulator instruction rate (inst/s) host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s) host_tick_rate 34581252938 # Simulator tick rate (ticks/s) host_mem_usage 653812 # Number of bytes of host memory used host_seconds 149.93 # Real time elapsed on the host sim_insts 128677191 # Number of instructions simulated sim_ops 248045844 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 9871616 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 827904 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 827904 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8126080 # Number of bytes written to this memory system.physmem.bytes_written::total 8126080 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 12936 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140860 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 154244 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 126970 # Number of write requests responded to by this memory system.physmem.num_writes::total 126970 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 159681 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1738761 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1903972 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 159681 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 159681 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1567304 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1567304 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1567304 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 159681 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1738761 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3471276 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 154244 # Number of read requests accepted system.physmem.writeReqs 173690 # Number of write requests accepted system.physmem.readBursts 154244 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9927 # Per bank write bursts system.physmem.perBankRdBursts::1 9220 # Per bank write bursts system.physmem.perBankRdBursts::2 9906 # Per bank write bursts system.physmem.perBankRdBursts::3 9744 # Per bank write bursts system.physmem.perBankRdBursts::4 9716 # Per bank write bursts system.physmem.perBankRdBursts::5 9338 # Per bank write bursts system.physmem.perBankRdBursts::6 9475 # Per bank write bursts system.physmem.perBankRdBursts::7 9515 # Per bank write bursts system.physmem.perBankRdBursts::8 8926 # Per bank write bursts system.physmem.perBankRdBursts::9 9405 # Per bank write bursts system.physmem.perBankRdBursts::10 9702 # Per bank write bursts system.physmem.perBankRdBursts::11 9402 # Per bank write bursts system.physmem.perBankRdBursts::12 9788 # Per bank write bursts system.physmem.perBankRdBursts::13 10193 # Per bank write bursts system.physmem.perBankRdBursts::14 9798 # Per bank write bursts system.physmem.perBankRdBursts::15 10094 # Per bank write bursts system.physmem.perBankWrBursts::0 9407 # Per bank write bursts system.physmem.perBankWrBursts::1 8748 # Per bank write bursts system.physmem.perBankWrBursts::2 9677 # Per bank write bursts system.physmem.perBankWrBursts::3 9718 # Per bank write bursts system.physmem.perBankWrBursts::4 9428 # Per bank write bursts system.physmem.perBankWrBursts::5 9072 # Per bank write bursts system.physmem.perBankWrBursts::6 8868 # Per bank write bursts system.physmem.perBankWrBursts::7 9192 # Per bank write bursts system.physmem.perBankWrBursts::8 8615 # Per bank write bursts system.physmem.perBankWrBursts::9 8711 # Per bank write bursts system.physmem.perBankWrBursts::10 9601 # Per bank write bursts system.physmem.perBankWrBursts::11 9113 # Per bank write bursts system.physmem.perBankWrBursts::12 9702 # Per bank write bursts system.physmem.perBankWrBursts::13 9421 # Per bank write bursts system.physmem.perBankWrBursts::14 9363 # Per bank write bursts system.physmem.perBankWrBursts::15 8959 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 68 # Number of times write queue was full causing retry system.physmem.totGap 5184749726000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 154244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 173690 # Write request sizes (log2) system.physmem.rdQLenPdf::0 150873 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2864 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1720 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2028 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 5197 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5607 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5381 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5544 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5616 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6039 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7751 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 6327 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 6715 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 8321 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 6359 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 6074 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 9044 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6942 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 1383 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1065 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1664 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 3046 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 3049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2409 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 2529 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 3647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2755 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 2403 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 2146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 2360 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 2108 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1639 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 1559 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 1250 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 853 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 400 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 368 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 460 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 213 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 57050 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 338.502226 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 199.067588 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 346.604467 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 19329 33.88% 33.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 13844 24.27% 58.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 5928 10.39% 68.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3298 5.78% 74.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2346 4.11% 78.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1576 2.76% 81.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1245 2.18% 83.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 971 1.70% 85.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8513 14.92% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 57050 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 29.117303 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 658.027323 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 5293 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 27.879675 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 19.284410 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 52.982511 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-31 4909 92.73% 92.73% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-47 99 1.87% 94.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-63 16 0.30% 94.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-79 5 0.09% 94.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-95 10 0.19% 95.18% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-111 12 0.23% 95.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-127 21 0.40% 95.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-143 16 0.30% 96.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-159 28 0.53% 96.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-175 6 0.11% 96.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-191 43 0.81% 97.56% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-207 33 0.62% 98.19% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-223 9 0.17% 98.36% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-239 4 0.08% 98.43% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-255 1 0.02% 98.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-271 3 0.06% 98.51% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::272-287 2 0.04% 98.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::288-303 9 0.17% 98.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::304-319 7 0.13% 98.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::320-335 3 0.06% 98.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::336-351 17 0.32% 99.23% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::352-367 15 0.28% 99.51% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::368-383 2 0.04% 99.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::384-399 3 0.06% 99.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::400-415 2 0.04% 99.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::416-431 1 0.02% 99.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads system.physmem.totQLat 1425327951 # Total ticks spent queuing system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 22.98 # Average write queue length when enqueuing system.physmem.readRowHits 126892 # Number of row buffer hits during reads system.physmem.writeRowHits 117801 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes system.physmem.avgGap 15810345.15 # Average gap between requests system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ) system.physmem_0.averagePower 668.758961 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 3467467313340 # Total energy per rank (pJ) system.physmem_1.averagePower 668.782314 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 4978313509331 # Time in different power states system.physmem_1.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 33303731919 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10369499579 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 128677191 # Number of instructions committed system.cpu.committedOps 248045844 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 232619140 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 2317433 # number of times a function call or return occured system.cpu.num_conditional_control_insts 23196735 # number of instructions that are conditional controls system.cpu.num_int_insts 232619140 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 435790308 # number of times the integer registers were read system.cpu.num_int_register_writes 198379629 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_cc_register_reads 133146964 # number of times the CC registers were read system.cpu.num_cc_register_writes 95675934 # number of times the CC registers were written system.cpu.num_mem_refs 22361713 # number of memory refs system.cpu.num_load_insts 13951833 # Number of load instructions system.cpu.num_store_insts 8409880 # Number of store instructions system.cpu.num_idle_cycles 9769324889.998116 # Number of idle cycles system.cpu.num_busy_cycles 600174689.001884 # Number of busy cycles system.cpu.not_idle_fraction 0.057879 # Percentage of non-idle cycles system.cpu.idle_fraction 0.942121 # Percentage of idle cycles system.cpu.Branches 26373024 # Number of branches fetched system.cpu.op_class::No_OpClass 172503 0.07% 0.07% # Class of executed instruction system.cpu.op_class::IntAlu 225254349 90.81% 90.88% # Class of executed instruction system.cpu.op_class::IntMult 140413 0.06% 90.94% # Class of executed instruction system.cpu.op_class::IntDiv 123366 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::MemRead 13946864 5.62% 96.61% # Class of executed instruction system.cpu.op_class::MemWrite 8409880 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 248047391 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 1622522 # number of replacements system.cpu.dcache.tags.tagsinuse 511.996992 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 20153045 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1623034 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.416896 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 54942250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.996992 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 88765477 # Number of tag accesses system.cpu.dcache.tags.data_accesses 88765477 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 12014873 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12014873 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8077139 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 8077139 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 58853 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 58853 # number of SoftPFReq hits system.cpu.dcache.demand_hits::cpu.data 20092012 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 20092012 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 20150865 # number of overall hits system.cpu.dcache.overall_hits::total 20150865 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 906821 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 906821 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 324755 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 324755 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses system.cpu.dcache.overall_misses::total 1634737 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 21785602 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21785602 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070178 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.070178 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038653 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.038653 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1539491 # number of writebacks system.cpu.dcache.writebacks::total 1539491 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9162 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 9162 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 9452 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 9452 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 9452 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 9452 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906531 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 906531 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315350 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315350 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id system.cpu.dtb_walker_cache.tags.tag_accesses 54641 # Number of tag accesses system.cpu.dtb_walker_cache.tags.data_accesses 54641 # Number of data accesses system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12184 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 12184 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12184 # number of demand (read+write) hits system.cpu.dtb_walker_cache.demand_hits::total 12184 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12184 # number of overall hits system.cpu.dtb_walker_cache.overall_hits::total 12184 # number of overall hits system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 10091 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 10091 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 10091 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 10091 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 10091 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 10091 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 104642000 # number of ReadReq miss cycles system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 104642000 # number of ReadReq miss cycles system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 104642000 # number of demand (read+write) miss cycles system.cpu.dtb_walker_cache.demand_miss_latency::total 104642000 # number of demand (read+write) miss cycles system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 104642000 # number of overall miss cycles system.cpu.dtb_walker_cache.overall_miss_latency::total 104642000 # number of overall miss cycles system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22275 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 22275 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22275 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 22275 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22275 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 22275 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.453019 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.453019 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.453019 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total 0.453019 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.453019 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total 0.453019 # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10369.834506 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10369.834506 # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10369.834506 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10369.834506 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.dtb_walker_cache.writebacks::writebacks 3116 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 3116 # number of writebacks system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 10091 # number of ReadReq MSHR misses system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 10091 # number of ReadReq MSHR misses system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 10091 # number of demand (read+write) MSHR misses system.cpu.dtb_walker_cache.demand_mshr_misses::total 10091 # number of demand (read+write) MSHR misses system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 10091 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_misses::total 10091 # number of overall MSHR misses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 89505500 # number of ReadReq MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 89505500 # number of ReadReq MSHR miss cycles system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 89505500 # number of demand (read+write) MSHR miss cycles system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 89505500 # number of demand (read+write) MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 89505500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 89505500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.453019 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.453019 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.453019 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average ReadReq mshr miss latency system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8869.834506 # average ReadReq mshr miss latency system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 794465 # number of replacements system.cpu.icache.tags.tagsinuse 510.329327 # Cycle average of tags in use system.cpu.icache.tags.total_refs 144962865 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 794977 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 182.348502 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 161575846250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.329327 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996737 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996737 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 146552833 # Number of tag accesses system.cpu.icache.tags.data_accesses 146552833 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 144962865 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 144962865 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 144962865 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 144962865 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits system.cpu.icache.overall_hits::total 144962865 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses system.cpu.icache.overall_misses::total 794984 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191330 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.191330 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id system.cpu.itb_walker_cache.tags.tag_accesses 29974 # Number of tag accesses system.cpu.itb_walker_cache.tags.data_accesses 29974 # Number of data accesses system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7029 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7029 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7031 # number of demand (read+write) hits system.cpu.itb_walker_cache.demand_hits::total 7031 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7031 # number of overall hits system.cpu.itb_walker_cache.overall_hits::total 7031 # number of overall hits system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 5304 # number of ReadReq misses system.cpu.itb_walker_cache.ReadReq_misses::total 5304 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 5304 # number of demand (read+write) misses system.cpu.itb_walker_cache.demand_misses::total 5304 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 5304 # number of overall misses system.cpu.itb_walker_cache.overall_misses::total 5304 # number of overall misses system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51550250 # number of ReadReq miss cycles system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51550250 # number of ReadReq miss cycles system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51550250 # number of demand (read+write) miss cycles system.cpu.itb_walker_cache.demand_miss_latency::total 51550250 # number of demand (read+write) miss cycles system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51550250 # number of overall miss cycles system.cpu.itb_walker_cache.overall_miss_latency::total 51550250 # number of overall miss cycles system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 12333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12335 # number of demand (read+write) accesses system.cpu.itb_walker_cache.demand_accesses::total 12335 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12335 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12335 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.430066 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.430066 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.429996 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total 0.429996 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.429996 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total 0.429996 # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9719.127074 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9719.127074 # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9719.127074 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9719.127074 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.itb_walker_cache.writebacks::writebacks 759 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 759 # number of writebacks system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 5304 # number of ReadReq MSHR misses system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 5304 # number of ReadReq MSHR misses system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 5304 # number of demand (read+write) MSHR misses system.cpu.itb_walker_cache.demand_mshr_misses::total 5304 # number of demand (read+write) MSHR misses system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 5304 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_misses::total 5304 # number of overall MSHR misses system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 43592750 # number of ReadReq MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 43592750 # number of ReadReq MSHR miss cycles system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 43592750 # number of demand (read+write) MSHR miss cycles system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 43592750 # number of demand (read+write) MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 43592750 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 43592750 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.430066 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.430066 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.429996 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.429996 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average ReadReq mshr miss latency system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8218.844268 # average ReadReq mshr miss latency system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 87146 # number of replacements system.cpu.l2cache.tags.tagsinuse 64741.188816 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3494549 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 151845 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 23.013922 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 50454.801369 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141667 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 3260.512095 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 11025.733685 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.769879 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049751 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.168239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.987872 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 64699 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2964 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5133 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56510 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987228 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 32250710 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 32250710 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7142 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3328 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 782034 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3328 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 782034 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1480489 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2272993 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7142 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3328 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 782034 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1480489 # number of overall hits system.cpu.l2cache.overall_hits::total 2272993 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 12937 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 141790 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 154732 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 12937 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses system.cpu.l2cache.overall_misses::total 154732 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1308871 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2114317 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1543366 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1543366 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1674 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 313408 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 313408 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7142 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3333 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 794971 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1622279 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2427725 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7142 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3333 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 794971 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1622279 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2427725 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016274 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.087402 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.063735 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001500 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks system.cpu.l2cache.writebacks::total 80303 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 12937 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 141790 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 154732 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88554571000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88554571000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.063735 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 54167 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 228399 # Transaction distribution system.iobus.trans_dist::ReadResp 228399 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 11006 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution system.iobus.trans_dist::MessageReq 1652 # Transaction distribution system.iobus.trans_dist::MessageResp 1652 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 432904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 477136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95114 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 575554 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 216452 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 244848 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 3278696 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 3940536 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 216453000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 257203754 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 466130000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50194752 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47502 # number of replacements system.iocache.tags.tagsinuse 0.095966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47518 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 5046161981000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095966 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005998 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.005998 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 428013 # Number of tag accesses system.iocache.tags.data_accesses 428013 # Number of data accesses system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses system.iocache.ReadReq_misses::total 837 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses system.iocache.demand_misses::pc.south_bridge.ide 837 # number of demand (read+write) misses system.iocache.demand_misses::total 837 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 837 # number of overall misses system.iocache.overall_misses::total 837 # number of overall misses system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132288440 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 132288440 # number of ReadReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8590965562 # number of WriteInvalidateReq miss cycles system.iocache.WriteInvalidateReq_miss_latency::total 8590965562 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::pc.south_bridge.ide 132288440 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 132288440 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::pc.south_bridge.ide 132288440 # number of overall miss cycles system.iocache.overall_miss_latency::total 132288440 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::pc.south_bridge.ide 837 # number of demand (read+write) accesses system.iocache.demand_accesses::total 837 # number of demand (read+write) accesses system.iocache.overall_accesses::pc.south_bridge.ide 837 # number of overall (read+write) accesses system.iocache.overall_accesses::total 837 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 158050.704898 # average ReadReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365 # average WriteInvalidateReq miss latency system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency system.iocache.demand_avg_miss_latency::total 158050.704898 # average overall miss latency system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency system.iocache.overall_avg_miss_latency::total 158050.704898 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 4442 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 6.674246 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::pc.south_bridge.ide 837 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 837 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 837 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 88419930 # number of ReadReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6161511576 # number of WriteInvalidateReq MSHR miss cycles system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6161511576 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 88419930 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 88419930 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007 # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 617109 # Transaction distribution system.membus.trans_dist::ReadResp 617109 # Transaction distribution system.membus.trans_dist::WriteReq 13916 # Transaction distribution system.membus.trans_dist::WriteResp 13916 # Transaction distribution system.membus.trans_dist::Writeback 126970 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution system.membus.trans_dist::ReadExReq 112993 # Transaction distribution system.membus.trans_dist::ReadExResp 112993 # Transaction distribution system.membus.trans_dist::MessageReq 1652 # Transaction distribution system.membus.trans_dist::MessageResp 1652 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 1583 # Total snoops (count) system.membus.snoop_fanout::samples 331203 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 331203 # Request fanout histogram system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. ---------- End Simulation Statistics ----------