---------- Begin Simulation Statistics ---------- sim_seconds 0.000042 # Number of seconds simulated sim_ticks 41659 # Number of ticks simulated final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks host_inst_rate 33721 # Simulator instruction rate (inst/s) host_op_rate 33714 # Simulator op (including micro ops) rate (op/s) host_tick_rate 544888 # Simulator tick rate (ticks/s) host_mem_usage 445796 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 39808 # Number of bytes written to this memory system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory system.mem_ctrls.bw_read::ruby.dir_cntrl0 961712955 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::total 961712955 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::ruby.dir_cntrl0 955567824 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::total 955567824 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917280780 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::total 1917280780 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 626 # Number of read requests accepted system.mem_ctrls.writeReqs 622 # Number of write requests accepted system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrls.bytesReadDRAM 24960 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 15104 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 24000 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 236 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 219 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 23 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 58 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 62 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 15 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 32 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 31 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 22 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 54 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 57 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 21 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 15 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 31 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 63 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrls.totGap 41626 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::6 626 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 390 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 18 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 27 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 27 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 24 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 24 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 24 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 24 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 24 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 105 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 455.923810 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::gmean 317.170384 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::stdev 344.729986 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 11 10.48% 10.48% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 29 27.62% 38.10% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 10 9.52% 47.62% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 10 9.52% 57.14% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 14 13.33% 70.48% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 5 4.76% 75.24% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 4 3.81% 79.05% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 5 4.76% 83.81% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 17 16.19% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 105 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 16.434783 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 16.058223 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::stdev 4.388270 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::12-13 3 13.04% 13.04% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::14-15 10 43.48% 56.52% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-17 5 21.74% 78.26% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::18-19 4 17.39% 95.65% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 4.35% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 23 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16.304348 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.283756 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::stdev 0.875670 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 20 86.96% 86.96% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::17 1 4.35% 91.30% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::19 2 8.70% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 23 # Writes before turning the bus around for reads system.mem_ctrls.totQLat 4371 # Total ticks spent queuing system.mem_ctrls.totMemAccLat 11781 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 1950 # Total ticks spent in databus transfers system.mem_ctrls.avgQLat 11.21 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 30.21 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 599.15 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 576.11 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 961.71 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 955.57 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 9.18 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 4.68 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 4.50 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 24.82 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 298 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 355 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 76.41 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes system.mem_ctrls.avgGap 33.35 # Average gap between requests system.mem_ctrls.pageHitRate 82.35 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 234360 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 130200 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 1555200 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) system.mem_ctrls_0.actBackEnergy 26028252 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 682200 # Energy for precharge background per rank (pJ) system.mem_ctrls_0.totalEnergy 33144852 # Total energy per rank (pJ) system.mem_ctrls_0.averagePower 845.747691 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 1011 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT 36893 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 536760 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 298200 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 2608320 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 2166912 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) system.mem_ctrls_1.actBackEnergy 26345628 # Energy for active background per rank (pJ) system.mem_ctrls_1.preBackEnergy 403800 # Energy for precharge background per rank (pJ) system.mem_ctrls_1.totalEnergy 34902420 # Total energy per rank (pJ) system.mem_ctrls_1.averagePower 890.595050 # Core power per rank (mW) system.mem_ctrls_1.memoryStateTime::IDLE 832 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 37357 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 415 # DTB read hits system.cpu.dtb.read_misses 4 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 419 # DTB read accesses system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 298 # DTB write accesses system.cpu.dtb.data_hits 709 # DTB hits system.cpu.dtb.data_misses 8 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.itb.fetch_hits 2586 # ITB hits system.cpu.itb.fetch_misses 11 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_accesses 2597 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls system.cpu.numCycles 41659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls system.cpu.num_int_insts 2375 # number of integer instructions system.cpu.num_fp_insts 6 # number of float instructions system.cpu.num_int_register_reads 2998 # number of times the integer registers were read system.cpu.num_int_register_writes 1768 # number of times the integer registers were written system.cpu.num_fp_register_reads 6 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 41659 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 1248 # delay histogram for all message system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 1248 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 system.ruby.outstanding_req_hist::samples 3295 system.ruby.outstanding_req_hist::mean 1 system.ruby.outstanding_req_hist::gmean 1 system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist::total 3295 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 3294 system.ruby.latency_hist::mean 11.646934 system.ruby.latency_hist::gmean 2.114776 system.ruby.latency_hist::stdev 26.263922 system.ruby.latency_hist | 3185 96.69% 96.69% | 90 2.73% 99.42% | 14 0.43% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 3294 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 system.ruby.hit_latency_hist::samples 2668 system.ruby.hit_latency_hist::mean 1 system.ruby.hit_latency_hist::gmean 1 system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist::total 2668 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 626 system.ruby.miss_latency_hist::mean 57.023962 system.ruby.miss_latency_hist::gmean 51.467697 system.ruby.miss_latency_hist::stdev 32.986607 system.ruby.miss_latency_hist | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 626 system.ruby.Directory.incomplete_times 625 system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 7.489378 system.ruby.network.routers0.msg_count.Control::2 626 system.ruby.network.routers0.msg_count.Data::2 622 system.ruby.network.routers0.msg_count.Response_Data::4 626 system.ruby.network.routers0.msg_count.Writeback_Control::3 622 system.ruby.network.routers0.msg_bytes.Control::2 5008 system.ruby.network.routers0.msg_bytes.Data::2 44784 system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 system.ruby.network.routers1.percent_links_utilized 7.489378 system.ruby.network.routers1.msg_count.Control::2 626 system.ruby.network.routers1.msg_count.Data::2 622 system.ruby.network.routers1.msg_count.Response_Data::4 626 system.ruby.network.routers1.msg_count.Writeback_Control::3 622 system.ruby.network.routers1.msg_bytes.Control::2 5008 system.ruby.network.routers1.msg_bytes.Data::2 44784 system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 system.ruby.network.routers2.percent_links_utilized 7.489378 system.ruby.network.routers2.msg_count.Control::2 626 system.ruby.network.routers2.msg_count.Data::2 622 system.ruby.network.routers2.msg_count.Response_Data::4 626 system.ruby.network.routers2.msg_count.Writeback_Control::3 622 system.ruby.network.routers2.msg_bytes.Control::2 5008 system.ruby.network.routers2.msg_bytes.Data::2 44784 system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 system.ruby.network.msg_count.Control 1878 system.ruby.network.msg_count.Data 1866 system.ruby.network.msg_count.Response_Data 1878 system.ruby.network.msg_count.Writeback_Control 1866 system.ruby.network.msg_byte.Control 15024 system.ruby.network.msg_byte.Data 134352 system.ruby.network.msg_byte.Response_Data 135216 system.ruby.network.msg_byte.Writeback_Control 14928 system.ruby.network.routers0.throttle0.link_utilization 7.508582 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976 system.ruby.network.routers0.throttle1.link_utilization 7.470175 system.ruby.network.routers0.throttle1.msg_count.Control::2 626 system.ruby.network.routers0.throttle1.msg_count.Data::2 622 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784 system.ruby.network.routers1.throttle0.link_utilization 7.470175 system.ruby.network.routers1.throttle0.msg_count.Control::2 626 system.ruby.network.routers1.throttle0.msg_count.Data::2 622 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784 system.ruby.network.routers1.throttle1.link_utilization 7.508582 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976 system.ruby.network.routers2.throttle0.link_utilization 7.508582 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976 system.ruby.network.routers2.throttle1.link_utilization 7.470175 system.ruby.network.routers2.throttle1.msg_count.Control::2 626 system.ruby.network.routers2.throttle1.msg_count.Data::2 622 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 44784 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::samples 626 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1 | 626 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::total 626 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 32 system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 415 system.ruby.LD.latency_hist::mean 30.537349 system.ruby.LD.latency_hist::gmean 9.686440 system.ruby.LD.latency_hist::stdev 30.265140 system.ruby.LD.latency_hist | 170 40.96% 40.96% | 203 48.92% 89.88% | 35 8.43% 98.31% | 3 0.72% 99.04% | 3 0.72% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 415 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 system.ruby.LD.hit_latency_hist::samples 170 system.ruby.LD.hit_latency_hist::mean 1 system.ruby.LD.hit_latency_hist::gmean 1 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 170 system.ruby.LD.miss_latency_hist::bucket_size 32 system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 245 system.ruby.LD.miss_latency_hist::mean 51.032653 system.ruby.LD.miss_latency_hist::gmean 46.821080 system.ruby.LD.miss_latency_hist::stdev 22.902478 system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 245 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 294 system.ruby.ST.latency_hist::mean 16.663265 system.ruby.ST.latency_hist::gmean 3.036238 system.ruby.ST.latency_hist::stdev 32.952425 system.ruby.ST.latency_hist | 283 96.26% 96.26% | 6 2.04% 98.30% | 4 1.36% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 294 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 system.ruby.ST.hit_latency_hist::samples 210 system.ruby.ST.hit_latency_hist::mean 1 system.ruby.ST.hit_latency_hist::gmean 1 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 210 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 84 system.ruby.ST.miss_latency_hist::mean 55.821429 system.ruby.ST.miss_latency_hist::gmean 48.772534 system.ruby.ST.miss_latency_hist::stdev 40.751129 system.ruby.ST.miss_latency_hist | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 84 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 2585 system.ruby.IFETCH.latency_hist::mean 8.043714 system.ruby.IFETCH.latency_hist::gmean 1.589638 system.ruby.IFETCH.latency_hist::stdev 23.152025 system.ruby.IFETCH.latency_hist | 2529 97.83% 97.83% | 46 1.78% 99.61% | 6 0.23% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 2585 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 system.ruby.IFETCH.hit_latency_hist::samples 2288 system.ruby.IFETCH.hit_latency_hist::mean 1 system.ruby.IFETCH.hit_latency_hist::gmean 1 system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 2288 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 297 system.ruby.IFETCH.miss_latency_hist::mean 62.306397 system.ruby.IFETCH.miss_latency_hist::gmean 56.498895 system.ruby.IFETCH.miss_latency_hist::stdev 36.624977 system.ruby.IFETCH.miss_latency_hist | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 297 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 626 system.ruby.Directory.miss_mach_latency_hist::mean 57.023962 system.ruby.Directory.miss_mach_latency_hist::gmean 51.467697 system.ruby.Directory.miss_mach_latency_hist::stdev 32.986607 system.ruby.Directory.miss_mach_latency_hist | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 626 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 245 system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.032653 system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 46.821080 system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 22.902478 system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 245 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 84 system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.821429 system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.772534 system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 40.751129 system.ruby.ST.Directory.miss_type_mach_latency_hist | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 84 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 297 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 62.306397 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 56.498895 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 36.624977 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 system.ruby.Directory_Controller.GETX 626 0.00% 0.00% system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% system.ruby.L1Cache_Controller.Data 626 0.00% 0.00% system.ruby.L1Cache_Controller.Replacement 622 0.00% 0.00% system.ruby.L1Cache_Controller.Writeback_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.I.Load 245 0.00% 0.00% system.ruby.L1Cache_Controller.I.Ifetch 297 0.00% 0.00% system.ruby.L1Cache_Controller.I.Store 84 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 170 0.00% 0.00% system.ruby.L1Cache_Controller.M.Ifetch 2288 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 210 0.00% 0.00% system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00% ---------- End Simulation Statistics ----------