---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated sim_ticks 21382500 # Number of ticks simulated final_tick 21382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 21602 # Simulator instruction rate (inst/s) host_op_rate 39134 # Simulator op (including micro ops) rate (op/s) host_tick_rate 85845466 # Simulator tick rate (ticks/s) host_mem_usage 271116 # Number of bytes of host memory used host_seconds 0.25 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory system.physmem.bytes_read::total 26688 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory system.physmem.num_reads::total 417 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 832082310 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 416041155 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1248123465 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 832082310 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 832082310 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 832082310 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 416041155 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1248123465 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 31 # Per bank write bursts system.physmem.perBankRdBursts::1 1 # Per bank write bursts system.physmem.perBankRdBursts::2 5 # Per bank write bursts system.physmem.perBankRdBursts::3 8 # Per bank write bursts system.physmem.perBankRdBursts::4 51 # Per bank write bursts system.physmem.perBankRdBursts::5 44 # Per bank write bursts system.physmem.perBankRdBursts::6 21 # Per bank write bursts system.physmem.perBankRdBursts::7 37 # Per bank write bursts system.physmem.perBankRdBursts::8 23 # Per bank write bursts system.physmem.perBankRdBursts::9 71 # Per bank write bursts system.physmem.perBankRdBursts::10 64 # Per bank write bursts system.physmem.perBankRdBursts::11 16 # Per bank write bursts system.physmem.perBankRdBursts::12 2 # Per bank write bursts system.physmem.perBankRdBursts::13 19 # Per bank write bursts system.physmem.perBankRdBursts::14 7 # Per bank write bursts system.physmem.perBankRdBursts::15 17 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts system.physmem.perBankWrBursts::4 0 # Per bank write bursts system.physmem.perBankWrBursts::5 0 # Per bank write bursts system.physmem.perBankWrBursts::6 0 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts system.physmem.perBankWrBursts::10 0 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 21259500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 417 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 161.877699 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 262.561948 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 36 37.11% 37.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 27 27.84% 64.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 16 16.49% 81.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 4 4.12% 85.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 4 4.12% 91.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 2 2.06% 93.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation system.physmem.totQLat 5040250 # Total ticks spent queuing system.physmem.totMemAccLat 12859000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers system.physmem.avgQLat 12086.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 30836.93 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1248.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1248.12 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 9.75 # Data bus utilization in percentage system.physmem.busUtilRead 9.75 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 309 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 50982.01 # Average gap between requests system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 173880 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 94875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 912600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 13023390 # Total energy per rank (pJ) system.physmem_0.averagePower 822.573188 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 13750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1497600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 10696050 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 117000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 13970445 # Total energy per rank (pJ) system.physmem_1.averagePower 882.390336 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 15223250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 3511 # Number of BP lookups system.cpu.branchPred.condPredicted 3511 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 567 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2933 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu.branchPred.usedRAS 414 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 2933 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 496 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 2437 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 406 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.pwrStateResidencyTicks::ON 21382500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 42766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 11494 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 15919 # Number of instructions fetch has processed system.cpu.fetch.Branches 3511 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 910 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1335 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 2042 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 23431 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.223593 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.745730 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 19161 81.78% 81.78% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 166 0.71% 82.48% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 156 0.67% 83.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 235 1.00% 84.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 218 0.93% 85.08% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 215 0.92% 86.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 266 1.14% 87.14% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 168 0.72% 87.85% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 2846 12.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 23431 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.082098 # Number of branch fetches per cycle system.cpu.fetch.rate 0.372235 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 11586 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 7313 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3407 # Number of cycles decode is running system.cpu.decode.UnblockCycles 458 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 667 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 26631 # Number of instructions handled by decode system.cpu.rename.SquashCycles 667 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 11849 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2059 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1032 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 3561 # Number of cycles rename is running system.cpu.rename.UnblockCycles 4263 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 25112 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full system.cpu.rename.SQFullEvents 4127 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 61260 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 35084 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 24 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 1417 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2745 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1552 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 21890 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 18162 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 138 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 12165 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 16733 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 23431 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.775127 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.748484 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 18255 77.91% 77.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1208 5.16% 83.07% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 874 3.73% 86.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 566 2.42% 89.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 836 3.57% 92.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 600 2.56% 95.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 613 2.62% 97.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 346 1.48% 99.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 133 0.57% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 23431 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 213 76.07% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.07% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 51 18.21% 94.29% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 16 5.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 14483 79.74% 79.75% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.79% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.83% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2327 12.81% 92.64% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1337 7.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 18162 # Type of FU issued system.cpu.iq.rate 0.424683 # Inst issue rate system.cpu.iq.fu_busy_cnt 280 # FU busy when requested system.cpu.iq.fu_busy_rate 0.015417 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 60165 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 34082 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 16453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 18436 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 200 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1692 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 617 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 667 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 141 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 21912 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2745 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1552 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 140 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 685 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 805 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 17078 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3333 # number of memory reference insts executed system.cpu.iew.exec_branches 1727 # Number of branches executed system.cpu.iew.exec_stores 1245 # Number of stores executed system.cpu.iew.exec_rate 0.399336 # Inst execution rate system.cpu.iew.wb_sent 16776 # cumulative count of insts sent to commit system.cpu.iew.wb_count 16457 # cumulative count of insts written-back system.cpu.iew.wb_producers 11050 # num instructions producing a value system.cpu.iew.wb_consumers 17247 # num instructions consuming a value system.cpu.iew.wb_rate 0.384815 # insts written-back per cycle system.cpu.iew.wb_fanout 0.640691 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 655 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 21365 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.456213 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.347578 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 18118 84.80% 84.80% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 989 4.63% 89.43% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 572 2.68% 92.11% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 729 3.41% 95.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 380 1.78% 97.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 132 0.62% 97.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 120 0.56% 98.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 73 0.34% 98.82% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 252 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 21365 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1988 # Number of memory references committed system.cpu.commit.loads 1053 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 1208 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9653 # Number of committed integer instructions. system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction system.cpu.commit.bw_lim_events 252 # number cycles where commit BW limit reached system.cpu.rob.rob_reads 43024 # The number of ROB reads system.cpu.rob.rob_writes 45919 # The number of ROB writes system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 19335 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.949071 # CPI: Cycles Per Instruction system.cpu.cpi_total 7.949071 # CPI: Total CPI of All Threads system.cpu.ipc 0.125801 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.125801 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 21733 # number of integer regfile reads system.cpu.int_regfile_writes 13291 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads system.cpu.cc_regfile_reads 8307 # number of cc regfile reads system.cpu.cc_regfile_writes 5092 # number of cc regfile writes system.cpu.misc_regfile_reads 7667 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 81.328051 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2579 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 18.553957 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 81.328051 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.019855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.019855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5679 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5679 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1719 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1719 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 2579 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 2579 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2579 # number of overall hits system.cpu.dcache.overall_hits::total 2579 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses system.cpu.dcache.overall_misses::total 191 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 9465500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 9465500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 6317000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 6317000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 15782500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 15782500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 15782500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 15782500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1835 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1835 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2770 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2770 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2770 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2770 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063215 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.063215 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.068953 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.068953 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.068953 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.068953 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81599.137931 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 81599.137931 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84226.666667 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 84226.666667 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 82630.890052 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 82630.890052 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 75 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5739000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5739000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6242000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 6242000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11981000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11981000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034877 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.050181 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.050181 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89671.875000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89671.875000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83226.666667 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83226.666667 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 130.610950 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1656 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.935484 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 130.610950 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.063775 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.063775 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4363 # Number of tag accesses system.cpu.icache.tags.data_accesses 4363 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1656 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1656 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1656 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1656 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1656 # number of overall hits system.cpu.icache.overall_hits::total 1656 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses system.cpu.icache.overall_misses::total 386 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 29282500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 29282500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 29282500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 29282500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 29282500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 29282500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2042 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2042 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2042 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 2042 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 2042 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2042 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189030 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.189030 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.189030 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.189030 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.189030 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.189030 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75861.398964 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 75861.398964 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 75861.398964 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 75861.398964 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22839500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 22839500 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22839500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 22839500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22839500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 22839500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136631 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.136631 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136631 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.136631 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81862.007168 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81862.007168 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 212.046379 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.650071 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 81.396308 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003987 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002484 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006471 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 139 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 139 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6129000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 6129000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22409000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 22409000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5642000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5642000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 22409000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 11771000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 34180000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 22409000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 11771000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 34180000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 75 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 75 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81720 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81720 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80607.913669 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80607.913669 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88156.250000 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88156.250000 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 81966.426859 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 81966.426859 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5379000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5379000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19629000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19629000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5002000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5002000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19629000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10381000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 30010000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19629000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10381000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 30010000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71720 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71720 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70607.913669 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70607.913669 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78156.250000 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78156.250000 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 75 # Transaction distribution system.membus.trans_dist::ReadExResp 75 # Transaction distribution system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 417 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 417 # Request fanout histogram system.membus.reqLayer0.occupancy 503500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 2228500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.4 # Layer utilization (%) ---------- End Simulation Statistics ----------