---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000114                       # Number of seconds simulated
sim_ticks                                   113941500                       # Number of ticks simulated
final_tick                                  113941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 130117                       # Simulator instruction rate (inst/s)
host_op_rate                                   130117                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               13474596                       # Simulator tick rate (ticks/s)
host_mem_usage                                 234988                       # Number of bytes of host memory used
host_seconds                                     8.46                       # Real time elapsed on the host
sim_insts                                     1100269                       # Number of instructions simulated
sim_ops                                       1100269                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            23232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                43008                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        23232                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5376                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          320                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          384                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           29312                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               363                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                84                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   672                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           203894104                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            94364213                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            47182107                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            11233835                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             2808459                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7301993                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             3370150                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7301993                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               377456853                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      203894104                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       47182107                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        2808459                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        3370150                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          257254819                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          203894104                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           94364213                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           47182107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           11233835                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            2808459                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7301993                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            3370150                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7301993                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              377456853                       # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          227884                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                   88195                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted             85894                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect              1314                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups                85741                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                   83416                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                     517                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles             17885                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        523742                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      88195                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             83933                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       172058                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   4069                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 15014                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1439                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     6122                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  517                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            209007                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.505859                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.211450                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   36949     17.68%     17.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   85270     40.80%     58.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     593      0.28%     58.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1005      0.48%     59.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     500      0.24%     59.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   81190     38.85%     98.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     659      0.32%     98.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     361      0.17%     98.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2480      1.19%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              209007                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.387017                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.298283                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   18552                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                16516                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   170985                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  348                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2606                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                520718                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2606                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   19281                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   2206                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         13583                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   170639                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  692                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                517471                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  300                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             353567                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1032190                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups         1032190                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               339600                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13967                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               909                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           933                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     4082                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              165924                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              83735                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            81055                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           80764                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    432543                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                950                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   429278                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              221                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          11501                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        11387                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           391                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       209007                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.053893                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.097042                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              36203     17.32%     17.32% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               5360      2.56%     19.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              82686     39.56%     59.45% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              82056     39.26%     98.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1635      0.78%     99.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                680      0.33%     99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                282      0.13%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 94      0.04%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 11      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         209007                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     43     16.23%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                   110     41.51%     57.74% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  112     42.26%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               180966     42.16%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.16% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              165240     38.49%     80.65% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              83072     19.35%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                429278                       # Type of FU issued
system.cpu0.iq.rate                          1.883757                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        265                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000617                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1068049                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           445050                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       427325                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                429543                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           80408                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2540                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           56                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1537                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked            8                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2606                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   1701                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   86                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             515038                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              368                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               165924                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               83735                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               837                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    90                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            56                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           370                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1149                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1519                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               428170                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               164921                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1108                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        81545                       # number of nop insts executed
system.cpu0.iew.exec_refs                      247840                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   85100                       # Number of branches executed
system.cpu0.iew.exec_stores                     82919                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.878895                       # Inst execution rate
system.cpu0.iew.wb_sent                        427676                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       427325                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   253224                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   255650                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.875186                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.990510                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts        501745                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps          501745                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts          13260                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1314                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       206418                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.430723                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.136815                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        36760     17.81%     17.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        84779     41.07%     58.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2446      1.18%     60.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          715      0.35%     60.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          578      0.28%     60.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        80055     38.78%     99.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          554      0.27%     99.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          230      0.11%     99.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          301      0.15%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       206418                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              501745                       # Number of instructions committed
system.cpu0.commit.committedOps                501745                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        245582                       # Number of memory references committed
system.cpu0.commit.loads                       163384                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     84086                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   337930                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  301                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      719961                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1032633                       # The number of ROB writes
system.cpu0.timesIdled                            343                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          18877                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     420844                       # Number of Instructions Simulated
system.cpu0.committedOps                       420844                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               420844                       # Number of Instructions Simulated
system.cpu0.cpi                              0.541493                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.541493                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.846747                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.846747                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  766075                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 345063                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 249668                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   308                       # number of replacements
system.cpu0.icache.tagsinuse               248.197747                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    5361                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   601                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.920133                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   248.197747                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.484761                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.484761                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         5361                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5361                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5361                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5361                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5361                       # number of overall hits
system.cpu0.icache.overall_hits::total           5361                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          761                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          761                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          761                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           761                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          761                       # number of overall misses
system.cpu0.icache.overall_misses::total          761                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     29540500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     29540500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     29540500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     29540500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     29540500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     29540500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         6122                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         6122                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         6122                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         6122                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         6122                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         6122                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.124306                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.124306                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.124306                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.124306                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.124306                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.124306                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38818.002628                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 38818.002628                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38818.002628                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 38818.002628                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38818.002628                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 38818.002628                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        13500                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs        13500                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          159                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          159                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          159                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          159                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          159                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          159                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          602                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          602                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          602                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          602                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          602                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          602                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22436000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     22436000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22436000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     22436000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22436000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     22436000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.098334                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.098334                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.098334                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37269.102990                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 37269.102990                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 37269.102990                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     2                       # number of replacements
system.cpu0.dcache.tagsinuse               144.386808                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  165433                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                973.135294                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   144.386808                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.282005                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.282005                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        83919                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          83919                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        81593                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         81593                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           18                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       165512                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          165512                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       165512                       # number of overall hits
system.cpu0.dcache.overall_hits::total         165512                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          525                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          525                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          563                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          563                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           24                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           24                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1088                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1088                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1088                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1088                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16325500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     16325500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     28838494                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     28838494                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       480000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       480000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     45163994                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     45163994                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     45163994                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     45163994                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        84444                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        84444                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        82156                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        82156                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       166600                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       166600                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       166600                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       166600                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006217                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006217                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006853                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006853                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.571429                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.571429                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006531                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006531                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006531                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006531                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31096.190476                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31096.190476                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51222.902309                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 51222.902309                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        20000                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total        20000                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41511.023897                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 41511.023897                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41511.023897                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41511.023897                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       119500                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               18                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  6638.888889                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          345                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          345                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          392                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          392                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          737                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          737                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          737                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          737                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          180                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          180                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          171                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          171                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           24                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           24                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          351                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          351                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5693511                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5693511                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6731000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6731000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       405000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       405000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     12424511                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     12424511                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     12424511                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     12424511                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002132                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002132                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002081                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002081                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.571429                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.571429                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002107                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002107                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31630.616667                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31630.616667                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39362.573099                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39362.573099                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        16875                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        16875                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35397.467236                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35397.467236                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35397.467236                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35397.467236                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          191339                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                   49631                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted             46572                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect              1528                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups                42950                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                   41997                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                     805                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles             33375                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        271825                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      49631                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             42802                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                        98758                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4453                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 42292                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6725                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1070                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    23889                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  317                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            185079                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.468697                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.066601                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   86321     46.64%     46.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   51121     27.62%     74.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    7925      4.28%     78.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3336      1.80%     80.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     734      0.40%     80.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   30013     16.22%     96.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1151      0.62%     97.58% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     885      0.48%     98.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3593      1.94%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              185079                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.259388                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.420646                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   40472                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                37211                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    91012                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 6805                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2854                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                267804                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2854                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   41302                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  21637                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         14674                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    84497                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                13390                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                265308                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                    16                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   60                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             184298                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               499771                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          499771                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               168579                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   15719                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1236                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1367                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    16177                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               72909                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              33507                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            35450                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           28267                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    217311                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               8226                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   220400                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued              173                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          13138                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        12222                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           799                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       185079                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.190843                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.296813                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              84217     45.50%     45.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              27917     15.08%     60.59% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              33688     18.20%     78.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              34243     18.50%     97.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3324      1.80%     99.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1232      0.67%     99.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                345      0.19%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         185079                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     21      6.60%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    87     27.36%     33.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     66.04%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               108844     49.38%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.38% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               78735     35.72%     85.11% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              32821     14.89%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                220400                       # Type of FU issued
system.cpu1.iq.rate                          1.151882                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        318                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001443                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            626370                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           238714                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       218326                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                220718                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           28122                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2824                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1558                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2854                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   2376                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   88                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             261974                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              434                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                72909                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               33507                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1131                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    89                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           510                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         1187                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1697                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               219051                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                71704                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1349                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        36437                       # number of nop insts executed
system.cpu1.iew.exec_refs                      104435                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   45735                       # Number of branches executed
system.cpu1.iew.exec_stores                     32731                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.144832                       # Inst execution rate
system.cpu1.iew.wb_sent                        218612                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       218326                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   121254                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   126110                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.141043                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.961494                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts        246738                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps          246738                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts          15223                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           7427                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1528                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       175501                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.405907                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.932846                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        84843     48.34%     48.34% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        43671     24.88%     73.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6232      3.55%     76.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         8331      4.75%     81.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1551      0.88%     82.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        28453     16.21%     98.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          613      0.35%     98.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7          993      0.57%     99.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          814      0.46%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       175501                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              246738                       # Number of instructions committed
system.cpu1.commit.committedOps                246738                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        102034                       # Number of memory references committed
system.cpu1.commit.loads                        70085                       # Number of loads committed
system.cpu1.commit.membars                       6711                       # Number of memory barriers committed
system.cpu1.commit.branches                     44619                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   168775                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  814                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      436061                       # The number of ROB reads
system.cpu1.rob.rob_writes                     526790                       # The number of ROB writes
system.cpu1.timesIdled                            250                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           6260                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       36543                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     204620                       # Number of Instructions Simulated
system.cpu1.committedOps                       204620                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               204620                       # Number of Instructions Simulated
system.cpu1.cpi                              0.935094                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.935094                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.069411                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.069411                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  373202                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 174771                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 106146                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.icache.replacements                   322                       # number of replacements
system.cpu1.icache.tagsinuse                90.902674                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   23372                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 53.605505                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    90.902674                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.177544                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.177544                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        23372                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          23372                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        23372                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           23372                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        23372                       # number of overall hits
system.cpu1.icache.overall_hits::total          23372                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          517                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          517                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          517                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           517                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          517                       # number of overall misses
system.cpu1.icache.overall_misses::total          517                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     11874500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     11874500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     11874500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     11874500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     11874500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     11874500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        23889                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        23889                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        23889                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        23889                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        23889                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        23889                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021642                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.021642                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021642                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.021642                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021642                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.021642                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22968.085106                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 22968.085106                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22968.085106                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 22968.085106                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22968.085106                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 22968.085106                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs        32000                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs        32000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           81                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           81                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           81                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           81                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           81                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          436                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          436                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          436                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          436                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8863000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      8863000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8863000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      8863000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8863000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      8863000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018251                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.018251                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.018251                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20327.981651                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 20327.981651                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 20327.981651                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     0                       # number of replacements
system.cpu1.dcache.tagsinuse                27.508331                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   38240                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1318.620690                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    27.508331                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.053727                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.053727                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        43171                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          43171                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        31745                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         31745                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           15                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        74916                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           74916                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        74916                       # number of overall hits
system.cpu1.dcache.overall_hits::total          74916                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          395                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          395                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          134                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          134                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          529                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           529                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          529                       # number of overall misses
system.cpu1.dcache.overall_misses::total          529                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     11922500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total     11922500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3308000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3308000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1319000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total      1319000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     15230500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     15230500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     15230500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     15230500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        43566                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        43566                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        31879                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        31879                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        75445                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        75445                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        75445                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        75445                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009067                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.009067                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004203                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.004203                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.785714                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.785714                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007012                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.007012                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007012                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.007012                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 30183.544304                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 30183.544304                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24686.567164                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24686.567164                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23981.818182                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 23981.818182                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28791.115312                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 28791.115312                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28791.115312                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 28791.115312                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          229                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          229                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           34                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          263                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          263                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          263                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          263                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          166                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          100                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          266                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          266                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      3273504                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      3273504                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1639000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1639000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data      1148500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total      1148500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4912504                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      4912504                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4912504                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      4912504                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003810                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003810                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003137                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003137                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.785714                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003526                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003526                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003526                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003526                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19719.903614                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19719.903614                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data        16390                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total        16390                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20881.818182                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20881.818182                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18468.060150                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18468.060150                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18468.060150                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18468.060150                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          191032                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                   57390                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted             54193                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect              1550                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups                50681                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                   49645                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                     804                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles             29539                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        321276                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      57390                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             50449                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       112230                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   4473                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 35583                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6761                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1077                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    20533                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  334                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            188044                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.708515                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.158633                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   75814     40.32%     40.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   56962     30.29%     70.61% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    6138      3.26%     73.87% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3348      1.78%     75.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     769      0.41%     76.06% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   39287     20.89%     96.95% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1207      0.64%     97.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     911      0.48%     98.08% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3608      1.92%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              188044                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.300421                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.681792                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   35225                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                31967                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                   106013                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 5229                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2849                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                316907                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2849                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   36004                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  16323                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         14784                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                   101094                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                10229                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                314547                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                    23                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   56                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             220052                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               605102                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          605102                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               204228                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   15824                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1236                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1356                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    12873                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               89800                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              42907                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            42940                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           37601                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    260749                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               6485                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   262481                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued              146                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          13131                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        11780                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           687                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       188044                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.395849                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.314415                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              73292     38.98%     38.98% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              23055     12.26%     51.24% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              43065     22.90%     74.14% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              43582     23.18%     97.31% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3340      1.78%     99.09% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1248      0.66%     99.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                346      0.18%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 54      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 62      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         188044                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     21      6.65%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.65% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    85     26.90%     33.54% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     66.46%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               126143     48.06%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.06% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               94161     35.87%     83.93% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              42177     16.07%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                262481                       # Type of FU issued
system.cpu2.iq.rate                          1.374016                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        316                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001204                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            713468                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           280402                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       260315                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                262797                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           37443                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2702                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1644                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2849                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   1860                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   77                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             311245                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              407                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                89800                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               42907                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1163                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    74                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           516                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         1201                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1717                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               261072                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                88760                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1409                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        44011                       # number of nop insts executed
system.cpu2.iew.exec_refs                      130847                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   53503                       # Number of branches executed
system.cpu2.iew.exec_stores                     42087                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.366640                       # Inst execution rate
system.cpu2.iew.wb_sent                        260613                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       260315                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   147697                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   152590                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.362677                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.967934                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts        296145                       # The number of committed instructions
system.cpu2.commit.commitCommittedOps          296145                       # The number of committed instructions
system.cpu2.commit.commitSquashedInsts          15092                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           5798                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1550                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       178435                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.659680                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.032759                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        72400     40.57%     40.57% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        51371     28.79%     69.36% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6245      3.50%     72.86% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6660      3.73%     76.60% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1539      0.86%     77.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        37793     21.18%     98.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          621      0.35%     98.99% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7          991      0.56%     99.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          815      0.46%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       178435                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              296145                       # Number of instructions committed
system.cpu2.commit.committedOps                296145                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        128361                       # Number of memory references committed
system.cpu2.commit.loads                        87098                       # Number of loads committed
system.cpu2.commit.membars                       5084                       # Number of memory barriers committed
system.cpu2.commit.branches                     52312                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   202794                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  815                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      488270                       # The number of ROB reads
system.cpu2.rob.rob_writes                     625337                       # The number of ROB writes
system.cpu2.timesIdled                            230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           2988                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       36850                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     247959                       # Number of Instructions Simulated
system.cpu2.committedOps                       247959                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               247959                       # Number of Instructions Simulated
system.cpu2.cpi                              0.770418                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.770418                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.297997                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.297997                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  452595                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 210629                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 132559                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.icache.replacements                   322                       # number of replacements
system.cpu2.icache.tagsinuse                84.182173                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   20037                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   438                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 45.746575                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    84.182173                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.164418                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.164418                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        20037                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          20037                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        20037                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           20037                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        20037                       # number of overall hits
system.cpu2.icache.overall_hits::total          20037                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          496                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          496                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          496                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           496                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          496                       # number of overall misses
system.cpu2.icache.overall_misses::total          496                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7608500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      7608500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      7608500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      7608500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      7608500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      7608500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        20533                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        20533                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        20533                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        20533                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        20533                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        20533                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024156                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.024156                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024156                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.024156                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024156                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.024156                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15339.717742                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 15339.717742                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15339.717742                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 15339.717742                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15339.717742                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 15339.717742                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           58                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           58                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           58                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           58                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          438                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          438                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          438                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          438                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          438                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          438                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5673500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      5673500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5673500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      5673500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5673500                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      5673500                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021332                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.021332                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.021332                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12953.196347                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12953.196347                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12953.196347                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     0                       # number of replacements
system.cpu2.dcache.tagsinuse                24.868946                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   47444                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1694.428571                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    24.868946                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.048572                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.048572                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        50906                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          50906                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        41055                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         41055                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           12                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        91961                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           91961                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        91961                       # number of overall hits
system.cpu2.dcache.overall_hits::total          91961                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          392                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          392                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          140                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           56                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          532                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           532                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          532                       # number of overall misses
system.cpu2.dcache.overall_misses::total          532                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     10132000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total     10132000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3391500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3391500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1227500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total      1227500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     13523500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     13523500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     13523500                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     13523500                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        51298                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        51298                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        41195                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        41195                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        92493                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        92493                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        92493                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        92493                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007642                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.007642                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003398                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003398                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.823529                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.823529                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005752                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.005752                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005752                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.005752                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 25846.938776                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 25846.938776                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data        24225                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total        24225                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21919.642857                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 21919.642857                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25420.112782                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 25420.112782                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25420.112782                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 25420.112782                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          241                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          241                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           35                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          276                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          276                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          276                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          276                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          151                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          151                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           56                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          256                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          256                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          256                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2456507                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2456507                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1732500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1732500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1052000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1052000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4189007                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      4189007                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4189007                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      4189007                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002944                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.002944                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002549                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002549                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.823529                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.823529                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002768                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.002768                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002768                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.002768                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16268.258278                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16268.258278                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        16500                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        16500                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18785.714286                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18785.714286                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16363.308594                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16363.308594                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16363.308594                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16363.308594                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          190752                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.BPredUnit.lookups                   53643                       # Number of BP lookups
system.cpu3.BPredUnit.condPredicted             50394                       # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect              1547                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups                46912                       # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits                   45897                       # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS                     838                       # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles             31381                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        296607                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      53643                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             46735                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       105748                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4379                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 39758                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6743                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1058                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    22503                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  317                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            187456                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.582275                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.112091                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   81708     43.59%     43.59% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   54260     28.95%     72.53% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    7170      3.82%     76.36% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3258      1.74%     78.10% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     706      0.38%     78.47% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   34710     18.52%     96.99% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1204      0.64%     97.63% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     885      0.47%     98.10% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3555      1.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              187456                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.281219                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.554935                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   37941                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                35250                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    98653                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 6106                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2763                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                292333                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2763                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   38724                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  18900                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         15518                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    92845                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                11963                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                289904                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   41                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             201915                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               552179                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          552179                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               186764                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   15151                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1285                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1418                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    14719                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               81367                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              38245                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            39205                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           32957                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    238924                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               7473                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   241868                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued              117                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          12521                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        10991                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           722                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       187456                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.290265                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.307286                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              79218     42.26%     42.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              25849     13.79%     56.05% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              38415     20.49%     76.54% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              38999     20.80%     97.35% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3297      1.76%     99.10% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1241      0.66%     99.77% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                322      0.17%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 62      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         187456                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     22      7.19%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      7.19% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    74     24.18%     31.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     68.63%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               117603     48.62%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.62% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               86736     35.86%     84.48% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              37529     15.52%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                241868                       # Type of FU issued
system.cpu3.iq.rate                          1.267971                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        306                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001265                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            671615                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           258950                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       239863                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                242174                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           32833                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2526                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1583                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2763                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   1788                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             286739                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              413                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                81367                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               38245                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1210                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    58                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            32                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           503                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         1210                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1713                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               240581                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                80413                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1287                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        40342                       # number of nop insts executed
system.cpu3.iew.exec_refs                      117868                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   49825                       # Number of branches executed
system.cpu3.iew.exec_stores                     37455                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.261224                       # Inst execution rate
system.cpu3.iew.wb_sent                        240146                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       239863                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   134653                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   139524                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.257460                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.965088                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts        272332                       # The number of committed instructions
system.cpu3.commit.commitCommittedOps          272332                       # The number of committed instructions
system.cpu3.commit.commitSquashedInsts          14381                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           6751                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1547                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       177951                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.530376                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.985731                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        79207     44.51%     44.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        47739     26.83%     71.34% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6222      3.50%     74.83% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         7617      4.28%     79.11% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1549      0.87%     79.98% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        33224     18.67%     98.66% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          582      0.33%     98.98% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7          998      0.56%     99.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          813      0.46%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       177951                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              272332                       # Number of instructions committed
system.cpu3.commit.committedOps                272332                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        115503                       # Number of memory references committed
system.cpu3.commit.loads                        78841                       # Number of loads committed
system.cpu3.commit.membars                       6036                       # Number of memory barriers committed
system.cpu3.commit.branches                     48661                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   186284                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  813                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      463264                       # The number of ROB reads
system.cpu3.rob.rob_writes                     576197                       # The number of ROB writes
system.cpu3.timesIdled                            226                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           3296                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       37130                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     226846                       # Number of Instructions Simulated
system.cpu3.committedOps                       226846                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               226846                       # Number of Instructions Simulated
system.cpu3.cpi                              0.840888                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.840888                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.189220                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.189220                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  413495                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 192863                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 119579                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.icache.replacements                   323                       # number of replacements
system.cpu3.icache.tagsinuse                88.254899                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   21999                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   439                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 50.111617                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    88.254899                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.172373                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.172373                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        21999                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          21999                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        21999                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           21999                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        21999                       # number of overall hits
system.cpu3.icache.overall_hits::total          21999                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          504                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          504                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          504                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           504                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          504                       # number of overall misses
system.cpu3.icache.overall_misses::total          504                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7701000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      7701000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      7701000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      7701000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      7701000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      7701000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        22503                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        22503                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        22503                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        22503                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        22503                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        22503                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.022397                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.022397                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.022397                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.022397                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.022397                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.022397                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15279.761905                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 15279.761905                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15279.761905                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 15279.761905                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15279.761905                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 15279.761905                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           65                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           65                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           65                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           65                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           65                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          439                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          439                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          439                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          439                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          439                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          439                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5678000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      5678000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5678000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      5678000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5678000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      5678000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.019509                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.019509                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.019509                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12933.940774                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12933.940774                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12933.940774                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     0                       # number of replacements
system.cpu3.dcache.tagsinuse                26.059158                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   42792                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1528.285714                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    26.059158                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.050897                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.050897                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        47204                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          47204                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        36453                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         36453                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        83657                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           83657                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        83657                       # number of overall hits
system.cpu3.dcache.overall_hits::total          83657                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          361                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          361                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          140                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           55                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          501                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           501                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          501                       # number of overall misses
system.cpu3.dcache.overall_misses::total          501                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9450000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      9450000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3328500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      3328500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1305500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total      1305500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data     12778500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total     12778500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data     12778500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total     12778500                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        47565                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        47565                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        36593                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        36593                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           69                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        84158                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        84158                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        84158                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        84158                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007590                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.007590                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003826                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.003826                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.797101                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.797101                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005953                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.005953                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005953                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.005953                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 26177.285319                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 26177.285319                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        23775                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total        23775                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23736.363636                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 23736.363636                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 25505.988024                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 25505.988024                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 25505.988024                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 25505.988024                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          206                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          206                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          239                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          239                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          239                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          239                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          155                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           55                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          262                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          262                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2585504                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2585504                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1735000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1735000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data      1134500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total      1134500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4320504                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      4320504                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4320504                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      4320504                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003259                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003259                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002924                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002924                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.797101                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.797101                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003113                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003113                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003113                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003113                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16680.670968                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16680.670968                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16214.953271                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16214.953271                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20627.272727                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20627.272727                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16490.473282                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16490.473282                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16490.473282                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16490.473282                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       436.890326                       # Cycle average of tags in use
system.l2c.total_refs                            1480                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           538                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.750929                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            0.838452                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           294.676580                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            59.534459                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            68.181124                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             5.702984                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst             2.344879                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             0.730463                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             4.107761                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.773625                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004496                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000908                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.001040                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000087                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000036                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000011                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000063                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000012                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.006666                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                239                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                350                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                428                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                431                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1480                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 239                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 350                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 428                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 431                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1480                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                239                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                350                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                428                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                431                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1480                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              363                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               86                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  550                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            15                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                75                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               363                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                86                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   681                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              363                       # number of overall misses
system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               86                       # number of overall misses
system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               10                       # number of overall misses
system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                8                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  681                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     19255500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      4177000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      4495500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       377500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst       449500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       388000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       29248000                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      5163500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       751000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       663000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       658499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      7235999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     19255500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      9340500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      4495500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1128500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       449500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data       715500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       388000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       710999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        36483999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     19255500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      9340500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      4495500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1128500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       449500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data       715500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       388000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       710999                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       36483999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            602                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            436                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            438                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            439                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2030                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           15                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              78                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             602                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             436                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             438                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             439                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2161                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            602                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            436                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            438                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            439                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2161                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.602990                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.197248                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.022831                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.018223                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.270936                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.869565                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.961538                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.602990                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.197248                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.022831                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.018223                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.315132                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.602990                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.197248                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.022831                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.018223                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.315132                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.454545                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 56445.945946                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.255814                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 53928.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst        44950                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst        48500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53178.181818                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54930.851064                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57769.230769                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data        55250                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54874.916667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 55236.633588                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53045.454545                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 55598.214286                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52273.255814                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        56425                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst        44950                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 55038.461538                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        48500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 54692.230769                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53574.154185                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53045.454545                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 55598.214286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52273.255814                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        56425                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst        44950                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        48500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53574.154185                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 9                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          363                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           84                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst            5                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             541                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           15                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           21                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           75                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          363                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           84                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              672                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          363                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           84                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             672                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14840000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3282500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3420000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data       291500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       200000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       240000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     22354000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       800000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       600000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       844000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       765000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3009000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4019000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       593500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       516500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       511500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5640500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     14840000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      7301500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      3420000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       885000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst       200000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       556500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       240000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       551500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     27994500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     14840000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      7301500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      3420000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       885000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst       200000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       556500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       240000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       551500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     27994500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.011416                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.266502                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.869565                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.961538                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011416                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.310967                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011416                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.310967                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44358.108108                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 41319.778189                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40263.157895                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        40120                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42755.319149                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        42625                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 43057.251908                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43461.309524                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        44250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 41658.482143                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43461.309524                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        44250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 41658.482143                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------