---------- Begin Simulation Statistics ---------- sim_seconds 0.000224 # Number of seconds simulated sim_ticks 224044586 # Number of ticks simulated final_tick 224044586 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_tick_rate 1786168 # Simulator tick rate (ticks/s) host_mem_usage 347548 # Number of bytes of host memory used host_seconds 125.43 # Real time elapsed on the host system.physmem.bytes_read::cpu0 89715 # Number of bytes read from this memory system.physmem.bytes_read::cpu1 89291 # Number of bytes read from this memory system.physmem.bytes_read::cpu2 88175 # Number of bytes read from this memory system.physmem.bytes_read::cpu3 85667 # Number of bytes read from this memory system.physmem.bytes_read::cpu4 87042 # Number of bytes read from this memory system.physmem.bytes_read::cpu5 87583 # Number of bytes read from this memory system.physmem.bytes_read::cpu6 89679 # Number of bytes read from this memory system.physmem.bytes_read::cpu7 83220 # Number of bytes read from this memory system.physmem.bytes_read::total 700372 # Number of bytes read from this memory system.physmem.bytes_written::writebacks 455360 # Number of bytes written to this memory system.physmem.bytes_written::cpu0 5322 # Number of bytes written to this memory system.physmem.bytes_written::cpu1 5377 # Number of bytes written to this memory system.physmem.bytes_written::cpu2 5241 # Number of bytes written to this memory system.physmem.bytes_written::cpu3 5325 # Number of bytes written to this memory system.physmem.bytes_written::cpu4 5339 # Number of bytes written to this memory system.physmem.bytes_written::cpu5 5367 # Number of bytes written to this memory system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory system.physmem.bytes_written::cpu7 5417 # Number of bytes written to this memory system.physmem.bytes_written::total 498192 # Number of bytes written to this memory system.physmem.num_reads::cpu0 11091 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1 11171 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2 11126 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3 11075 # Number of read requests responded to by this memory system.physmem.num_reads::cpu4 11127 # Number of read requests responded to by this memory system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory system.physmem.num_reads::cpu6 11244 # Number of read requests responded to by this memory system.physmem.num_reads::cpu7 11085 # Number of read requests responded to by this memory system.physmem.num_reads::total 88957 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 7115 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0 5322 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1 5377 # Number of write requests responded to by this memory system.physmem.num_writes::cpu2 5241 # Number of write requests responded to by this memory system.physmem.num_writes::cpu3 5325 # Number of write requests responded to by this memory system.physmem.num_writes::cpu4 5339 # Number of write requests responded to by this memory system.physmem.num_writes::cpu5 5367 # Number of write requests responded to by this memory system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory system.physmem.num_writes::cpu7 5417 # Number of write requests responded to by this memory system.physmem.num_writes::total 49947 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0 400433689 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1 398541208 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2 393560057 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3 382365856 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu4 388503028 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu5 390917726 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu6 400273006 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu7 371443923 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3126038493 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2032452594 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0 23754200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1 23999687 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu2 23392665 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu3 23767591 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu4 23830078 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu5 23955053 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu6 24298735 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu7 24178223 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2223628827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 2032452594 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0 424187889 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1 422540895 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2 416952722 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3 406133447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu4 412333106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu5 414872779 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu6 424571741 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu7 395622146 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5349667320 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 14607 # number of replacements system.l2c.tagsinuse 798.832185 # Cycle average of tags in use system.l2c.total_refs 150557 # Total number of references to valid blocks. system.l2c.sampled_refs 15432 # Sample count of references to valid blocks. system.l2c.avg_refs 9.756156 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 740.812109 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0 7.661361 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1 7.247095 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2 7.177515 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3 6.855610 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu4 7.321397 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu5 7.120032 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu6 7.753138 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu7 6.883928 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.723449 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0 0.007482 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1 0.007077 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2 0.007009 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy system.l2c.occ_percent::cpu4 0.007150 # Average percentage of cache occupancy system.l2c.occ_percent::cpu5 0.006953 # Average percentage of cache occupancy system.l2c.occ_percent::cpu6 0.007571 # Average percentage of cache occupancy system.l2c.occ_percent::cpu7 0.006723 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.780110 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0 10638 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1 10673 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3 10613 # number of ReadReq hits system.l2c.ReadReq_hits::cpu4 10754 # number of ReadReq hits system.l2c.ReadReq_hits::cpu5 10954 # number of ReadReq hits system.l2c.ReadReq_hits::cpu6 10851 # number of ReadReq hits system.l2c.ReadReq_hits::cpu7 10889 # number of ReadReq hits system.l2c.ReadReq_hits::total 86243 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 75632 # number of Writeback hits system.l2c.Writeback_hits::total 75632 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1 349 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2 360 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu3 350 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu4 332 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu5 339 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu6 326 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu7 357 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2743 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu0 1980 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1 1883 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu2 1924 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu3 2003 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu4 1977 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu5 1920 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu6 1982 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu7 1896 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 15565 # number of ReadExReq hits system.l2c.demand_hits::cpu0 12618 # number of demand (read+write) hits system.l2c.demand_hits::cpu1 12556 # number of demand (read+write) hits system.l2c.demand_hits::cpu2 12795 # number of demand (read+write) hits system.l2c.demand_hits::cpu3 12616 # number of demand (read+write) hits system.l2c.demand_hits::cpu4 12731 # number of demand (read+write) hits system.l2c.demand_hits::cpu5 12874 # number of demand (read+write) hits system.l2c.demand_hits::cpu6 12833 # number of demand (read+write) hits system.l2c.demand_hits::cpu7 12785 # number of demand (read+write) hits system.l2c.demand_hits::total 101808 # number of demand (read+write) hits system.l2c.overall_hits::cpu0 12618 # number of overall hits system.l2c.overall_hits::cpu1 12556 # number of overall hits system.l2c.overall_hits::cpu2 12795 # number of overall hits system.l2c.overall_hits::cpu3 12616 # number of overall hits system.l2c.overall_hits::cpu4 12731 # number of overall hits system.l2c.overall_hits::cpu5 12874 # number of overall hits system.l2c.overall_hits::cpu6 12833 # number of overall hits system.l2c.overall_hits::cpu7 12785 # number of overall hits system.l2c.overall_hits::total 101808 # number of overall hits system.l2c.ReadReq_misses::cpu0 834 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1 832 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2 822 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3 780 # number of ReadReq misses system.l2c.ReadReq_misses::cpu4 790 # number of ReadReq misses system.l2c.ReadReq_misses::cpu5 794 # number of ReadReq misses system.l2c.ReadReq_misses::cpu6 838 # number of ReadReq misses system.l2c.ReadReq_misses::cpu7 736 # number of ReadReq misses system.l2c.ReadReq_misses::total 6426 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0 1913 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1 1876 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2 1922 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu4 1999 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu5 1918 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu6 1887 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu7 1932 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 15459 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0 4394 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1 4308 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2 4316 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3 4354 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu4 4292 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu5 4292 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu6 4233 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu7 4328 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 34517 # number of ReadExReq misses system.l2c.demand_misses::cpu0 5228 # number of demand (read+write) misses system.l2c.demand_misses::cpu1 5140 # number of demand (read+write) misses system.l2c.demand_misses::cpu2 5138 # number of demand (read+write) misses system.l2c.demand_misses::cpu3 5134 # number of demand (read+write) misses system.l2c.demand_misses::cpu4 5082 # number of demand (read+write) misses system.l2c.demand_misses::cpu5 5086 # number of demand (read+write) misses system.l2c.demand_misses::cpu6 5071 # number of demand (read+write) misses system.l2c.demand_misses::cpu7 5064 # number of demand (read+write) misses system.l2c.demand_misses::total 40943 # number of demand (read+write) misses system.l2c.overall_misses::cpu0 5228 # number of overall misses system.l2c.overall_misses::cpu1 5140 # number of overall misses system.l2c.overall_misses::cpu2 5138 # number of overall misses system.l2c.overall_misses::cpu3 5134 # number of overall misses system.l2c.overall_misses::cpu4 5082 # number of overall misses system.l2c.overall_misses::cpu5 5086 # number of overall misses system.l2c.overall_misses::cpu6 5071 # number of overall misses system.l2c.overall_misses::cpu7 5064 # number of overall misses system.l2c.overall_misses::total 40943 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0 41350032 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1 41129977 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2 40786420 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3 38596362 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu4 39278271 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu5 39541044 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu6 41568753 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu7 36525760 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 318776619 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0 49804280 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1 51885731 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2 53676097 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu3 52486307 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu4 52437029 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu5 51272005 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu6 52254582 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu7 52654576 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 416470607 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0 219461654 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1 215283667 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2 215604529 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3 217440085 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu4 214512687 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu5 214479862 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu6 211622352 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu7 216182446 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 1724587282 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0 260811686 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1 256413644 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2 256390949 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3 256036447 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu4 253790958 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu5 254020906 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu6 253191105 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu7 252708206 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 2043363901 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0 260811686 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1 256413644 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2 256390949 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3 256036447 # number of overall miss cycles system.l2c.overall_miss_latency::cpu4 253790958 # number of overall miss cycles system.l2c.overall_miss_latency::cpu5 254020906 # number of overall miss cycles system.l2c.overall_miss_latency::cpu6 253191105 # number of overall miss cycles system.l2c.overall_miss_latency::cpu7 252708206 # number of overall miss cycles system.l2c.overall_miss_latency::total 2043363901 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0 11472 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1 11505 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2 11693 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3 11393 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu4 11544 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu5 11748 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu6 11689 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu7 11625 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 92669 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 75632 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 75632 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0 2243 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1 2225 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2 2282 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3 2362 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu4 2331 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu5 2257 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu6 2213 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 18202 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0 6374 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1 6191 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2 6240 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3 6357 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu4 6269 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu5 6212 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu6 6215 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu7 6224 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 50082 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0 17846 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1 17696 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2 17933 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3 17750 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu4 17813 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu5 17960 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu6 17904 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu7 17849 # number of demand (read+write) accesses system.l2c.demand_accesses::total 142751 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0 17846 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1 17696 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2 17933 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3 17750 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu4 17813 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu5 17960 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu6 17904 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu7 17849 # number of overall (read+write) accesses system.l2c.overall_accesses::total 142751 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0 0.072699 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1 0.072316 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2 0.070298 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3 0.068463 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu4 0.068434 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu5 0.067586 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu6 0.071691 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu7 0.063312 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.069344 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0 0.852876 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1 0.843146 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2 0.842244 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3 0.851820 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu4 0.857572 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu5 0.849801 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu6 0.852689 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu7 0.844037 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.849302 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0 0.689363 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1 0.695849 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2 0.691667 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3 0.684914 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu4 0.684639 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu5 0.690921 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu6 0.681094 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu7 0.695373 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.689210 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0 0.292951 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1 0.290461 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2 0.286511 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3 0.289239 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu4 0.285297 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu5 0.283185 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu6 0.283233 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu7 0.283713 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.286814 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0 0.292951 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1 0.290461 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2 0.286511 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3 0.289239 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu4 0.285297 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu5 0.283185 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu6 0.283233 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu7 0.283713 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.286814 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0 49580.374101 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1 49435.068510 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2 49618.515815 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3 49482.515385 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu4 49719.330380 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu5 49799.803526 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu6 49604.717184 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu7 49627.391304 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 49607.316993 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0 26034.647151 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1 27657.639126 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2 27927.209677 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu3 26086.633698 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu4 26231.630315 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu5 26732.015120 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu6 27691.882353 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu7 27253.921325 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 26940.332945 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0 49945.756486 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1 49972.996054 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2 49954.710148 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3 49940.304318 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu4 49979.656803 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu5 49972.008854 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu6 49993.468462 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu7 49949.733364 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 49963.417504 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0 49887.468630 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1 49885.922957 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2 49900.924290 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3 49870.753214 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu4 49939.188902 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu5 49945.125049 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu6 49929.225991 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu7 49902.884281 # average overall miss latency system.l2c.demand_avg_miss_latency::total 49907.527563 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0 49887.468630 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1 49885.922957 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2 49900.924290 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3 49870.753214 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu4 49939.188902 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu5 49945.125049 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu6 49929.225991 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu7 49902.884281 # average overall miss latency system.l2c.overall_avg_miss_latency::total 49907.527563 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 7115 # number of writebacks system.l2c.writebacks::total 7115 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0 22 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1 23 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2 22 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3 24 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu4 13 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu5 15 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu6 19 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu7 17 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 9 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 13 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu1 8 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 13 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 15 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu4 15 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 12 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 35 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1 31 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2 35 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3 39 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu4 28 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu5 24 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu6 23 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 29 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 35 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1 31 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2 35 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3 39 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu4 28 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu5 24 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu6 23 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 29 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 244 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0 812 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1 809 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2 800 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3 756 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu4 777 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu5 779 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu6 819 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu7 719 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 6271 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0 1913 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1 1872 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2 1921 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu3 2011 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu4 1998 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu5 1916 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu6 1887 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu7 1932 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 15450 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0 4381 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1 4300 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2 4303 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3 4339 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu4 4277 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu5 4283 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu7 4316 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 34428 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0 5193 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1 5109 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2 5103 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3 5095 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu4 5054 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu5 5062 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu6 5048 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu7 5035 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 40699 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0 5193 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1 5109 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2 5103 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3 5095 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu4 5054 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu5 5062 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu6 5048 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu7 5035 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 40699 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0 32483716 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1 32363556 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2 32004501 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3 30243000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu4 31083178 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu5 31162243 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu6 32763319 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu7 28723011 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 250826524 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76520708 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1 74880632 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76840756 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3 80440711 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79880909 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76600687 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu6 75440727 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77280682 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 617885812 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0 175203645 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1 171923291 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2 172082750 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3 173484044 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu4 171083248 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu5 171323717 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu6 169163499 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu7 172603062 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 1376867256 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0 207687361 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1 204286847 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2 204087251 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3 203727044 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu4 202166426 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu5 202485960 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu6 201926818 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu7 201326073 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 1627693780 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0 207687361 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1 204286847 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2 204087251 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3 203727044 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu4 202166426 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu5 202485960 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu6 201926818 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu7 201326073 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 1627693780 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 393605068 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397164440 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396084825 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 395564887 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 396845191 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 392884701 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 399924937 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 397605829 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 3169679878 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 212842079 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215082041 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 209602015 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 213002165 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213521784 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214681989 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217761849 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216562185 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 1713056107 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0 606447147 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1 612246481 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu2 605686840 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu3 608567052 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu4 610366975 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu5 607566690 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu6 617686786 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu7 614168014 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 4882735985 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070781 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070317 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068417 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066357 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067308 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066309 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu6 0.070066 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061849 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.067671 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852876 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841348 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841805 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851397 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.857143 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.848914 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.852689 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.844037 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.848808 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.687324 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.694557 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.689583 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.682555 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.682246 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689472 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680451 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.693445 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.687433 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.285105 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.285105 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40004.576355 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40004.395550 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40005.626250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40003.968254 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40004.090090 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.879332 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40004.052503 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39948.554937 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 39997.851060 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.370099 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40000.337607 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.393545 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.353555 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 39980.434935 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39979.481733 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 39979.187599 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.353002 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39992.609191 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 39991.701666 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39982.160698 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39991.343249 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 39982.494584 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40000.759411 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40000.867850 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40000.827382 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.441613 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 39992.658766 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.num_reads 98637 # number of read accesses completed system.cpu0.num_writes 53345 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed system.cpu0.l1c.replacements 22018 # number of replacements system.cpu0.l1c.tagsinuse 396.710521 # Cycle average of tags in use system.cpu0.l1c.total_refs 13223 # Total number of references to valid blocks. system.cpu0.l1c.sampled_refs 22420 # Sample count of references to valid blocks. system.cpu0.l1c.avg_refs 0.589786 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.l1c.occ_blocks::cpu0 396.710521 # Average occupied blocks per requestor system.cpu0.l1c.occ_percent::cpu0 0.774825 # Average percentage of cache occupancy system.cpu0.l1c.occ_percent::total 0.774825 # Average percentage of cache occupancy system.cpu0.l1c.ReadReq_hits::cpu0 8580 # number of ReadReq hits system.cpu0.l1c.ReadReq_hits::total 8580 # number of ReadReq hits system.cpu0.l1c.WriteReq_hits::cpu0 1119 # number of WriteReq hits system.cpu0.l1c.WriteReq_hits::total 1119 # number of WriteReq hits system.cpu0.l1c.demand_hits::cpu0 9699 # number of demand (read+write) hits system.cpu0.l1c.demand_hits::total 9699 # number of demand (read+write) hits system.cpu0.l1c.overall_hits::cpu0 9699 # number of overall hits system.cpu0.l1c.overall_hits::total 9699 # number of overall hits system.cpu0.l1c.ReadReq_misses::cpu0 35932 # number of ReadReq misses system.cpu0.l1c.ReadReq_misses::total 35932 # number of ReadReq misses system.cpu0.l1c.WriteReq_misses::cpu0 23215 # number of WriteReq misses system.cpu0.l1c.WriteReq_misses::total 23215 # number of WriteReq misses system.cpu0.l1c.demand_misses::cpu0 59147 # number of demand (read+write) misses system.cpu0.l1c.demand_misses::total 59147 # number of demand (read+write) misses system.cpu0.l1c.overall_misses::cpu0 59147 # number of overall misses system.cpu0.l1c.overall_misses::total 59147 # number of overall misses system.cpu0.l1c.ReadReq_miss_latency::cpu0 928213854 # number of ReadReq miss cycles system.cpu0.l1c.ReadReq_miss_latency::total 928213854 # number of ReadReq miss cycles system.cpu0.l1c.WriteReq_miss_latency::cpu0 888665457 # number of WriteReq miss cycles system.cpu0.l1c.WriteReq_miss_latency::total 888665457 # number of WriteReq miss cycles system.cpu0.l1c.demand_miss_latency::cpu0 1816879311 # number of demand (read+write) miss cycles system.cpu0.l1c.demand_miss_latency::total 1816879311 # number of demand (read+write) miss cycles system.cpu0.l1c.overall_miss_latency::cpu0 1816879311 # number of overall miss cycles system.cpu0.l1c.overall_miss_latency::total 1816879311 # number of overall miss cycles system.cpu0.l1c.ReadReq_accesses::cpu0 44512 # number of ReadReq accesses(hits+misses) system.cpu0.l1c.ReadReq_accesses::total 44512 # number of ReadReq accesses(hits+misses) system.cpu0.l1c.WriteReq_accesses::cpu0 24334 # number of WriteReq accesses(hits+misses) system.cpu0.l1c.WriteReq_accesses::total 24334 # number of WriteReq accesses(hits+misses) system.cpu0.l1c.demand_accesses::cpu0 68846 # number of demand (read+write) accesses system.cpu0.l1c.demand_accesses::total 68846 # number of demand (read+write) accesses system.cpu0.l1c.overall_accesses::cpu0 68846 # number of overall (read+write) accesses system.cpu0.l1c.overall_accesses::total 68846 # number of overall (read+write) accesses system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807243 # miss rate for ReadReq accesses system.cpu0.l1c.ReadReq_miss_rate::total 0.807243 # miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954015 # miss rate for WriteReq accesses system.cpu0.l1c.WriteReq_miss_rate::total 0.954015 # miss rate for WriteReq accesses system.cpu0.l1c.demand_miss_rate::cpu0 0.859120 # miss rate for demand accesses system.cpu0.l1c.demand_miss_rate::total 0.859120 # miss rate for demand accesses system.cpu0.l1c.overall_miss_rate::cpu0 0.859120 # miss rate for overall accesses system.cpu0.l1c.overall_miss_rate::total 0.859120 # miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 25832.512913 # average ReadReq miss latency system.cpu0.l1c.ReadReq_avg_miss_latency::total 25832.512913 # average ReadReq miss latency system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38279.795692 # average WriteReq miss latency system.cpu0.l1c.WriteReq_avg_miss_latency::total 38279.795692 # average WriteReq miss latency system.cpu0.l1c.demand_avg_miss_latency::cpu0 30718.029841 # average overall miss latency system.cpu0.l1c.demand_avg_miss_latency::total 30718.029841 # average overall miss latency system.cpu0.l1c.overall_avg_miss_latency::cpu0 30718.029841 # average overall miss latency system.cpu0.l1c.overall_avg_miss_latency::total 30718.029841 # average overall miss latency system.cpu0.l1c.blocked_cycles::no_mshrs 213519076 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.blocked::no_mshrs 67191 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3177.792800 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed system.cpu0.l1c.writebacks::writebacks 9668 # number of writebacks system.cpu0.l1c.writebacks::total 9668 # number of writebacks system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35932 # number of ReadReq MSHR misses system.cpu0.l1c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23215 # number of WriteReq MSHR misses system.cpu0.l1c.WriteReq_mshr_misses::total 23215 # number of WriteReq MSHR misses system.cpu0.l1c.demand_mshr_misses::cpu0 59147 # number of demand (read+write) MSHR misses system.cpu0.l1c.demand_mshr_misses::total 59147 # number of demand (read+write) MSHR misses system.cpu0.l1c.overall_mshr_misses::cpu0 59147 # number of overall MSHR misses system.cpu0.l1c.overall_mshr_misses::total 59147 # number of overall MSHR misses system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 892144080 # number of ReadReq MSHR miss cycles system.cpu0.l1c.ReadReq_mshr_miss_latency::total 892144080 # number of ReadReq MSHR miss cycles system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 865359572 # number of WriteReq MSHR miss cycles system.cpu0.l1c.WriteReq_mshr_miss_latency::total 865359572 # number of WriteReq MSHR miss cycles system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1757503652 # number of demand (read+write) MSHR miss cycles system.cpu0.l1c.demand_mshr_miss_latency::total 1757503652 # number of demand (read+write) MSHR miss cycles system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1757503652 # number of overall MSHR miss cycles system.cpu0.l1c.overall_mshr_miss_latency::total 1757503652 # number of overall MSHR miss cycles system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 897451639 # number of ReadReq MSHR uncacheable cycles system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 897451639 # number of ReadReq MSHR uncacheable cycles system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 561857596 # number of WriteReq MSHR uncacheable cycles system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 561857596 # number of WriteReq MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1459309235 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1459309235 # number of overall MSHR uncacheable cycles system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807243 # mshr miss rate for ReadReq accesses system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807243 # mshr miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954015 # mshr miss rate for WriteReq accesses system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954015 # mshr miss rate for WriteReq accesses system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for demand accesses system.cpu0.l1c.demand_mshr_miss_rate::total 0.859120 # mshr miss rate for demand accesses system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for overall accesses system.cpu0.l1c.overall_mshr_miss_rate::total 0.859120 # mshr miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24828.678615 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24828.678615 # average ReadReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37275.880767 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37275.880767 # average WriteReq mshr miss latency system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency system.cpu0.l1c.demand_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 99346 # number of read accesses completed system.cpu1.num_writes 53405 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed system.cpu1.l1c.replacements 21836 # number of replacements system.cpu1.l1c.tagsinuse 395.252412 # Cycle average of tags in use system.cpu1.l1c.total_refs 13010 # Total number of references to valid blocks. system.cpu1.l1c.sampled_refs 22258 # Sample count of references to valid blocks. system.cpu1.l1c.avg_refs 0.584509 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l1c.occ_blocks::cpu1 395.252412 # Average occupied blocks per requestor system.cpu1.l1c.occ_percent::cpu1 0.771977 # Average percentage of cache occupancy system.cpu1.l1c.occ_percent::total 0.771977 # Average percentage of cache occupancy system.cpu1.l1c.ReadReq_hits::cpu1 8468 # number of ReadReq hits system.cpu1.l1c.ReadReq_hits::total 8468 # number of ReadReq hits system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits system.cpu1.l1c.demand_hits::cpu1 9513 # number of demand (read+write) hits system.cpu1.l1c.demand_hits::total 9513 # number of demand (read+write) hits system.cpu1.l1c.overall_hits::cpu1 9513 # number of overall hits system.cpu1.l1c.overall_hits::total 9513 # number of overall hits system.cpu1.l1c.ReadReq_misses::cpu1 36170 # number of ReadReq misses system.cpu1.l1c.ReadReq_misses::total 36170 # number of ReadReq misses system.cpu1.l1c.WriteReq_misses::cpu1 22843 # number of WriteReq misses system.cpu1.l1c.WriteReq_misses::total 22843 # number of WriteReq misses system.cpu1.l1c.demand_misses::cpu1 59013 # number of demand (read+write) misses system.cpu1.l1c.demand_misses::total 59013 # number of demand (read+write) misses system.cpu1.l1c.overall_misses::cpu1 59013 # number of overall misses system.cpu1.l1c.overall_misses::total 59013 # number of overall misses system.cpu1.l1c.ReadReq_miss_latency::cpu1 930956991 # number of ReadReq miss cycles system.cpu1.l1c.ReadReq_miss_latency::total 930956991 # number of ReadReq miss cycles system.cpu1.l1c.WriteReq_miss_latency::cpu1 873445374 # number of WriteReq miss cycles system.cpu1.l1c.WriteReq_miss_latency::total 873445374 # number of WriteReq miss cycles system.cpu1.l1c.demand_miss_latency::cpu1 1804402365 # number of demand (read+write) miss cycles system.cpu1.l1c.demand_miss_latency::total 1804402365 # number of demand (read+write) miss cycles system.cpu1.l1c.overall_miss_latency::cpu1 1804402365 # number of overall miss cycles system.cpu1.l1c.overall_miss_latency::total 1804402365 # number of overall miss cycles system.cpu1.l1c.ReadReq_accesses::cpu1 44638 # number of ReadReq accesses(hits+misses) system.cpu1.l1c.ReadReq_accesses::total 44638 # number of ReadReq accesses(hits+misses) system.cpu1.l1c.WriteReq_accesses::cpu1 23888 # number of WriteReq accesses(hits+misses) system.cpu1.l1c.WriteReq_accesses::total 23888 # number of WriteReq accesses(hits+misses) system.cpu1.l1c.demand_accesses::cpu1 68526 # number of demand (read+write) accesses system.cpu1.l1c.demand_accesses::total 68526 # number of demand (read+write) accesses system.cpu1.l1c.overall_accesses::cpu1 68526 # number of overall (read+write) accesses system.cpu1.l1c.overall_accesses::total 68526 # number of overall (read+write) accesses system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.810296 # miss rate for ReadReq accesses system.cpu1.l1c.ReadReq_miss_rate::total 0.810296 # miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956254 # miss rate for WriteReq accesses system.cpu1.l1c.WriteReq_miss_rate::total 0.956254 # miss rate for WriteReq accesses system.cpu1.l1c.demand_miss_rate::cpu1 0.861177 # miss rate for demand accesses system.cpu1.l1c.demand_miss_rate::total 0.861177 # miss rate for demand accesses system.cpu1.l1c.overall_miss_rate::cpu1 0.861177 # miss rate for overall accesses system.cpu1.l1c.overall_miss_rate::total 0.861177 # miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 25738.374095 # average ReadReq miss latency system.cpu1.l1c.ReadReq_avg_miss_latency::total 25738.374095 # average ReadReq miss latency system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38236.894191 # average WriteReq miss latency system.cpu1.l1c.WriteReq_avg_miss_latency::total 38236.894191 # average WriteReq miss latency system.cpu1.l1c.demand_avg_miss_latency::cpu1 30576.353770 # average overall miss latency system.cpu1.l1c.demand_avg_miss_latency::total 30576.353770 # average overall miss latency system.cpu1.l1c.overall_avg_miss_latency::cpu1 30576.353770 # average overall miss latency system.cpu1.l1c.overall_avg_miss_latency::total 30576.353770 # average overall miss latency system.cpu1.l1c.blocked_cycles::no_mshrs 212850460 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.blocked::no_mshrs 67062 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3173.935463 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed system.cpu1.l1c.writebacks::writebacks 9414 # number of writebacks system.cpu1.l1c.writebacks::total 9414 # number of writebacks system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36170 # number of ReadReq MSHR misses system.cpu1.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22843 # number of WriteReq MSHR misses system.cpu1.l1c.WriteReq_mshr_misses::total 22843 # number of WriteReq MSHR misses system.cpu1.l1c.demand_mshr_misses::cpu1 59013 # number of demand (read+write) MSHR misses system.cpu1.l1c.demand_mshr_misses::total 59013 # number of demand (read+write) MSHR misses system.cpu1.l1c.overall_mshr_misses::cpu1 59013 # number of overall MSHR misses system.cpu1.l1c.overall_mshr_misses::total 59013 # number of overall MSHR misses system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 894646237 # number of ReadReq MSHR miss cycles system.cpu1.l1c.ReadReq_mshr_miss_latency::total 894646237 # number of ReadReq MSHR miss cycles system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 850514976 # number of WriteReq MSHR miss cycles system.cpu1.l1c.WriteReq_mshr_miss_latency::total 850514976 # number of WriteReq MSHR miss cycles system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1745161213 # number of demand (read+write) MSHR miss cycles system.cpu1.l1c.demand_mshr_miss_latency::total 1745161213 # number of demand (read+write) MSHR miss cycles system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1745161213 # number of overall MSHR miss cycles system.cpu1.l1c.overall_mshr_miss_latency::total 1745161213 # number of overall MSHR miss cycles system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 906808922 # number of ReadReq MSHR uncacheable cycles system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 906808922 # number of ReadReq MSHR uncacheable cycles system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 573615954 # number of WriteReq MSHR uncacheable cycles system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 573615954 # number of WriteReq MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480424876 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480424876 # number of overall MSHR uncacheable cycles system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.810296 # mshr miss rate for ReadReq accesses system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.810296 # mshr miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956254 # mshr miss rate for WriteReq accesses system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956254 # mshr miss rate for WriteReq accesses system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for demand accesses system.cpu1.l1c.demand_mshr_miss_rate::total 0.861177 # mshr miss rate for demand accesses system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for overall accesses system.cpu1.l1c.overall_mshr_miss_rate::total 0.861177 # mshr miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24734.482638 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24734.482638 # average ReadReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37233.068161 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37233.068161 # average WriteReq mshr miss latency system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency system.cpu1.l1c.demand_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.num_reads 99179 # number of read accesses completed system.cpu2.num_writes 53408 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed system.cpu2.l1c.replacements 21970 # number of replacements system.cpu2.l1c.tagsinuse 396.422513 # Cycle average of tags in use system.cpu2.l1c.total_refs 13458 # Total number of references to valid blocks. system.cpu2.l1c.sampled_refs 22394 # Sample count of references to valid blocks. system.cpu2.l1c.avg_refs 0.600965 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.l1c.occ_blocks::cpu2 396.422513 # Average occupied blocks per requestor system.cpu2.l1c.occ_percent::cpu2 0.774263 # Average percentage of cache occupancy system.cpu2.l1c.occ_percent::total 0.774263 # Average percentage of cache occupancy system.cpu2.l1c.ReadReq_hits::cpu2 8875 # number of ReadReq hits system.cpu2.l1c.ReadReq_hits::total 8875 # number of ReadReq hits system.cpu2.l1c.WriteReq_hits::cpu2 1083 # number of WriteReq hits system.cpu2.l1c.WriteReq_hits::total 1083 # number of WriteReq hits system.cpu2.l1c.demand_hits::cpu2 9958 # number of demand (read+write) hits system.cpu2.l1c.demand_hits::total 9958 # number of demand (read+write) hits system.cpu2.l1c.overall_hits::cpu2 9958 # number of overall hits system.cpu2.l1c.overall_hits::total 9958 # number of overall hits system.cpu2.l1c.ReadReq_misses::cpu2 35921 # number of ReadReq misses system.cpu2.l1c.ReadReq_misses::total 35921 # number of ReadReq misses system.cpu2.l1c.WriteReq_misses::cpu2 23014 # number of WriteReq misses system.cpu2.l1c.WriteReq_misses::total 23014 # number of WriteReq misses system.cpu2.l1c.demand_misses::cpu2 58935 # number of demand (read+write) misses system.cpu2.l1c.demand_misses::total 58935 # number of demand (read+write) misses system.cpu2.l1c.overall_misses::cpu2 58935 # number of overall misses system.cpu2.l1c.overall_misses::total 58935 # number of overall misses system.cpu2.l1c.ReadReq_miss_latency::cpu2 936514854 # number of ReadReq miss cycles system.cpu2.l1c.ReadReq_miss_latency::total 936514854 # number of ReadReq miss cycles system.cpu2.l1c.WriteReq_miss_latency::cpu2 882688372 # number of WriteReq miss cycles system.cpu2.l1c.WriteReq_miss_latency::total 882688372 # number of WriteReq miss cycles system.cpu2.l1c.demand_miss_latency::cpu2 1819203226 # number of demand (read+write) miss cycles system.cpu2.l1c.demand_miss_latency::total 1819203226 # number of demand (read+write) miss cycles system.cpu2.l1c.overall_miss_latency::cpu2 1819203226 # number of overall miss cycles system.cpu2.l1c.overall_miss_latency::total 1819203226 # number of overall miss cycles system.cpu2.l1c.ReadReq_accesses::cpu2 44796 # number of ReadReq accesses(hits+misses) system.cpu2.l1c.ReadReq_accesses::total 44796 # number of ReadReq accesses(hits+misses) system.cpu2.l1c.WriteReq_accesses::cpu2 24097 # number of WriteReq accesses(hits+misses) system.cpu2.l1c.WriteReq_accesses::total 24097 # number of WriteReq accesses(hits+misses) system.cpu2.l1c.demand_accesses::cpu2 68893 # number of demand (read+write) accesses system.cpu2.l1c.demand_accesses::total 68893 # number of demand (read+write) accesses system.cpu2.l1c.overall_accesses::cpu2 68893 # number of overall (read+write) accesses system.cpu2.l1c.overall_accesses::total 68893 # number of overall (read+write) accesses system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.801880 # miss rate for ReadReq accesses system.cpu2.l1c.ReadReq_miss_rate::total 0.801880 # miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955057 # miss rate for WriteReq accesses system.cpu2.l1c.WriteReq_miss_rate::total 0.955057 # miss rate for WriteReq accesses system.cpu2.l1c.demand_miss_rate::cpu2 0.855457 # miss rate for demand accesses system.cpu2.l1c.demand_miss_rate::total 0.855457 # miss rate for demand accesses system.cpu2.l1c.overall_miss_rate::cpu2 0.855457 # miss rate for overall accesses system.cpu2.l1c.overall_miss_rate::total 0.855457 # miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26071.513989 # average ReadReq miss latency system.cpu2.l1c.ReadReq_avg_miss_latency::total 26071.513989 # average ReadReq miss latency system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38354.409142 # average WriteReq miss latency system.cpu2.l1c.WriteReq_avg_miss_latency::total 38354.409142 # average WriteReq miss latency system.cpu2.l1c.demand_avg_miss_latency::cpu2 30867.960058 # average overall miss latency system.cpu2.l1c.demand_avg_miss_latency::total 30867.960058 # average overall miss latency system.cpu2.l1c.overall_avg_miss_latency::cpu2 30867.960058 # average overall miss latency system.cpu2.l1c.overall_avg_miss_latency::total 30867.960058 # average overall miss latency system.cpu2.l1c.blocked_cycles::no_mshrs 215347558 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.blocked::no_mshrs 67274 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3201.051788 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed system.cpu2.l1c.writebacks::writebacks 9572 # number of writebacks system.cpu2.l1c.writebacks::total 9572 # number of writebacks system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35921 # number of ReadReq MSHR misses system.cpu2.l1c.ReadReq_mshr_misses::total 35921 # number of ReadReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23014 # number of WriteReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::total 23014 # number of WriteReq MSHR misses system.cpu2.l1c.demand_mshr_misses::cpu2 58935 # number of demand (read+write) MSHR misses system.cpu2.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses system.cpu2.l1c.overall_mshr_misses::cpu2 58935 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 900454097 # number of ReadReq MSHR miss cycles system.cpu2.l1c.ReadReq_mshr_miss_latency::total 900454097 # number of ReadReq MSHR miss cycles system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 859588304 # number of WriteReq MSHR miss cycles system.cpu2.l1c.WriteReq_mshr_miss_latency::total 859588304 # number of WriteReq MSHR miss cycles system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1760042401 # number of demand (read+write) MSHR miss cycles system.cpu2.l1c.demand_mshr_miss_latency::total 1760042401 # number of demand (read+write) MSHR miss cycles system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1760042401 # number of overall MSHR miss cycles system.cpu2.l1c.overall_mshr_miss_latency::total 1760042401 # number of overall MSHR miss cycles system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 903394412 # number of ReadReq MSHR uncacheable cycles system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 903394412 # number of ReadReq MSHR uncacheable cycles system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 551786925 # number of WriteReq MSHR uncacheable cycles system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 551786925 # number of WriteReq MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1455181337 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1455181337 # number of overall MSHR uncacheable cycles system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.801880 # mshr miss rate for ReadReq accesses system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.801880 # mshr miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955057 # mshr miss rate for WriteReq accesses system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955057 # mshr miss rate for WriteReq accesses system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for demand accesses system.cpu2.l1c.demand_mshr_miss_rate::total 0.855457 # mshr miss rate for demand accesses system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for overall accesses system.cpu2.l1c.overall_mshr_miss_rate::total 0.855457 # mshr miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 25067.623312 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 25067.623312 # average ReadReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37350.669332 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37350.669332 # average WriteReq mshr miss latency system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency system.cpu2.l1c.demand_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.num_reads 98310 # number of read accesses completed system.cpu3.num_writes 53451 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed system.cpu3.l1c.replacements 21775 # number of replacements system.cpu3.l1c.tagsinuse 395.971374 # Cycle average of tags in use system.cpu3.l1c.total_refs 13179 # Total number of references to valid blocks. system.cpu3.l1c.sampled_refs 22179 # Sample count of references to valid blocks. system.cpu3.l1c.avg_refs 0.594211 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.l1c.occ_blocks::cpu3 395.971374 # Average occupied blocks per requestor system.cpu3.l1c.occ_percent::cpu3 0.773382 # Average percentage of cache occupancy system.cpu3.l1c.occ_percent::total 0.773382 # Average percentage of cache occupancy system.cpu3.l1c.ReadReq_hits::cpu3 8374 # number of ReadReq hits system.cpu3.l1c.ReadReq_hits::total 8374 # number of ReadReq hits system.cpu3.l1c.WriteReq_hits::cpu3 1100 # number of WriteReq hits system.cpu3.l1c.WriteReq_hits::total 1100 # number of WriteReq hits system.cpu3.l1c.demand_hits::cpu3 9474 # number of demand (read+write) hits system.cpu3.l1c.demand_hits::total 9474 # number of demand (read+write) hits system.cpu3.l1c.overall_hits::cpu3 9474 # number of overall hits system.cpu3.l1c.overall_hits::total 9474 # number of overall hits system.cpu3.l1c.ReadReq_misses::cpu3 35667 # number of ReadReq misses system.cpu3.l1c.ReadReq_misses::total 35667 # number of ReadReq misses system.cpu3.l1c.WriteReq_misses::cpu3 23305 # number of WriteReq misses system.cpu3.l1c.WriteReq_misses::total 23305 # number of WriteReq misses system.cpu3.l1c.demand_misses::cpu3 58972 # number of demand (read+write) misses system.cpu3.l1c.demand_misses::total 58972 # number of demand (read+write) misses system.cpu3.l1c.overall_misses::cpu3 58972 # number of overall misses system.cpu3.l1c.overall_misses::total 58972 # number of overall misses system.cpu3.l1c.ReadReq_miss_latency::cpu3 919630073 # number of ReadReq miss cycles system.cpu3.l1c.ReadReq_miss_latency::total 919630073 # number of ReadReq miss cycles system.cpu3.l1c.WriteReq_miss_latency::cpu3 893117472 # number of WriteReq miss cycles system.cpu3.l1c.WriteReq_miss_latency::total 893117472 # number of WriteReq miss cycles system.cpu3.l1c.demand_miss_latency::cpu3 1812747545 # number of demand (read+write) miss cycles system.cpu3.l1c.demand_miss_latency::total 1812747545 # number of demand (read+write) miss cycles system.cpu3.l1c.overall_miss_latency::cpu3 1812747545 # number of overall miss cycles system.cpu3.l1c.overall_miss_latency::total 1812747545 # number of overall miss cycles system.cpu3.l1c.ReadReq_accesses::cpu3 44041 # number of ReadReq accesses(hits+misses) system.cpu3.l1c.ReadReq_accesses::total 44041 # number of ReadReq accesses(hits+misses) system.cpu3.l1c.WriteReq_accesses::cpu3 24405 # number of WriteReq accesses(hits+misses) system.cpu3.l1c.WriteReq_accesses::total 24405 # number of WriteReq accesses(hits+misses) system.cpu3.l1c.demand_accesses::cpu3 68446 # number of demand (read+write) accesses system.cpu3.l1c.demand_accesses::total 68446 # number of demand (read+write) accesses system.cpu3.l1c.overall_accesses::cpu3 68446 # number of overall (read+write) accesses system.cpu3.l1c.overall_accesses::total 68446 # number of overall (read+write) accesses system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809859 # miss rate for ReadReq accesses system.cpu3.l1c.ReadReq_miss_rate::total 0.809859 # miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954927 # miss rate for WriteReq accesses system.cpu3.l1c.WriteReq_miss_rate::total 0.954927 # miss rate for WriteReq accesses system.cpu3.l1c.demand_miss_rate::cpu3 0.861584 # miss rate for demand accesses system.cpu3.l1c.demand_miss_rate::total 0.861584 # miss rate for demand accesses system.cpu3.l1c.overall_miss_rate::cpu3 0.861584 # miss rate for overall accesses system.cpu3.l1c.overall_miss_rate::total 0.861584 # miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 25783.779768 # average ReadReq miss latency system.cpu3.l1c.ReadReq_avg_miss_latency::total 25783.779768 # average ReadReq miss latency system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38322.998155 # average WriteReq miss latency system.cpu3.l1c.WriteReq_avg_miss_latency::total 38322.998155 # average WriteReq miss latency system.cpu3.l1c.demand_avg_miss_latency::cpu3 30739.122719 # average overall miss latency system.cpu3.l1c.demand_avg_miss_latency::total 30739.122719 # average overall miss latency system.cpu3.l1c.overall_avg_miss_latency::cpu3 30739.122719 # average overall miss latency system.cpu3.l1c.overall_avg_miss_latency::total 30739.122719 # average overall miss latency system.cpu3.l1c.blocked_cycles::no_mshrs 213693223 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.blocked::no_mshrs 67039 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3187.595623 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed system.cpu3.l1c.writebacks::writebacks 9546 # number of writebacks system.cpu3.l1c.writebacks::total 9546 # number of writebacks system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35667 # number of ReadReq MSHR misses system.cpu3.l1c.ReadReq_mshr_misses::total 35667 # number of ReadReq MSHR misses system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23305 # number of WriteReq MSHR misses system.cpu3.l1c.WriteReq_mshr_misses::total 23305 # number of WriteReq MSHR misses system.cpu3.l1c.demand_mshr_misses::cpu3 58972 # number of demand (read+write) MSHR misses system.cpu3.l1c.demand_mshr_misses::total 58972 # number of demand (read+write) MSHR misses system.cpu3.l1c.overall_mshr_misses::cpu3 58972 # number of overall MSHR misses system.cpu3.l1c.overall_mshr_misses::total 58972 # number of overall MSHR misses system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 883822339 # number of ReadReq MSHR miss cycles system.cpu3.l1c.ReadReq_mshr_miss_latency::total 883822339 # number of ReadReq MSHR miss cycles system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869724232 # number of WriteReq MSHR miss cycles system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869724232 # number of WriteReq MSHR miss cycles system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1753546571 # number of demand (read+write) MSHR miss cycles system.cpu3.l1c.demand_mshr_miss_latency::total 1753546571 # number of demand (read+write) MSHR miss cycles system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1753546571 # number of overall MSHR miss cycles system.cpu3.l1c.overall_mshr_miss_latency::total 1753546571 # number of overall MSHR miss cycles system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 901886993 # number of ReadReq MSHR uncacheable cycles system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 901886993 # number of ReadReq MSHR uncacheable cycles system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 561139437 # number of WriteReq MSHR uncacheable cycles system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 561139437 # number of WriteReq MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1463026430 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1463026430 # number of overall MSHR uncacheable cycles system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809859 # mshr miss rate for ReadReq accesses system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809859 # mshr miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954927 # mshr miss rate for WriteReq accesses system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954927 # mshr miss rate for WriteReq accesses system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for demand accesses system.cpu3.l1c.demand_mshr_miss_rate::total 0.861584 # mshr miss rate for demand accesses system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for overall accesses system.cpu3.l1c.overall_mshr_miss_rate::total 0.861584 # mshr miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24779.833992 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24779.833992 # average ReadReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37319.211843 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37319.211843 # average WriteReq mshr miss latency system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency system.cpu3.l1c.demand_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 100000 # number of read accesses completed system.cpu4.num_writes 53697 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed system.cpu4.l1c.replacements 22069 # number of replacements system.cpu4.l1c.tagsinuse 396.565187 # Cycle average of tags in use system.cpu4.l1c.total_refs 13244 # Total number of references to valid blocks. system.cpu4.l1c.sampled_refs 22489 # Sample count of references to valid blocks. system.cpu4.l1c.avg_refs 0.588910 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu4.l1c.occ_blocks::cpu4 396.565187 # Average occupied blocks per requestor system.cpu4.l1c.occ_percent::cpu4 0.774541 # Average percentage of cache occupancy system.cpu4.l1c.occ_percent::total 0.774541 # Average percentage of cache occupancy system.cpu4.l1c.ReadReq_hits::cpu4 8614 # number of ReadReq hits system.cpu4.l1c.ReadReq_hits::total 8614 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1053 # number of WriteReq hits system.cpu4.l1c.WriteReq_hits::total 1053 # number of WriteReq hits system.cpu4.l1c.demand_hits::cpu4 9667 # number of demand (read+write) hits system.cpu4.l1c.demand_hits::total 9667 # number of demand (read+write) hits system.cpu4.l1c.overall_hits::cpu4 9667 # number of overall hits system.cpu4.l1c.overall_hits::total 9667 # number of overall hits system.cpu4.l1c.ReadReq_misses::cpu4 36078 # number of ReadReq misses system.cpu4.l1c.ReadReq_misses::total 36078 # number of ReadReq misses system.cpu4.l1c.WriteReq_misses::cpu4 23045 # number of WriteReq misses system.cpu4.l1c.WriteReq_misses::total 23045 # number of WriteReq misses system.cpu4.l1c.demand_misses::cpu4 59123 # number of demand (read+write) misses system.cpu4.l1c.demand_misses::total 59123 # number of demand (read+write) misses system.cpu4.l1c.overall_misses::cpu4 59123 # number of overall misses system.cpu4.l1c.overall_misses::total 59123 # number of overall misses system.cpu4.l1c.ReadReq_miss_latency::cpu4 933502205 # number of ReadReq miss cycles system.cpu4.l1c.ReadReq_miss_latency::total 933502205 # number of ReadReq miss cycles system.cpu4.l1c.WriteReq_miss_latency::cpu4 883607398 # number of WriteReq miss cycles system.cpu4.l1c.WriteReq_miss_latency::total 883607398 # number of WriteReq miss cycles system.cpu4.l1c.demand_miss_latency::cpu4 1817109603 # number of demand (read+write) miss cycles system.cpu4.l1c.demand_miss_latency::total 1817109603 # number of demand (read+write) miss cycles system.cpu4.l1c.overall_miss_latency::cpu4 1817109603 # number of overall miss cycles system.cpu4.l1c.overall_miss_latency::total 1817109603 # number of overall miss cycles system.cpu4.l1c.ReadReq_accesses::cpu4 44692 # number of ReadReq accesses(hits+misses) system.cpu4.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) system.cpu4.l1c.WriteReq_accesses::cpu4 24098 # number of WriteReq accesses(hits+misses) system.cpu4.l1c.WriteReq_accesses::total 24098 # number of WriteReq accesses(hits+misses) system.cpu4.l1c.demand_accesses::cpu4 68790 # number of demand (read+write) accesses system.cpu4.l1c.demand_accesses::total 68790 # number of demand (read+write) accesses system.cpu4.l1c.overall_accesses::cpu4 68790 # number of overall (read+write) accesses system.cpu4.l1c.overall_accesses::total 68790 # number of overall (read+write) accesses system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807259 # miss rate for ReadReq accesses system.cpu4.l1c.ReadReq_miss_rate::total 0.807259 # miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956303 # miss rate for WriteReq accesses system.cpu4.l1c.WriteReq_miss_rate::total 0.956303 # miss rate for WriteReq accesses system.cpu4.l1c.demand_miss_rate::cpu4 0.859471 # miss rate for demand accesses system.cpu4.l1c.demand_miss_rate::total 0.859471 # miss rate for demand accesses system.cpu4.l1c.overall_miss_rate::cpu4 0.859471 # miss rate for overall accesses system.cpu4.l1c.overall_miss_rate::total 0.859471 # miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 25874.555269 # average ReadReq miss latency system.cpu4.l1c.ReadReq_avg_miss_latency::total 25874.555269 # average ReadReq miss latency system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38342.694641 # average WriteReq miss latency system.cpu4.l1c.WriteReq_avg_miss_latency::total 38342.694641 # average WriteReq miss latency system.cpu4.l1c.demand_avg_miss_latency::cpu4 30734.394449 # average overall miss latency system.cpu4.l1c.demand_avg_miss_latency::total 30734.394449 # average overall miss latency system.cpu4.l1c.overall_avg_miss_latency::cpu4 30734.394449 # average overall miss latency system.cpu4.l1c.overall_avg_miss_latency::total 30734.394449 # average overall miss latency system.cpu4.l1c.blocked_cycles::no_mshrs 213249503 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.blocked::no_mshrs 67264 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3170.336331 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed system.cpu4.l1c.writebacks::writebacks 9627 # number of writebacks system.cpu4.l1c.writebacks::total 9627 # number of writebacks system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36078 # number of ReadReq MSHR misses system.cpu4.l1c.ReadReq_mshr_misses::total 36078 # number of ReadReq MSHR misses system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23045 # number of WriteReq MSHR misses system.cpu4.l1c.WriteReq_mshr_misses::total 23045 # number of WriteReq MSHR misses system.cpu4.l1c.demand_mshr_misses::cpu4 59123 # number of demand (read+write) MSHR misses system.cpu4.l1c.demand_mshr_misses::total 59123 # number of demand (read+write) MSHR misses system.cpu4.l1c.overall_mshr_misses::cpu4 59123 # number of overall MSHR misses system.cpu4.l1c.overall_mshr_misses::total 59123 # number of overall MSHR misses system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 897285830 # number of ReadReq MSHR miss cycles system.cpu4.l1c.ReadReq_mshr_miss_latency::total 897285830 # number of ReadReq MSHR miss cycles system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 860474190 # number of WriteReq MSHR miss cycles system.cpu4.l1c.WriteReq_mshr_miss_latency::total 860474190 # number of WriteReq MSHR miss cycles system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1757760020 # number of demand (read+write) MSHR miss cycles system.cpu4.l1c.demand_mshr_miss_latency::total 1757760020 # number of demand (read+write) MSHR miss cycles system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1757760020 # number of overall MSHR miss cycles system.cpu4.l1c.overall_mshr_miss_latency::total 1757760020 # number of overall MSHR miss cycles system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 897898466 # number of ReadReq MSHR uncacheable cycles system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 897898466 # number of ReadReq MSHR uncacheable cycles system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 564390024 # number of WriteReq MSHR uncacheable cycles system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 564390024 # number of WriteReq MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1462288490 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1462288490 # number of overall MSHR uncacheable cycles system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807259 # mshr miss rate for ReadReq accesses system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807259 # mshr miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956303 # mshr miss rate for WriteReq accesses system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956303 # mshr miss rate for WriteReq accesses system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for demand accesses system.cpu4.l1c.demand_mshr_miss_rate::total 0.859471 # mshr miss rate for demand accesses system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for overall accesses system.cpu4.l1c.overall_mshr_miss_rate::total 0.859471 # mshr miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24870.719829 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24870.719829 # average ReadReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37338.866999 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37338.866999 # average WriteReq mshr miss latency system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency system.cpu4.l1c.demand_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu5.num_reads 98755 # number of read accesses completed system.cpu5.num_writes 53000 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed system.cpu5.l1c.replacements 21964 # number of replacements system.cpu5.l1c.tagsinuse 395.335157 # Cycle average of tags in use system.cpu5.l1c.total_refs 13162 # Total number of references to valid blocks. system.cpu5.l1c.sampled_refs 22364 # Sample count of references to valid blocks. system.cpu5.l1c.avg_refs 0.588535 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu5.l1c.occ_blocks::cpu5 395.335157 # Average occupied blocks per requestor system.cpu5.l1c.occ_percent::cpu5 0.772139 # Average percentage of cache occupancy system.cpu5.l1c.occ_percent::total 0.772139 # Average percentage of cache occupancy system.cpu5.l1c.ReadReq_hits::cpu5 8580 # number of ReadReq hits system.cpu5.l1c.ReadReq_hits::total 8580 # number of ReadReq hits system.cpu5.l1c.WriteReq_hits::cpu5 1063 # number of WriteReq hits system.cpu5.l1c.WriteReq_hits::total 1063 # number of WriteReq hits system.cpu5.l1c.demand_hits::cpu5 9643 # number of demand (read+write) hits system.cpu5.l1c.demand_hits::total 9643 # number of demand (read+write) hits system.cpu5.l1c.overall_hits::cpu5 9643 # number of overall hits system.cpu5.l1c.overall_hits::total 9643 # number of overall hits system.cpu5.l1c.ReadReq_misses::cpu5 36060 # number of ReadReq misses system.cpu5.l1c.ReadReq_misses::total 36060 # number of ReadReq misses system.cpu5.l1c.WriteReq_misses::cpu5 22989 # number of WriteReq misses system.cpu5.l1c.WriteReq_misses::total 22989 # number of WriteReq misses system.cpu5.l1c.demand_misses::cpu5 59049 # number of demand (read+write) misses system.cpu5.l1c.demand_misses::total 59049 # number of demand (read+write) misses system.cpu5.l1c.overall_misses::cpu5 59049 # number of overall misses system.cpu5.l1c.overall_misses::total 59049 # number of overall misses system.cpu5.l1c.ReadReq_miss_latency::cpu5 944228607 # number of ReadReq miss cycles system.cpu5.l1c.ReadReq_miss_latency::total 944228607 # number of ReadReq miss cycles system.cpu5.l1c.WriteReq_miss_latency::cpu5 875107262 # number of WriteReq miss cycles system.cpu5.l1c.WriteReq_miss_latency::total 875107262 # number of WriteReq miss cycles system.cpu5.l1c.demand_miss_latency::cpu5 1819335869 # number of demand (read+write) miss cycles system.cpu5.l1c.demand_miss_latency::total 1819335869 # number of demand (read+write) miss cycles system.cpu5.l1c.overall_miss_latency::cpu5 1819335869 # number of overall miss cycles system.cpu5.l1c.overall_miss_latency::total 1819335869 # number of overall miss cycles system.cpu5.l1c.ReadReq_accesses::cpu5 44640 # number of ReadReq accesses(hits+misses) system.cpu5.l1c.ReadReq_accesses::total 44640 # number of ReadReq accesses(hits+misses) system.cpu5.l1c.WriteReq_accesses::cpu5 24052 # number of WriteReq accesses(hits+misses) system.cpu5.l1c.WriteReq_accesses::total 24052 # number of WriteReq accesses(hits+misses) system.cpu5.l1c.demand_accesses::cpu5 68692 # number of demand (read+write) accesses system.cpu5.l1c.demand_accesses::total 68692 # number of demand (read+write) accesses system.cpu5.l1c.overall_accesses::cpu5 68692 # number of overall (read+write) accesses system.cpu5.l1c.overall_accesses::total 68692 # number of overall (read+write) accesses system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807796 # miss rate for ReadReq accesses system.cpu5.l1c.ReadReq_miss_rate::total 0.807796 # miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955804 # miss rate for WriteReq accesses system.cpu5.l1c.WriteReq_miss_rate::total 0.955804 # miss rate for WriteReq accesses system.cpu5.l1c.demand_miss_rate::cpu5 0.859620 # miss rate for demand accesses system.cpu5.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses system.cpu5.l1c.overall_miss_rate::cpu5 0.859620 # miss rate for overall accesses system.cpu5.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26184.930865 # average ReadReq miss latency system.cpu5.l1c.ReadReq_avg_miss_latency::total 26184.930865 # average ReadReq miss latency system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38066.347471 # average WriteReq miss latency system.cpu5.l1c.WriteReq_avg_miss_latency::total 38066.347471 # average WriteReq miss latency system.cpu5.l1c.demand_avg_miss_latency::cpu5 30810.612695 # average overall miss latency system.cpu5.l1c.demand_avg_miss_latency::total 30810.612695 # average overall miss latency system.cpu5.l1c.overall_avg_miss_latency::cpu5 30810.612695 # average overall miss latency system.cpu5.l1c.overall_avg_miss_latency::total 30810.612695 # average overall miss latency system.cpu5.l1c.blocked_cycles::no_mshrs 213071792 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.blocked::no_mshrs 67023 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3179.084672 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed system.cpu5.l1c.writebacks::writebacks 9605 # number of writebacks system.cpu5.l1c.writebacks::total 9605 # number of writebacks system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36060 # number of ReadReq MSHR misses system.cpu5.l1c.ReadReq_mshr_misses::total 36060 # number of ReadReq MSHR misses system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22989 # number of WriteReq MSHR misses system.cpu5.l1c.WriteReq_mshr_misses::total 22989 # number of WriteReq MSHR misses system.cpu5.l1c.demand_mshr_misses::cpu5 59049 # number of demand (read+write) MSHR misses system.cpu5.l1c.demand_mshr_misses::total 59049 # number of demand (read+write) MSHR misses system.cpu5.l1c.overall_mshr_misses::cpu5 59049 # number of overall MSHR misses system.cpu5.l1c.overall_mshr_misses::total 59049 # number of overall MSHR misses system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 908030320 # number of ReadReq MSHR miss cycles system.cpu5.l1c.ReadReq_mshr_miss_latency::total 908030320 # number of ReadReq MSHR miss cycles system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 852027269 # number of WriteReq MSHR miss cycles system.cpu5.l1c.WriteReq_mshr_miss_latency::total 852027269 # number of WriteReq MSHR miss cycles system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1760057589 # number of demand (read+write) MSHR miss cycles system.cpu5.l1c.demand_mshr_miss_latency::total 1760057589 # number of demand (read+write) MSHR miss cycles system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1760057589 # number of overall MSHR miss cycles system.cpu5.l1c.overall_mshr_miss_latency::total 1760057589 # number of overall MSHR miss cycles system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 893562759 # number of ReadReq MSHR uncacheable cycles system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 893562759 # number of ReadReq MSHR uncacheable cycles system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567489251 # number of WriteReq MSHR uncacheable cycles system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567489251 # number of WriteReq MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1461052010 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1461052010 # number of overall MSHR uncacheable cycles system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807796 # mshr miss rate for ReadReq accesses system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807796 # mshr miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955804 # mshr miss rate for WriteReq accesses system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955804 # mshr miss rate for WriteReq accesses system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for demand accesses system.cpu5.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for overall accesses system.cpu5.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 25181.095951 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 25181.095951 # average ReadReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37062.389360 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37062.389360 # average WriteReq mshr miss latency system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency system.cpu5.l1c.demand_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu6.num_reads 99515 # number of read accesses completed system.cpu6.num_writes 53091 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed system.cpu6.l1c.replacements 21875 # number of replacements system.cpu6.l1c.tagsinuse 395.073790 # Cycle average of tags in use system.cpu6.l1c.total_refs 13163 # Total number of references to valid blocks. system.cpu6.l1c.sampled_refs 22301 # Sample count of references to valid blocks. system.cpu6.l1c.avg_refs 0.590243 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu6.l1c.occ_blocks::cpu6 395.073790 # Average occupied blocks per requestor system.cpu6.l1c.occ_percent::cpu6 0.771628 # Average percentage of cache occupancy system.cpu6.l1c.occ_percent::total 0.771628 # Average percentage of cache occupancy system.cpu6.l1c.ReadReq_hits::cpu6 8660 # number of ReadReq hits system.cpu6.l1c.ReadReq_hits::total 8660 # number of ReadReq hits system.cpu6.l1c.WriteReq_hits::cpu6 1070 # number of WriteReq hits system.cpu6.l1c.WriteReq_hits::total 1070 # number of WriteReq hits system.cpu6.l1c.demand_hits::cpu6 9730 # number of demand (read+write) hits system.cpu6.l1c.demand_hits::total 9730 # number of demand (read+write) hits system.cpu6.l1c.overall_hits::cpu6 9730 # number of overall hits system.cpu6.l1c.overall_hits::total 9730 # number of overall hits system.cpu6.l1c.ReadReq_misses::cpu6 36079 # number of ReadReq misses system.cpu6.l1c.ReadReq_misses::total 36079 # number of ReadReq misses system.cpu6.l1c.WriteReq_misses::cpu6 22730 # number of WriteReq misses system.cpu6.l1c.WriteReq_misses::total 22730 # number of WriteReq misses system.cpu6.l1c.demand_misses::cpu6 58809 # number of demand (read+write) misses system.cpu6.l1c.demand_misses::total 58809 # number of demand (read+write) misses system.cpu6.l1c.overall_misses::cpu6 58809 # number of overall misses system.cpu6.l1c.overall_misses::total 58809 # number of overall misses system.cpu6.l1c.ReadReq_miss_latency::cpu6 942403765 # number of ReadReq miss cycles system.cpu6.l1c.ReadReq_miss_latency::total 942403765 # number of ReadReq miss cycles system.cpu6.l1c.WriteReq_miss_latency::cpu6 866225957 # number of WriteReq miss cycles system.cpu6.l1c.WriteReq_miss_latency::total 866225957 # number of WriteReq miss cycles system.cpu6.l1c.demand_miss_latency::cpu6 1808629722 # number of demand (read+write) miss cycles system.cpu6.l1c.demand_miss_latency::total 1808629722 # number of demand (read+write) miss cycles system.cpu6.l1c.overall_miss_latency::cpu6 1808629722 # number of overall miss cycles system.cpu6.l1c.overall_miss_latency::total 1808629722 # number of overall miss cycles system.cpu6.l1c.ReadReq_accesses::cpu6 44739 # number of ReadReq accesses(hits+misses) system.cpu6.l1c.ReadReq_accesses::total 44739 # number of ReadReq accesses(hits+misses) system.cpu6.l1c.WriteReq_accesses::cpu6 23800 # number of WriteReq accesses(hits+misses) system.cpu6.l1c.WriteReq_accesses::total 23800 # number of WriteReq accesses(hits+misses) system.cpu6.l1c.demand_accesses::cpu6 68539 # number of demand (read+write) accesses system.cpu6.l1c.demand_accesses::total 68539 # number of demand (read+write) accesses system.cpu6.l1c.overall_accesses::cpu6 68539 # number of overall (read+write) accesses system.cpu6.l1c.overall_accesses::total 68539 # number of overall (read+write) accesses system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806433 # miss rate for ReadReq accesses system.cpu6.l1c.ReadReq_miss_rate::total 0.806433 # miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955042 # miss rate for WriteReq accesses system.cpu6.l1c.WriteReq_miss_rate::total 0.955042 # miss rate for WriteReq accesses system.cpu6.l1c.demand_miss_rate::cpu6 0.858037 # miss rate for demand accesses system.cpu6.l1c.demand_miss_rate::total 0.858037 # miss rate for demand accesses system.cpu6.l1c.overall_miss_rate::cpu6 0.858037 # miss rate for overall accesses system.cpu6.l1c.overall_miss_rate::total 0.858037 # miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26120.562238 # average ReadReq miss latency system.cpu6.l1c.ReadReq_avg_miss_latency::total 26120.562238 # average ReadReq miss latency system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38109.368984 # average WriteReq miss latency system.cpu6.l1c.WriteReq_avg_miss_latency::total 38109.368984 # average WriteReq miss latency system.cpu6.l1c.demand_avg_miss_latency::cpu6 30754.301586 # average overall miss latency system.cpu6.l1c.demand_avg_miss_latency::total 30754.301586 # average overall miss latency system.cpu6.l1c.overall_avg_miss_latency::cpu6 30754.301586 # average overall miss latency system.cpu6.l1c.overall_avg_miss_latency::total 30754.301586 # average overall miss latency system.cpu6.l1c.blocked_cycles::no_mshrs 212806358 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.blocked::no_mshrs 66914 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3180.296470 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed system.cpu6.l1c.writebacks::writebacks 9438 # number of writebacks system.cpu6.l1c.writebacks::total 9438 # number of writebacks system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36079 # number of ReadReq MSHR misses system.cpu6.l1c.ReadReq_mshr_misses::total 36079 # number of ReadReq MSHR misses system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22730 # number of WriteReq MSHR misses system.cpu6.l1c.WriteReq_mshr_misses::total 22730 # number of WriteReq MSHR misses system.cpu6.l1c.demand_mshr_misses::cpu6 58809 # number of demand (read+write) MSHR misses system.cpu6.l1c.demand_mshr_misses::total 58809 # number of demand (read+write) MSHR misses system.cpu6.l1c.overall_mshr_misses::cpu6 58809 # number of overall MSHR misses system.cpu6.l1c.overall_mshr_misses::total 58809 # number of overall MSHR misses system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 906189412 # number of ReadReq MSHR miss cycles system.cpu6.l1c.ReadReq_mshr_miss_latency::total 906189412 # number of ReadReq MSHR miss cycles system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 843405989 # number of WriteReq MSHR miss cycles system.cpu6.l1c.WriteReq_mshr_miss_latency::total 843405989 # number of WriteReq MSHR miss cycles system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1749595401 # number of demand (read+write) MSHR miss cycles system.cpu6.l1c.demand_mshr_miss_latency::total 1749595401 # number of demand (read+write) MSHR miss cycles system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1749595401 # number of overall MSHR miss cycles system.cpu6.l1c.overall_mshr_miss_latency::total 1749595401 # number of overall MSHR miss cycles system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 905213986 # number of ReadReq MSHR uncacheable cycles system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 905213986 # number of ReadReq MSHR uncacheable cycles system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 576398345 # number of WriteReq MSHR uncacheable cycles system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 576398345 # number of WriteReq MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1481612331 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1481612331 # number of overall MSHR uncacheable cycles system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806433 # mshr miss rate for ReadReq accesses system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806433 # mshr miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955042 # mshr miss rate for WriteReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955042 # mshr miss rate for WriteReq accesses system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for demand accesses system.cpu6.l1c.demand_mshr_miss_rate::total 0.858037 # mshr miss rate for demand accesses system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for overall accesses system.cpu6.l1c.overall_mshr_miss_rate::total 0.858037 # mshr miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 25116.810665 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 25116.810665 # average ReadReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37105.410867 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37105.410867 # average WriteReq mshr miss latency system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency system.cpu6.l1c.demand_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu7.num_reads 98608 # number of read accesses completed system.cpu7.num_writes 53688 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed system.cpu7.l1c.replacements 21767 # number of replacements system.cpu7.l1c.tagsinuse 394.473547 # Cycle average of tags in use system.cpu7.l1c.total_refs 13199 # Total number of references to valid blocks. system.cpu7.l1c.sampled_refs 22171 # Sample count of references to valid blocks. system.cpu7.l1c.avg_refs 0.595327 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu7.l1c.occ_blocks::cpu7 394.473547 # Average occupied blocks per requestor system.cpu7.l1c.occ_percent::cpu7 0.770456 # Average percentage of cache occupancy system.cpu7.l1c.occ_percent::total 0.770456 # Average percentage of cache occupancy system.cpu7.l1c.ReadReq_hits::cpu7 8649 # number of ReadReq hits system.cpu7.l1c.ReadReq_hits::total 8649 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 995 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 995 # number of WriteReq hits system.cpu7.l1c.demand_hits::cpu7 9644 # number of demand (read+write) hits system.cpu7.l1c.demand_hits::total 9644 # number of demand (read+write) hits system.cpu7.l1c.overall_hits::cpu7 9644 # number of overall hits system.cpu7.l1c.overall_hits::total 9644 # number of overall hits system.cpu7.l1c.ReadReq_misses::cpu7 35884 # number of ReadReq misses system.cpu7.l1c.ReadReq_misses::total 35884 # number of ReadReq misses system.cpu7.l1c.WriteReq_misses::cpu7 23099 # number of WriteReq misses system.cpu7.l1c.WriteReq_misses::total 23099 # number of WriteReq misses system.cpu7.l1c.demand_misses::cpu7 58983 # number of demand (read+write) misses system.cpu7.l1c.demand_misses::total 58983 # number of demand (read+write) misses system.cpu7.l1c.overall_misses::cpu7 58983 # number of overall misses system.cpu7.l1c.overall_misses::total 58983 # number of overall misses system.cpu7.l1c.ReadReq_miss_latency::cpu7 932010776 # number of ReadReq miss cycles system.cpu7.l1c.ReadReq_miss_latency::total 932010776 # number of ReadReq miss cycles system.cpu7.l1c.WriteReq_miss_latency::cpu7 877703149 # number of WriteReq miss cycles system.cpu7.l1c.WriteReq_miss_latency::total 877703149 # number of WriteReq miss cycles system.cpu7.l1c.demand_miss_latency::cpu7 1809713925 # number of demand (read+write) miss cycles system.cpu7.l1c.demand_miss_latency::total 1809713925 # number of demand (read+write) miss cycles system.cpu7.l1c.overall_miss_latency::cpu7 1809713925 # number of overall miss cycles system.cpu7.l1c.overall_miss_latency::total 1809713925 # number of overall miss cycles system.cpu7.l1c.ReadReq_accesses::cpu7 44533 # number of ReadReq accesses(hits+misses) system.cpu7.l1c.ReadReq_accesses::total 44533 # number of ReadReq accesses(hits+misses) system.cpu7.l1c.WriteReq_accesses::cpu7 24094 # number of WriteReq accesses(hits+misses) system.cpu7.l1c.WriteReq_accesses::total 24094 # number of WriteReq accesses(hits+misses) system.cpu7.l1c.demand_accesses::cpu7 68627 # number of demand (read+write) accesses system.cpu7.l1c.demand_accesses::total 68627 # number of demand (read+write) accesses system.cpu7.l1c.overall_accesses::cpu7 68627 # number of overall (read+write) accesses system.cpu7.l1c.overall_accesses::total 68627 # number of overall (read+write) accesses system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805784 # miss rate for ReadReq accesses system.cpu7.l1c.ReadReq_miss_rate::total 0.805784 # miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.958703 # miss rate for WriteReq accesses system.cpu7.l1c.WriteReq_miss_rate::total 0.958703 # miss rate for WriteReq accesses system.cpu7.l1c.demand_miss_rate::cpu7 0.859472 # miss rate for demand accesses system.cpu7.l1c.demand_miss_rate::total 0.859472 # miss rate for demand accesses system.cpu7.l1c.overall_miss_rate::cpu7 0.859472 # miss rate for overall accesses system.cpu7.l1c.overall_miss_rate::total 0.859472 # miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25972.878609 # average ReadReq miss latency system.cpu7.l1c.ReadReq_avg_miss_latency::total 25972.878609 # average ReadReq miss latency system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37997.452227 # average WriteReq miss latency system.cpu7.l1c.WriteReq_avg_miss_latency::total 37997.452227 # average WriteReq miss latency system.cpu7.l1c.demand_avg_miss_latency::cpu7 30681.957937 # average overall miss latency system.cpu7.l1c.demand_avg_miss_latency::total 30681.957937 # average overall miss latency system.cpu7.l1c.overall_avg_miss_latency::cpu7 30681.957937 # average overall miss latency system.cpu7.l1c.overall_avg_miss_latency::total 30681.957937 # average overall miss latency system.cpu7.l1c.blocked_cycles::no_mshrs 213241981 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.blocked::no_mshrs 67091 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3178.399204 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed system.cpu7.l1c.writebacks::writebacks 9457 # number of writebacks system.cpu7.l1c.writebacks::total 9457 # number of writebacks system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35884 # number of ReadReq MSHR misses system.cpu7.l1c.ReadReq_mshr_misses::total 35884 # number of ReadReq MSHR misses system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23099 # number of WriteReq MSHR misses system.cpu7.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses system.cpu7.l1c.demand_mshr_misses::cpu7 58983 # number of demand (read+write) MSHR misses system.cpu7.l1c.demand_mshr_misses::total 58983 # number of demand (read+write) MSHR misses system.cpu7.l1c.overall_mshr_misses::cpu7 58983 # number of overall MSHR misses system.cpu7.l1c.overall_mshr_misses::total 58983 # number of overall MSHR misses system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 895990178 # number of ReadReq MSHR miss cycles system.cpu7.l1c.ReadReq_mshr_miss_latency::total 895990178 # number of ReadReq MSHR miss cycles system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 854514720 # number of WriteReq MSHR miss cycles system.cpu7.l1c.WriteReq_mshr_miss_latency::total 854514720 # number of WriteReq MSHR miss cycles system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1750504898 # number of demand (read+write) MSHR miss cycles system.cpu7.l1c.demand_mshr_miss_latency::total 1750504898 # number of demand (read+write) MSHR miss cycles system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1750504898 # number of overall MSHR miss cycles system.cpu7.l1c.overall_mshr_miss_latency::total 1750504898 # number of overall MSHR miss cycles system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 906836045 # number of ReadReq MSHR uncacheable cycles system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 906836045 # number of ReadReq MSHR uncacheable cycles system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 572746318 # number of WriteReq MSHR uncacheable cycles system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 572746318 # number of WriteReq MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1479582363 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1479582363 # number of overall MSHR uncacheable cycles system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805784 # mshr miss rate for ReadReq accesses system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805784 # mshr miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.958703 # mshr miss rate for WriteReq accesses system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.958703 # mshr miss rate for WriteReq accesses system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for demand accesses system.cpu7.l1c.demand_mshr_miss_rate::total 0.859472 # mshr miss rate for demand accesses system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for overall accesses system.cpu7.l1c.overall_mshr_miss_rate::total 0.859472 # mshr miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24969.071954 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24969.071954 # average ReadReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 36993.580674 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 36993.580674 # average WriteReq mshr miss latency system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency system.cpu7.l1c.demand_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------