---------- Begin Simulation Statistics ---------- sim_seconds 0.000502 # Number of seconds simulated sim_ticks 501584000 # Number of ticks simulated final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_tick_rate 112049096 # Simulator tick rate (ticks/s) host_mem_usage 235328 # Number of bytes of host memory used host_seconds 4.48 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory system.physmem.bytes_read::cpu1 79943 # Number of bytes read from this memory system.physmem.bytes_read::cpu2 80467 # Number of bytes read from this memory system.physmem.bytes_read::cpu3 80557 # Number of bytes read from this memory system.physmem.bytes_read::cpu4 77449 # Number of bytes read from this memory system.physmem.bytes_read::cpu5 81573 # Number of bytes read from this memory system.physmem.bytes_read::cpu6 79541 # Number of bytes read from this memory system.physmem.bytes_read::cpu7 76446 # Number of bytes read from this memory system.physmem.bytes_read::total 633149 # Number of bytes read from this memory system.physmem.bytes_written::writebacks 399616 # Number of bytes written to this memory system.physmem.bytes_written::cpu0 5376 # Number of bytes written to this memory system.physmem.bytes_written::cpu1 5525 # Number of bytes written to this memory system.physmem.bytes_written::cpu2 5482 # Number of bytes written to this memory system.physmem.bytes_written::cpu3 5537 # Number of bytes written to this memory system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory system.physmem.bytes_written::cpu5 5409 # Number of bytes written to this memory system.physmem.bytes_written::cpu6 5437 # Number of bytes written to this memory system.physmem.bytes_written::cpu7 5416 # Number of bytes written to this memory system.physmem.bytes_written::total 443294 # Number of bytes written to this memory system.physmem.num_reads::cpu0 10960 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1 10958 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2 11104 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3 10879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu4 10858 # Number of read requests responded to by this memory system.physmem.num_reads::cpu5 10887 # Number of read requests responded to by this memory system.physmem.num_reads::cpu6 10871 # Number of read requests responded to by this memory system.physmem.num_reads::cpu7 10989 # Number of read requests responded to by this memory system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 6244 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0 5376 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1 5525 # Number of write requests responded to by this memory system.physmem.num_writes::cpu2 5482 # Number of write requests responded to by this memory system.physmem.num_writes::cpu3 5537 # Number of write requests responded to by this memory system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory system.physmem.num_writes::cpu5 5409 # Number of write requests responded to by this memory system.physmem.num_writes::cpu6 5437 # Number of write requests responded to by this memory system.physmem.num_writes::cpu7 5416 # Number of write requests responded to by this memory system.physmem.num_writes::total 49922 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0 153858576 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1 159381081 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2 160425771 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3 160605203 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu4 154408833 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu5 162630786 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu6 158579620 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu7 152409168 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1262299037 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 796708029 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0 10718045 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1 11015104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu2 10929376 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu3 11039028 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu4 10957287 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu5 10783837 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu6 10839660 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu7 10797793 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 883788159 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 796708029 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0 164576621 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1 170396185 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2 171355147 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3 171644231 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu4 165366120 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu5 173414622 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu6 169419280 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu7 163206960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2146087196 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.num_reads 99682 # number of read accesses completed system.cpu0.num_writes 55240 # number of write accesses completed system.cpu0.l1c.tags.replacements 22392 # number of replacements system.cpu0.l1c.tags.tagsinuse 393.390751 # Cycle average of tags in use system.cpu0.l1c.tags.total_refs 13565 # Total number of references to valid blocks. system.cpu0.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. system.cpu0.l1c.tags.avg_refs 0.595348 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.l1c.tags.occ_blocks::cpu0 393.390751 # Average occupied blocks per requestor system.cpu0.l1c.tags.occ_percent::cpu0 0.768341 # Average percentage of cache occupancy system.cpu0.l1c.tags.occ_percent::total 0.768341 # Average percentage of cache occupancy system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id system.cpu0.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id system.cpu0.l1c.tags.tag_accesses 339133 # Number of tag accesses system.cpu0.l1c.tags.data_accesses 339133 # Number of data accesses system.cpu0.l1c.ReadReq_hits::cpu0 8847 # number of ReadReq hits system.cpu0.l1c.ReadReq_hits::total 8847 # number of ReadReq hits system.cpu0.l1c.WriteReq_hits::cpu0 1120 # number of WriteReq hits system.cpu0.l1c.WriteReq_hits::total 1120 # number of WriteReq hits system.cpu0.l1c.demand_hits::cpu0 9967 # number of demand (read+write) hits system.cpu0.l1c.demand_hits::total 9967 # number of demand (read+write) hits system.cpu0.l1c.overall_hits::cpu0 9967 # number of overall hits system.cpu0.l1c.overall_hits::total 9967 # number of overall hits system.cpu0.l1c.ReadReq_misses::cpu0 36618 # number of ReadReq misses system.cpu0.l1c.ReadReq_misses::total 36618 # number of ReadReq misses system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses system.cpu0.l1c.demand_misses::cpu0 60587 # number of demand (read+write) misses system.cpu0.l1c.demand_misses::total 60587 # number of demand (read+write) misses system.cpu0.l1c.overall_misses::cpu0 60587 # number of overall misses system.cpu0.l1c.overall_misses::total 60587 # number of overall misses system.cpu0.l1c.ReadReq_miss_latency::cpu0 672506192 # number of ReadReq miss cycles system.cpu0.l1c.ReadReq_miss_latency::total 672506192 # number of ReadReq miss cycles system.cpu0.l1c.WriteReq_miss_latency::cpu0 563028530 # number of WriteReq miss cycles system.cpu0.l1c.WriteReq_miss_latency::total 563028530 # number of WriteReq miss cycles system.cpu0.l1c.demand_miss_latency::cpu0 1235534722 # number of demand (read+write) miss cycles system.cpu0.l1c.demand_miss_latency::total 1235534722 # number of demand (read+write) miss cycles system.cpu0.l1c.overall_miss_latency::cpu0 1235534722 # number of overall miss cycles system.cpu0.l1c.overall_miss_latency::total 1235534722 # number of overall miss cycles system.cpu0.l1c.ReadReq_accesses::cpu0 45465 # number of ReadReq accesses(hits+misses) system.cpu0.l1c.ReadReq_accesses::total 45465 # number of ReadReq accesses(hits+misses) system.cpu0.l1c.WriteReq_accesses::cpu0 25089 # number of WriteReq accesses(hits+misses) system.cpu0.l1c.WriteReq_accesses::total 25089 # number of WriteReq accesses(hits+misses) system.cpu0.l1c.demand_accesses::cpu0 70554 # number of demand (read+write) accesses system.cpu0.l1c.demand_accesses::total 70554 # number of demand (read+write) accesses system.cpu0.l1c.overall_accesses::cpu0 70554 # number of overall (read+write) accesses system.cpu0.l1c.overall_accesses::total 70554 # number of overall (read+write) accesses system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805411 # miss rate for ReadReq accesses system.cpu0.l1c.ReadReq_miss_rate::total 0.805411 # miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955359 # miss rate for WriteReq accesses system.cpu0.l1c.WriteReq_miss_rate::total 0.955359 # miss rate for WriteReq accesses system.cpu0.l1c.demand_miss_rate::cpu0 0.858732 # miss rate for demand accesses system.cpu0.l1c.demand_miss_rate::total 0.858732 # miss rate for demand accesses system.cpu0.l1c.overall_miss_rate::cpu0 0.858732 # miss rate for overall accesses system.cpu0.l1c.overall_miss_rate::total 0.858732 # miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18365.453930 # average ReadReq miss latency system.cpu0.l1c.ReadReq_avg_miss_latency::total 18365.453930 # average ReadReq miss latency system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23489.863157 # average WriteReq miss latency system.cpu0.l1c.WriteReq_avg_miss_latency::total 23489.863157 # average WriteReq miss latency system.cpu0.l1c.demand_avg_miss_latency::cpu0 20392.736429 # average overall miss latency system.cpu0.l1c.demand_avg_miss_latency::total 20392.736429 # average overall miss latency system.cpu0.l1c.overall_avg_miss_latency::cpu0 20392.736429 # average overall miss latency system.cpu0.l1c.overall_avg_miss_latency::total 20392.736429 # average overall miss latency system.cpu0.l1c.blocked_cycles::no_mshrs 823442 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.blocked::no_mshrs 66357 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.409271 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.writebacks::writebacks 9844 # number of writebacks system.cpu0.l1c.writebacks::total 9844 # number of writebacks system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36618 # number of ReadReq MSHR misses system.cpu0.l1c.ReadReq_mshr_misses::total 36618 # number of ReadReq MSHR misses system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses system.cpu0.l1c.demand_mshr_misses::cpu0 60587 # number of demand (read+write) MSHR misses system.cpu0.l1c.demand_mshr_misses::total 60587 # number of demand (read+write) MSHR misses system.cpu0.l1c.overall_mshr_misses::cpu0 60587 # number of overall MSHR misses system.cpu0.l1c.overall_mshr_misses::total 60587 # number of overall MSHR misses system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9910 # number of ReadReq MSHR uncacheable system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5376 # number of WriteReq MSHR uncacheable system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15286 # number of overall MSHR uncacheable misses system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 635888192 # number of ReadReq MSHR miss cycles system.cpu0.l1c.ReadReq_mshr_miss_latency::total 635888192 # number of ReadReq MSHR miss cycles system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 539061530 # number of WriteReq MSHR miss cycles system.cpu0.l1c.WriteReq_mshr_miss_latency::total 539061530 # number of WriteReq MSHR miss cycles system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1174949722 # number of demand (read+write) MSHR miss cycles system.cpu0.l1c.demand_mshr_miss_latency::total 1174949722 # number of demand (read+write) MSHR miss cycles system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1174949722 # number of overall MSHR miss cycles system.cpu0.l1c.overall_mshr_miss_latency::total 1174949722 # number of overall MSHR miss cycles system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 753971133 # number of ReadReq MSHR uncacheable cycles system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 753971133 # number of ReadReq MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 753971133 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_latency::total 753971133 # number of overall MSHR uncacheable cycles system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805411 # mshr miss rate for ReadReq accesses system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805411 # mshr miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955359 # mshr miss rate for WriteReq accesses system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955359 # mshr miss rate for WriteReq accesses system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for demand accesses system.cpu0.l1c.demand_mshr_miss_rate::total 0.858732 # mshr miss rate for demand accesses system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for overall accesses system.cpu0.l1c.overall_mshr_miss_rate::total 0.858732 # mshr miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17365.453930 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17365.453930 # average ReadReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22489.946598 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22489.946598 # average WriteReq mshr miss latency system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 76081.849950 # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76081.849950 # average ReadReq mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 49324.292359 # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 49324.292359 # average overall mshr uncacheable latency system.cpu1.num_reads 99541 # number of read accesses completed system.cpu1.num_writes 55028 # number of write accesses completed system.cpu1.l1c.tags.replacements 22314 # number of replacements system.cpu1.l1c.tags.tagsinuse 393.210618 # Cycle average of tags in use system.cpu1.l1c.tags.total_refs 13573 # Total number of references to valid blocks. system.cpu1.l1c.tags.sampled_refs 22722 # Sample count of references to valid blocks. system.cpu1.l1c.tags.avg_refs 0.597351 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l1c.tags.occ_blocks::cpu1 393.210618 # Average occupied blocks per requestor system.cpu1.l1c.tags.occ_percent::cpu1 0.767989 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_percent::total 0.767989 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id system.cpu1.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id system.cpu1.l1c.tags.tag_accesses 338638 # Number of tag accesses system.cpu1.l1c.tags.data_accesses 338638 # Number of data accesses system.cpu1.l1c.ReadReq_hits::cpu1 8704 # number of ReadReq hits system.cpu1.l1c.ReadReq_hits::total 8704 # number of ReadReq hits system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits system.cpu1.l1c.demand_hits::cpu1 9853 # number of demand (read+write) hits system.cpu1.l1c.demand_hits::total 9853 # number of demand (read+write) hits system.cpu1.l1c.overall_hits::cpu1 9853 # number of overall hits system.cpu1.l1c.overall_hits::total 9853 # number of overall hits system.cpu1.l1c.ReadReq_misses::cpu1 36652 # number of ReadReq misses system.cpu1.l1c.ReadReq_misses::total 36652 # number of ReadReq misses system.cpu1.l1c.WriteReq_misses::cpu1 23946 # number of WriteReq misses system.cpu1.l1c.WriteReq_misses::total 23946 # number of WriteReq misses system.cpu1.l1c.demand_misses::cpu1 60598 # number of demand (read+write) misses system.cpu1.l1c.demand_misses::total 60598 # number of demand (read+write) misses system.cpu1.l1c.overall_misses::cpu1 60598 # number of overall misses system.cpu1.l1c.overall_misses::total 60598 # number of overall misses system.cpu1.l1c.ReadReq_miss_latency::cpu1 672762640 # number of ReadReq miss cycles system.cpu1.l1c.ReadReq_miss_latency::total 672762640 # number of ReadReq miss cycles system.cpu1.l1c.WriteReq_miss_latency::cpu1 564762705 # number of WriteReq miss cycles system.cpu1.l1c.WriteReq_miss_latency::total 564762705 # number of WriteReq miss cycles system.cpu1.l1c.demand_miss_latency::cpu1 1237525345 # number of demand (read+write) miss cycles system.cpu1.l1c.demand_miss_latency::total 1237525345 # number of demand (read+write) miss cycles system.cpu1.l1c.overall_miss_latency::cpu1 1237525345 # number of overall miss cycles system.cpu1.l1c.overall_miss_latency::total 1237525345 # number of overall miss cycles system.cpu1.l1c.ReadReq_accesses::cpu1 45356 # number of ReadReq accesses(hits+misses) system.cpu1.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) system.cpu1.l1c.WriteReq_accesses::cpu1 25095 # number of WriteReq accesses(hits+misses) system.cpu1.l1c.WriteReq_accesses::total 25095 # number of WriteReq accesses(hits+misses) system.cpu1.l1c.demand_accesses::cpu1 70451 # number of demand (read+write) accesses system.cpu1.l1c.demand_accesses::total 70451 # number of demand (read+write) accesses system.cpu1.l1c.overall_accesses::cpu1 70451 # number of overall (read+write) accesses system.cpu1.l1c.overall_accesses::total 70451 # number of overall (read+write) accesses system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808096 # miss rate for ReadReq accesses system.cpu1.l1c.ReadReq_miss_rate::total 0.808096 # miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954214 # miss rate for WriteReq accesses system.cpu1.l1c.WriteReq_miss_rate::total 0.954214 # miss rate for WriteReq accesses system.cpu1.l1c.demand_miss_rate::cpu1 0.860144 # miss rate for demand accesses system.cpu1.l1c.demand_miss_rate::total 0.860144 # miss rate for demand accesses system.cpu1.l1c.overall_miss_rate::cpu1 0.860144 # miss rate for overall accesses system.cpu1.l1c.overall_miss_rate::total 0.860144 # miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18355.414166 # average ReadReq miss latency system.cpu1.l1c.ReadReq_avg_miss_latency::total 18355.414166 # average ReadReq miss latency system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23584.845277 # average WriteReq miss latency system.cpu1.l1c.WriteReq_avg_miss_latency::total 23584.845277 # average WriteReq miss latency system.cpu1.l1c.demand_avg_miss_latency::cpu1 20421.884303 # average overall miss latency system.cpu1.l1c.demand_avg_miss_latency::total 20421.884303 # average overall miss latency system.cpu1.l1c.overall_avg_miss_latency::cpu1 20421.884303 # average overall miss latency system.cpu1.l1c.overall_avg_miss_latency::total 20421.884303 # average overall miss latency system.cpu1.l1c.blocked_cycles::no_mshrs 822356 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.429994 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.writebacks::writebacks 9894 # number of writebacks system.cpu1.l1c.writebacks::total 9894 # number of writebacks system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36652 # number of ReadReq MSHR misses system.cpu1.l1c.ReadReq_mshr_misses::total 36652 # number of ReadReq MSHR misses system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23946 # number of WriteReq MSHR misses system.cpu1.l1c.WriteReq_mshr_misses::total 23946 # number of WriteReq MSHR misses system.cpu1.l1c.demand_mshr_misses::cpu1 60598 # number of demand (read+write) MSHR misses system.cpu1.l1c.demand_mshr_misses::total 60598 # number of demand (read+write) MSHR misses system.cpu1.l1c.overall_mshr_misses::cpu1 60598 # number of overall MSHR misses system.cpu1.l1c.overall_mshr_misses::total 60598 # number of overall MSHR misses system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9864 # number of ReadReq MSHR uncacheable system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9864 # number of ReadReq MSHR uncacheable system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5527 # number of WriteReq MSHR uncacheable system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5527 # number of WriteReq MSHR uncacheable system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15391 # number of overall MSHR uncacheable misses system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15391 # number of overall MSHR uncacheable misses system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 636111640 # number of ReadReq MSHR miss cycles system.cpu1.l1c.ReadReq_mshr_miss_latency::total 636111640 # number of ReadReq MSHR miss cycles system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 540817705 # number of WriteReq MSHR miss cycles system.cpu1.l1c.WriteReq_mshr_miss_latency::total 540817705 # number of WriteReq MSHR miss cycles system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1176929345 # number of demand (read+write) MSHR miss cycles system.cpu1.l1c.demand_mshr_miss_latency::total 1176929345 # number of demand (read+write) MSHR miss cycles system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1176929345 # number of overall MSHR miss cycles system.cpu1.l1c.overall_mshr_miss_latency::total 1176929345 # number of overall MSHR miss cycles system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 750538193 # number of ReadReq MSHR uncacheable cycles system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 750538193 # number of ReadReq MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 750538193 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_latency::total 750538193 # number of overall MSHR uncacheable cycles system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808096 # mshr miss rate for ReadReq accesses system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808096 # mshr miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954214 # mshr miss rate for WriteReq accesses system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954214 # mshr miss rate for WriteReq accesses system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for demand accesses system.cpu1.l1c.demand_mshr_miss_rate::total 0.860144 # mshr miss rate for demand accesses system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for overall accesses system.cpu1.l1c.overall_mshr_miss_rate::total 0.860144 # mshr miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17355.441449 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17355.441449 # average ReadReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22584.887038 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22584.887038 # average WriteReq mshr miss latency system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 76088.624594 # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76088.624594 # average ReadReq mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48764.745176 # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48764.745176 # average overall mshr uncacheable latency system.cpu2.num_reads 99993 # number of read accesses completed system.cpu2.num_writes 55211 # number of write accesses completed system.cpu2.l1c.tags.replacements 22333 # number of replacements system.cpu2.l1c.tags.tagsinuse 392.533782 # Cycle average of tags in use system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. system.cpu2.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. system.cpu2.l1c.tags.avg_refs 0.595509 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.l1c.tags.occ_blocks::cpu2 392.533782 # Average occupied blocks per requestor system.cpu2.l1c.tags.occ_percent::cpu2 0.766668 # Average percentage of cache occupancy system.cpu2.l1c.tags.occ_percent::total 0.766668 # Average percentage of cache occupancy system.cpu2.l1c.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id system.cpu2.l1c.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id system.cpu2.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu2.l1c.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id system.cpu2.l1c.tags.tag_accesses 338842 # Number of tag accesses system.cpu2.l1c.tags.data_accesses 338842 # Number of data accesses system.cpu2.l1c.ReadReq_hits::cpu2 8700 # number of ReadReq hits system.cpu2.l1c.ReadReq_hits::total 8700 # number of ReadReq hits system.cpu2.l1c.WriteReq_hits::cpu2 1131 # number of WriteReq hits system.cpu2.l1c.WriteReq_hits::total 1131 # number of WriteReq hits system.cpu2.l1c.demand_hits::cpu2 9831 # number of demand (read+write) hits system.cpu2.l1c.demand_hits::total 9831 # number of demand (read+write) hits system.cpu2.l1c.overall_hits::cpu2 9831 # number of overall hits system.cpu2.l1c.overall_hits::total 9831 # number of overall hits system.cpu2.l1c.ReadReq_misses::cpu2 36743 # number of ReadReq misses system.cpu2.l1c.ReadReq_misses::total 36743 # number of ReadReq misses system.cpu2.l1c.WriteReq_misses::cpu2 23917 # number of WriteReq misses system.cpu2.l1c.WriteReq_misses::total 23917 # number of WriteReq misses system.cpu2.l1c.demand_misses::cpu2 60660 # number of demand (read+write) misses system.cpu2.l1c.demand_misses::total 60660 # number of demand (read+write) misses system.cpu2.l1c.overall_misses::cpu2 60660 # number of overall misses system.cpu2.l1c.overall_misses::total 60660 # number of overall misses system.cpu2.l1c.ReadReq_miss_latency::cpu2 667892138 # number of ReadReq miss cycles system.cpu2.l1c.ReadReq_miss_latency::total 667892138 # number of ReadReq miss cycles system.cpu2.l1c.WriteReq_miss_latency::cpu2 561829218 # number of WriteReq miss cycles system.cpu2.l1c.WriteReq_miss_latency::total 561829218 # number of WriteReq miss cycles system.cpu2.l1c.demand_miss_latency::cpu2 1229721356 # number of demand (read+write) miss cycles system.cpu2.l1c.demand_miss_latency::total 1229721356 # number of demand (read+write) miss cycles system.cpu2.l1c.overall_miss_latency::cpu2 1229721356 # number of overall miss cycles system.cpu2.l1c.overall_miss_latency::total 1229721356 # number of overall miss cycles system.cpu2.l1c.ReadReq_accesses::cpu2 45443 # number of ReadReq accesses(hits+misses) system.cpu2.l1c.ReadReq_accesses::total 45443 # number of ReadReq accesses(hits+misses) system.cpu2.l1c.WriteReq_accesses::cpu2 25048 # number of WriteReq accesses(hits+misses) system.cpu2.l1c.WriteReq_accesses::total 25048 # number of WriteReq accesses(hits+misses) system.cpu2.l1c.demand_accesses::cpu2 70491 # number of demand (read+write) accesses system.cpu2.l1c.demand_accesses::total 70491 # number of demand (read+write) accesses system.cpu2.l1c.overall_accesses::cpu2 70491 # number of overall (read+write) accesses system.cpu2.l1c.overall_accesses::total 70491 # number of overall (read+write) accesses system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808551 # miss rate for ReadReq accesses system.cpu2.l1c.ReadReq_miss_rate::total 0.808551 # miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954847 # miss rate for WriteReq accesses system.cpu2.l1c.WriteReq_miss_rate::total 0.954847 # miss rate for WriteReq accesses system.cpu2.l1c.demand_miss_rate::cpu2 0.860535 # miss rate for demand accesses system.cpu2.l1c.demand_miss_rate::total 0.860535 # miss rate for demand accesses system.cpu2.l1c.overall_miss_rate::cpu2 0.860535 # miss rate for overall accesses system.cpu2.l1c.overall_miss_rate::total 0.860535 # miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18177.398089 # average ReadReq miss latency system.cpu2.l1c.ReadReq_avg_miss_latency::total 18177.398089 # average ReadReq miss latency system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23490.789731 # average WriteReq miss latency system.cpu2.l1c.WriteReq_avg_miss_latency::total 23490.789731 # average WriteReq miss latency system.cpu2.l1c.demand_avg_miss_latency::cpu2 20272.359974 # average overall miss latency system.cpu2.l1c.demand_avg_miss_latency::total 20272.359974 # average overall miss latency system.cpu2.l1c.overall_avg_miss_latency::cpu2 20272.359974 # average overall miss latency system.cpu2.l1c.overall_avg_miss_latency::total 20272.359974 # average overall miss latency system.cpu2.l1c.blocked_cycles::no_mshrs 824101 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.blocked::no_mshrs 66507 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.391192 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.writebacks::writebacks 9742 # number of writebacks system.cpu2.l1c.writebacks::total 9742 # number of writebacks system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36743 # number of ReadReq MSHR misses system.cpu2.l1c.ReadReq_mshr_misses::total 36743 # number of ReadReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23917 # number of WriteReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::total 23917 # number of WriteReq MSHR misses system.cpu2.l1c.demand_mshr_misses::cpu2 60660 # number of demand (read+write) MSHR misses system.cpu2.l1c.demand_mshr_misses::total 60660 # number of demand (read+write) MSHR misses system.cpu2.l1c.overall_mshr_misses::cpu2 60660 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_misses::total 60660 # number of overall MSHR misses system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable system.cpu2.l1c.ReadReq_mshr_uncacheable::total 10005 # number of ReadReq MSHR uncacheable system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5482 # number of WriteReq MSHR uncacheable system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15487 # number of overall MSHR uncacheable misses system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 631149138 # number of ReadReq MSHR miss cycles system.cpu2.l1c.ReadReq_mshr_miss_latency::total 631149138 # number of ReadReq MSHR miss cycles system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537912218 # number of WriteReq MSHR miss cycles system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537912218 # number of WriteReq MSHR miss cycles system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1169061356 # number of demand (read+write) MSHR miss cycles system.cpu2.l1c.demand_mshr_miss_latency::total 1169061356 # number of demand (read+write) MSHR miss cycles system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1169061356 # number of overall MSHR miss cycles system.cpu2.l1c.overall_mshr_miss_latency::total 1169061356 # number of overall MSHR miss cycles system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 759988155 # number of ReadReq MSHR uncacheable cycles system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 759988155 # number of ReadReq MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 759988155 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_latency::total 759988155 # number of overall MSHR uncacheable cycles system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808551 # mshr miss rate for ReadReq accesses system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808551 # mshr miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954847 # mshr miss rate for WriteReq accesses system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954847 # mshr miss rate for WriteReq accesses system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for demand accesses system.cpu2.l1c.demand_mshr_miss_rate::total 0.860535 # mshr miss rate for demand accesses system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for overall accesses system.cpu2.l1c.overall_mshr_miss_rate::total 0.860535 # mshr miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17177.398089 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17177.398089 # average ReadReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22490.789731 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22490.789731 # average WriteReq mshr miss latency system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75960.835082 # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75960.835082 # average ReadReq mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 49072.651579 # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 49072.651579 # average overall mshr uncacheable latency system.cpu3.num_reads 99085 # number of read accesses completed system.cpu3.num_writes 55606 # number of write accesses completed system.cpu3.l1c.tags.replacements 22528 # number of replacements system.cpu3.l1c.tags.tagsinuse 391.624901 # Cycle average of tags in use system.cpu3.l1c.tags.total_refs 13493 # Total number of references to valid blocks. system.cpu3.l1c.tags.sampled_refs 22909 # Sample count of references to valid blocks. system.cpu3.l1c.tags.avg_refs 0.588982 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.l1c.tags.occ_blocks::cpu3 391.624901 # Average occupied blocks per requestor system.cpu3.l1c.tags.occ_percent::cpu3 0.764892 # Average percentage of cache occupancy system.cpu3.l1c.tags.occ_percent::total 0.764892 # Average percentage of cache occupancy system.cpu3.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id system.cpu3.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu3.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id system.cpu3.l1c.tags.tag_accesses 339302 # Number of tag accesses system.cpu3.l1c.tags.data_accesses 339302 # Number of data accesses system.cpu3.l1c.ReadReq_hits::cpu3 8770 # number of ReadReq hits system.cpu3.l1c.ReadReq_hits::total 8770 # number of ReadReq hits system.cpu3.l1c.WriteReq_hits::cpu3 1134 # number of WriteReq hits system.cpu3.l1c.WriteReq_hits::total 1134 # number of WriteReq hits system.cpu3.l1c.demand_hits::cpu3 9904 # number of demand (read+write) hits system.cpu3.l1c.demand_hits::total 9904 # number of demand (read+write) hits system.cpu3.l1c.overall_hits::cpu3 9904 # number of overall hits system.cpu3.l1c.overall_hits::total 9904 # number of overall hits system.cpu3.l1c.ReadReq_misses::cpu3 36439 # number of ReadReq misses system.cpu3.l1c.ReadReq_misses::total 36439 # number of ReadReq misses system.cpu3.l1c.WriteReq_misses::cpu3 24225 # number of WriteReq misses system.cpu3.l1c.WriteReq_misses::total 24225 # number of WriteReq misses system.cpu3.l1c.demand_misses::cpu3 60664 # number of demand (read+write) misses system.cpu3.l1c.demand_misses::total 60664 # number of demand (read+write) misses system.cpu3.l1c.overall_misses::cpu3 60664 # number of overall misses system.cpu3.l1c.overall_misses::total 60664 # number of overall misses system.cpu3.l1c.ReadReq_miss_latency::cpu3 671429109 # number of ReadReq miss cycles system.cpu3.l1c.ReadReq_miss_latency::total 671429109 # number of ReadReq miss cycles system.cpu3.l1c.WriteReq_miss_latency::cpu3 572133441 # number of WriteReq miss cycles system.cpu3.l1c.WriteReq_miss_latency::total 572133441 # number of WriteReq miss cycles system.cpu3.l1c.demand_miss_latency::cpu3 1243562550 # number of demand (read+write) miss cycles system.cpu3.l1c.demand_miss_latency::total 1243562550 # number of demand (read+write) miss cycles system.cpu3.l1c.overall_miss_latency::cpu3 1243562550 # number of overall miss cycles system.cpu3.l1c.overall_miss_latency::total 1243562550 # number of overall miss cycles system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) system.cpu3.l1c.WriteReq_accesses::cpu3 25359 # number of WriteReq accesses(hits+misses) system.cpu3.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses) system.cpu3.l1c.demand_accesses::cpu3 70568 # number of demand (read+write) accesses system.cpu3.l1c.demand_accesses::total 70568 # number of demand (read+write) accesses system.cpu3.l1c.overall_accesses::cpu3 70568 # number of overall (read+write) accesses system.cpu3.l1c.overall_accesses::total 70568 # number of overall (read+write) accesses system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806012 # miss rate for ReadReq accesses system.cpu3.l1c.ReadReq_miss_rate::total 0.806012 # miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955282 # miss rate for WriteReq accesses system.cpu3.l1c.WriteReq_miss_rate::total 0.955282 # miss rate for WriteReq accesses system.cpu3.l1c.demand_miss_rate::cpu3 0.859653 # miss rate for demand accesses system.cpu3.l1c.demand_miss_rate::total 0.859653 # miss rate for demand accesses system.cpu3.l1c.overall_miss_rate::cpu3 0.859653 # miss rate for overall accesses system.cpu3.l1c.overall_miss_rate::total 0.859653 # miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18426.112380 # average ReadReq miss latency system.cpu3.l1c.ReadReq_avg_miss_latency::total 18426.112380 # average ReadReq miss latency system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23617.479505 # average WriteReq miss latency system.cpu3.l1c.WriteReq_avg_miss_latency::total 23617.479505 # average WriteReq miss latency system.cpu3.l1c.demand_avg_miss_latency::cpu3 20499.184854 # average overall miss latency system.cpu3.l1c.demand_avg_miss_latency::total 20499.184854 # average overall miss latency system.cpu3.l1c.overall_avg_miss_latency::cpu3 20499.184854 # average overall miss latency system.cpu3.l1c.overall_avg_miss_latency::total 20499.184854 # average overall miss latency system.cpu3.l1c.blocked_cycles::no_mshrs 821290 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.blocked::no_mshrs 66174 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.411068 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.writebacks::writebacks 10017 # number of writebacks system.cpu3.l1c.writebacks::total 10017 # number of writebacks system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36439 # number of ReadReq MSHR misses system.cpu3.l1c.ReadReq_mshr_misses::total 36439 # number of ReadReq MSHR misses system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24225 # number of WriteReq MSHR misses system.cpu3.l1c.WriteReq_mshr_misses::total 24225 # number of WriteReq MSHR misses system.cpu3.l1c.demand_mshr_misses::cpu3 60664 # number of demand (read+write) MSHR misses system.cpu3.l1c.demand_mshr_misses::total 60664 # number of demand (read+write) MSHR misses system.cpu3.l1c.overall_mshr_misses::cpu3 60664 # number of overall MSHR misses system.cpu3.l1c.overall_mshr_misses::total 60664 # number of overall MSHR misses system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5538 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5538 # number of WriteReq MSHR uncacheable system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15311 # number of overall MSHR uncacheable misses system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 634992109 # number of ReadReq MSHR miss cycles system.cpu3.l1c.ReadReq_mshr_miss_latency::total 634992109 # number of ReadReq MSHR miss cycles system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 547908441 # number of WriteReq MSHR miss cycles system.cpu3.l1c.WriteReq_mshr_miss_latency::total 547908441 # number of WriteReq MSHR miss cycles system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1182900550 # number of demand (read+write) MSHR miss cycles system.cpu3.l1c.demand_mshr_miss_latency::total 1182900550 # number of demand (read+write) MSHR miss cycles system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1182900550 # number of overall MSHR miss cycles system.cpu3.l1c.overall_mshr_miss_latency::total 1182900550 # number of overall MSHR miss cycles system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 743773245 # number of ReadReq MSHR uncacheable cycles system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 743773245 # number of ReadReq MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 743773245 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_latency::total 743773245 # number of overall MSHR uncacheable cycles system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806012 # mshr miss rate for ReadReq accesses system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806012 # mshr miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955282 # mshr miss rate for WriteReq accesses system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955282 # mshr miss rate for WriteReq accesses system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for demand accesses system.cpu3.l1c.demand_mshr_miss_rate::total 0.859653 # mshr miss rate for demand accesses system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for overall accesses system.cpu3.l1c.overall_mshr_miss_rate::total 0.859653 # mshr miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17426.167266 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17426.167266 # average ReadReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22617.479505 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22617.479505 # average WriteReq mshr miss latency system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 76104.905863 # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76104.905863 # average ReadReq mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 48577.705245 # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 48577.705245 # average overall mshr uncacheable latency system.cpu4.num_reads 99978 # number of read accesses completed system.cpu4.num_writes 55474 # number of write accesses completed system.cpu4.l1c.tags.replacements 22223 # number of replacements system.cpu4.l1c.tags.tagsinuse 391.899958 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13858 # Total number of references to valid blocks. system.cpu4.l1c.tags.sampled_refs 22628 # Sample count of references to valid blocks. system.cpu4.l1c.tags.avg_refs 0.612427 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu4.l1c.tags.occ_blocks::cpu4 391.899958 # Average occupied blocks per requestor system.cpu4.l1c.tags.occ_percent::cpu4 0.765430 # Average percentage of cache occupancy system.cpu4.l1c.tags.occ_percent::total 0.765430 # Average percentage of cache occupancy system.cpu4.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id system.cpu4.l1c.tags.age_task_id_blocks_1024::0 396 # Occupied blocks per task id system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id system.cpu4.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id system.cpu4.l1c.tags.tag_accesses 340964 # Number of tag accesses system.cpu4.l1c.tags.data_accesses 340964 # Number of data accesses system.cpu4.l1c.ReadReq_hits::cpu4 8890 # number of ReadReq hits system.cpu4.l1c.ReadReq_hits::total 8890 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1171 # number of WriteReq hits system.cpu4.l1c.WriteReq_hits::total 1171 # number of WriteReq hits system.cpu4.l1c.demand_hits::cpu4 10061 # number of demand (read+write) hits system.cpu4.l1c.demand_hits::total 10061 # number of demand (read+write) hits system.cpu4.l1c.overall_hits::cpu4 10061 # number of overall hits system.cpu4.l1c.overall_hits::total 10061 # number of overall hits system.cpu4.l1c.ReadReq_misses::cpu4 36725 # number of ReadReq misses system.cpu4.l1c.ReadReq_misses::total 36725 # number of ReadReq misses system.cpu4.l1c.WriteReq_misses::cpu4 24186 # number of WriteReq misses system.cpu4.l1c.WriteReq_misses::total 24186 # number of WriteReq misses system.cpu4.l1c.demand_misses::cpu4 60911 # number of demand (read+write) misses system.cpu4.l1c.demand_misses::total 60911 # number of demand (read+write) misses system.cpu4.l1c.overall_misses::cpu4 60911 # number of overall misses system.cpu4.l1c.overall_misses::total 60911 # number of overall misses system.cpu4.l1c.ReadReq_miss_latency::cpu4 668441602 # number of ReadReq miss cycles system.cpu4.l1c.ReadReq_miss_latency::total 668441602 # number of ReadReq miss cycles system.cpu4.l1c.WriteReq_miss_latency::cpu4 573535032 # number of WriteReq miss cycles system.cpu4.l1c.WriteReq_miss_latency::total 573535032 # number of WriteReq miss cycles system.cpu4.l1c.demand_miss_latency::cpu4 1241976634 # number of demand (read+write) miss cycles system.cpu4.l1c.demand_miss_latency::total 1241976634 # number of demand (read+write) miss cycles system.cpu4.l1c.overall_miss_latency::cpu4 1241976634 # number of overall miss cycles system.cpu4.l1c.overall_miss_latency::total 1241976634 # number of overall miss cycles system.cpu4.l1c.ReadReq_accesses::cpu4 45615 # number of ReadReq accesses(hits+misses) system.cpu4.l1c.ReadReq_accesses::total 45615 # number of ReadReq accesses(hits+misses) system.cpu4.l1c.WriteReq_accesses::cpu4 25357 # number of WriteReq accesses(hits+misses) system.cpu4.l1c.WriteReq_accesses::total 25357 # number of WriteReq accesses(hits+misses) system.cpu4.l1c.demand_accesses::cpu4 70972 # number of demand (read+write) accesses system.cpu4.l1c.demand_accesses::total 70972 # number of demand (read+write) accesses system.cpu4.l1c.overall_accesses::cpu4 70972 # number of overall (read+write) accesses system.cpu4.l1c.overall_accesses::total 70972 # number of overall (read+write) accesses system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805108 # miss rate for ReadReq accesses system.cpu4.l1c.ReadReq_miss_rate::total 0.805108 # miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953819 # miss rate for WriteReq accesses system.cpu4.l1c.WriteReq_miss_rate::total 0.953819 # miss rate for WriteReq accesses system.cpu4.l1c.demand_miss_rate::cpu4 0.858240 # miss rate for demand accesses system.cpu4.l1c.demand_miss_rate::total 0.858240 # miss rate for demand accesses system.cpu4.l1c.overall_miss_rate::cpu4 0.858240 # miss rate for overall accesses system.cpu4.l1c.overall_miss_rate::total 0.858240 # miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18201.268945 # average ReadReq miss latency system.cpu4.l1c.ReadReq_avg_miss_latency::total 18201.268945 # average ReadReq miss latency system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23713.513272 # average WriteReq miss latency system.cpu4.l1c.WriteReq_avg_miss_latency::total 23713.513272 # average WriteReq miss latency system.cpu4.l1c.demand_avg_miss_latency::cpu4 20390.022065 # average overall miss latency system.cpu4.l1c.demand_avg_miss_latency::total 20390.022065 # average overall miss latency system.cpu4.l1c.overall_avg_miss_latency::cpu4 20390.022065 # average overall miss latency system.cpu4.l1c.overall_avg_miss_latency::total 20390.022065 # average overall miss latency system.cpu4.l1c.blocked_cycles::no_mshrs 823668 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.blocked::no_mshrs 66629 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.362005 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.writebacks::writebacks 9699 # number of writebacks system.cpu4.l1c.writebacks::total 9699 # number of writebacks system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36725 # number of ReadReq MSHR misses system.cpu4.l1c.ReadReq_mshr_misses::total 36725 # number of ReadReq MSHR misses system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24186 # number of WriteReq MSHR misses system.cpu4.l1c.WriteReq_mshr_misses::total 24186 # number of WriteReq MSHR misses system.cpu4.l1c.demand_mshr_misses::cpu4 60911 # number of demand (read+write) MSHR misses system.cpu4.l1c.demand_mshr_misses::total 60911 # number of demand (read+write) MSHR misses system.cpu4.l1c.overall_mshr_misses::cpu4 60911 # number of overall MSHR misses system.cpu4.l1c.overall_mshr_misses::total 60911 # number of overall MSHR misses system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9801 # number of ReadReq MSHR uncacheable system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5498 # number of WriteReq MSHR uncacheable system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 631717602 # number of ReadReq MSHR miss cycles system.cpu4.l1c.ReadReq_mshr_miss_latency::total 631717602 # number of ReadReq MSHR miss cycles system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 549351032 # number of WriteReq MSHR miss cycles system.cpu4.l1c.WriteReq_mshr_miss_latency::total 549351032 # number of WriteReq MSHR miss cycles system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1181068634 # number of demand (read+write) MSHR miss cycles system.cpu4.l1c.demand_mshr_miss_latency::total 1181068634 # number of demand (read+write) MSHR miss cycles system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1181068634 # number of overall MSHR miss cycles system.cpu4.l1c.overall_mshr_miss_latency::total 1181068634 # number of overall MSHR miss cycles system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748050214 # number of ReadReq MSHR uncacheable cycles system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748050214 # number of ReadReq MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 748050214 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_latency::total 748050214 # number of overall MSHR uncacheable cycles system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805108 # mshr miss rate for ReadReq accesses system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805108 # mshr miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953819 # mshr miss rate for WriteReq accesses system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953819 # mshr miss rate for WriteReq accesses system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for demand accesses system.cpu4.l1c.demand_mshr_miss_rate::total 0.858240 # mshr miss rate for demand accesses system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for overall accesses system.cpu4.l1c.overall_mshr_miss_rate::total 0.858240 # mshr miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17201.296174 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17201.296174 # average ReadReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22713.595965 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22713.595965 # average WriteReq mshr miss latency system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 76323.866340 # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76323.866340 # average ReadReq mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48895.366625 # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48895.366625 # average overall mshr uncacheable latency system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 55110 # number of write accesses completed system.cpu5.l1c.tags.replacements 22358 # number of replacements system.cpu5.l1c.tags.tagsinuse 391.816568 # Cycle average of tags in use system.cpu5.l1c.tags.total_refs 13630 # Total number of references to valid blocks. system.cpu5.l1c.tags.sampled_refs 22751 # Sample count of references to valid blocks. system.cpu5.l1c.tags.avg_refs 0.599095 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu5.l1c.tags.occ_blocks::cpu5 391.816568 # Average occupied blocks per requestor system.cpu5.l1c.tags.occ_percent::cpu5 0.765267 # Average percentage of cache occupancy system.cpu5.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy system.cpu5.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id system.cpu5.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu5.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id system.cpu5.l1c.tags.tag_accesses 340100 # Number of tag accesses system.cpu5.l1c.tags.data_accesses 340100 # Number of data accesses system.cpu5.l1c.ReadReq_hits::cpu5 8821 # number of ReadReq hits system.cpu5.l1c.ReadReq_hits::total 8821 # number of ReadReq hits system.cpu5.l1c.WriteReq_hits::cpu5 1107 # number of WriteReq hits system.cpu5.l1c.WriteReq_hits::total 1107 # number of WriteReq hits system.cpu5.l1c.demand_hits::cpu5 9928 # number of demand (read+write) hits system.cpu5.l1c.demand_hits::total 9928 # number of demand (read+write) hits system.cpu5.l1c.overall_hits::cpu5 9928 # number of overall hits system.cpu5.l1c.overall_hits::total 9928 # number of overall hits system.cpu5.l1c.ReadReq_misses::cpu5 36801 # number of ReadReq misses system.cpu5.l1c.ReadReq_misses::total 36801 # number of ReadReq misses system.cpu5.l1c.WriteReq_misses::cpu5 24029 # number of WriteReq misses system.cpu5.l1c.WriteReq_misses::total 24029 # number of WriteReq misses system.cpu5.l1c.demand_misses::cpu5 60830 # number of demand (read+write) misses system.cpu5.l1c.demand_misses::total 60830 # number of demand (read+write) misses system.cpu5.l1c.overall_misses::cpu5 60830 # number of overall misses system.cpu5.l1c.overall_misses::total 60830 # number of overall misses system.cpu5.l1c.ReadReq_miss_latency::cpu5 677475643 # number of ReadReq miss cycles system.cpu5.l1c.ReadReq_miss_latency::total 677475643 # number of ReadReq miss cycles system.cpu5.l1c.WriteReq_miss_latency::cpu5 566244558 # number of WriteReq miss cycles system.cpu5.l1c.WriteReq_miss_latency::total 566244558 # number of WriteReq miss cycles system.cpu5.l1c.demand_miss_latency::cpu5 1243720201 # number of demand (read+write) miss cycles system.cpu5.l1c.demand_miss_latency::total 1243720201 # number of demand (read+write) miss cycles system.cpu5.l1c.overall_miss_latency::cpu5 1243720201 # number of overall miss cycles system.cpu5.l1c.overall_miss_latency::total 1243720201 # number of overall miss cycles system.cpu5.l1c.ReadReq_accesses::cpu5 45622 # number of ReadReq accesses(hits+misses) system.cpu5.l1c.ReadReq_accesses::total 45622 # number of ReadReq accesses(hits+misses) system.cpu5.l1c.WriteReq_accesses::cpu5 25136 # number of WriteReq accesses(hits+misses) system.cpu5.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses) system.cpu5.l1c.demand_accesses::cpu5 70758 # number of demand (read+write) accesses system.cpu5.l1c.demand_accesses::total 70758 # number of demand (read+write) accesses system.cpu5.l1c.overall_accesses::cpu5 70758 # number of overall (read+write) accesses system.cpu5.l1c.overall_accesses::total 70758 # number of overall (read+write) accesses system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806650 # miss rate for ReadReq accesses system.cpu5.l1c.ReadReq_miss_rate::total 0.806650 # miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955960 # miss rate for WriteReq accesses system.cpu5.l1c.WriteReq_miss_rate::total 0.955960 # miss rate for WriteReq accesses system.cpu5.l1c.demand_miss_rate::cpu5 0.859691 # miss rate for demand accesses system.cpu5.l1c.demand_miss_rate::total 0.859691 # miss rate for demand accesses system.cpu5.l1c.overall_miss_rate::cpu5 0.859691 # miss rate for overall accesses system.cpu5.l1c.overall_miss_rate::total 0.859691 # miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18409.163963 # average ReadReq miss latency system.cpu5.l1c.ReadReq_avg_miss_latency::total 18409.163963 # average ReadReq miss latency system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23565.048816 # average WriteReq miss latency system.cpu5.l1c.WriteReq_avg_miss_latency::total 23565.048816 # average WriteReq miss latency system.cpu5.l1c.demand_avg_miss_latency::cpu5 20445.835953 # average overall miss latency system.cpu5.l1c.demand_avg_miss_latency::total 20445.835953 # average overall miss latency system.cpu5.l1c.overall_avg_miss_latency::cpu5 20445.835953 # average overall miss latency system.cpu5.l1c.overall_avg_miss_latency::total 20445.835953 # average overall miss latency system.cpu5.l1c.blocked_cycles::no_mshrs 821580 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.blocked::no_mshrs 66406 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.372075 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.writebacks::writebacks 10004 # number of writebacks system.cpu5.l1c.writebacks::total 10004 # number of writebacks system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36801 # number of ReadReq MSHR misses system.cpu5.l1c.ReadReq_mshr_misses::total 36801 # number of ReadReq MSHR misses system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24029 # number of WriteReq MSHR misses system.cpu5.l1c.WriteReq_mshr_misses::total 24029 # number of WriteReq MSHR misses system.cpu5.l1c.demand_mshr_misses::cpu5 60830 # number of demand (read+write) MSHR misses system.cpu5.l1c.demand_mshr_misses::total 60830 # number of demand (read+write) MSHR misses system.cpu5.l1c.overall_mshr_misses::cpu5 60830 # number of overall MSHR misses system.cpu5.l1c.overall_mshr_misses::total 60830 # number of overall MSHR misses system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9765 # number of ReadReq MSHR uncacheable system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5412 # number of WriteReq MSHR uncacheable system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5412 # number of WriteReq MSHR uncacheable system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15177 # number of overall MSHR uncacheable misses system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15177 # number of overall MSHR uncacheable misses system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 640675643 # number of ReadReq MSHR miss cycles system.cpu5.l1c.ReadReq_mshr_miss_latency::total 640675643 # number of ReadReq MSHR miss cycles system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 542215558 # number of WriteReq MSHR miss cycles system.cpu5.l1c.WriteReq_mshr_miss_latency::total 542215558 # number of WriteReq MSHR miss cycles system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1182891201 # number of demand (read+write) MSHR miss cycles system.cpu5.l1c.demand_mshr_miss_latency::total 1182891201 # number of demand (read+write) MSHR miss cycles system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1182891201 # number of overall MSHR miss cycles system.cpu5.l1c.overall_mshr_miss_latency::total 1182891201 # number of overall MSHR miss cycles system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 744215663 # number of ReadReq MSHR uncacheable cycles system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 744215663 # number of ReadReq MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 744215663 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_latency::total 744215663 # number of overall MSHR uncacheable cycles system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806650 # mshr miss rate for ReadReq accesses system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806650 # mshr miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955960 # mshr miss rate for WriteReq accesses system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955960 # mshr miss rate for WriteReq accesses system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for demand accesses system.cpu5.l1c.demand_mshr_miss_rate::total 0.859691 # mshr miss rate for demand accesses system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for overall accesses system.cpu5.l1c.overall_mshr_miss_rate::total 0.859691 # mshr miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17409.191136 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17409.191136 # average ReadReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22565.048816 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22565.048816 # average WriteReq mshr miss latency system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 76212.561495 # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76212.561495 # average ReadReq mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 49035.755617 # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 49035.755617 # average overall mshr uncacheable latency system.cpu6.num_reads 99774 # number of read accesses completed system.cpu6.num_writes 55185 # number of write accesses completed system.cpu6.l1c.tags.replacements 22542 # number of replacements system.cpu6.l1c.tags.tagsinuse 391.726459 # Cycle average of tags in use system.cpu6.l1c.tags.total_refs 13419 # Total number of references to valid blocks. system.cpu6.l1c.tags.sampled_refs 22929 # Sample count of references to valid blocks. system.cpu6.l1c.tags.avg_refs 0.585241 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu6.l1c.tags.occ_blocks::cpu6 391.726459 # Average occupied blocks per requestor system.cpu6.l1c.tags.occ_percent::cpu6 0.765091 # Average percentage of cache occupancy system.cpu6.l1c.tags.occ_percent::total 0.765091 # Average percentage of cache occupancy system.cpu6.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id system.cpu6.l1c.tags.tag_accesses 339673 # Number of tag accesses system.cpu6.l1c.tags.data_accesses 339673 # Number of data accesses system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits system.cpu6.l1c.WriteReq_hits::cpu6 1147 # number of WriteReq hits system.cpu6.l1c.WriteReq_hits::total 1147 # number of WriteReq hits system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits system.cpu6.l1c.overall_hits::total 9857 # number of overall hits system.cpu6.l1c.ReadReq_misses::cpu6 36696 # number of ReadReq misses system.cpu6.l1c.ReadReq_misses::total 36696 # number of ReadReq misses system.cpu6.l1c.WriteReq_misses::cpu6 24079 # number of WriteReq misses system.cpu6.l1c.WriteReq_misses::total 24079 # number of WriteReq misses system.cpu6.l1c.demand_misses::cpu6 60775 # number of demand (read+write) misses system.cpu6.l1c.demand_misses::total 60775 # number of demand (read+write) misses system.cpu6.l1c.overall_misses::cpu6 60775 # number of overall misses system.cpu6.l1c.overall_misses::total 60775 # number of overall misses system.cpu6.l1c.ReadReq_miss_latency::cpu6 672502171 # number of ReadReq miss cycles system.cpu6.l1c.ReadReq_miss_latency::total 672502171 # number of ReadReq miss cycles system.cpu6.l1c.WriteReq_miss_latency::cpu6 571063447 # number of WriteReq miss cycles system.cpu6.l1c.WriteReq_miss_latency::total 571063447 # number of WriteReq miss cycles system.cpu6.l1c.demand_miss_latency::cpu6 1243565618 # number of demand (read+write) miss cycles system.cpu6.l1c.demand_miss_latency::total 1243565618 # number of demand (read+write) miss cycles system.cpu6.l1c.overall_miss_latency::cpu6 1243565618 # number of overall miss cycles system.cpu6.l1c.overall_miss_latency::total 1243565618 # number of overall miss cycles system.cpu6.l1c.ReadReq_accesses::cpu6 45406 # number of ReadReq accesses(hits+misses) system.cpu6.l1c.ReadReq_accesses::total 45406 # number of ReadReq accesses(hits+misses) system.cpu6.l1c.WriteReq_accesses::cpu6 25226 # number of WriteReq accesses(hits+misses) system.cpu6.l1c.WriteReq_accesses::total 25226 # number of WriteReq accesses(hits+misses) system.cpu6.l1c.demand_accesses::cpu6 70632 # number of demand (read+write) accesses system.cpu6.l1c.demand_accesses::total 70632 # number of demand (read+write) accesses system.cpu6.l1c.overall_accesses::cpu6 70632 # number of overall (read+write) accesses system.cpu6.l1c.overall_accesses::total 70632 # number of overall (read+write) accesses system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808175 # miss rate for ReadReq accesses system.cpu6.l1c.ReadReq_miss_rate::total 0.808175 # miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954531 # miss rate for WriteReq accesses system.cpu6.l1c.WriteReq_miss_rate::total 0.954531 # miss rate for WriteReq accesses system.cpu6.l1c.demand_miss_rate::cpu6 0.860446 # miss rate for demand accesses system.cpu6.l1c.demand_miss_rate::total 0.860446 # miss rate for demand accesses system.cpu6.l1c.overall_miss_rate::cpu6 0.860446 # miss rate for overall accesses system.cpu6.l1c.overall_miss_rate::total 0.860446 # miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18326.307254 # average ReadReq miss latency system.cpu6.l1c.ReadReq_avg_miss_latency::total 18326.307254 # average ReadReq miss latency system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23716.244321 # average WriteReq miss latency system.cpu6.l1c.WriteReq_avg_miss_latency::total 23716.244321 # average WriteReq miss latency system.cpu6.l1c.demand_avg_miss_latency::cpu6 20461.795442 # average overall miss latency system.cpu6.l1c.demand_avg_miss_latency::total 20461.795442 # average overall miss latency system.cpu6.l1c.overall_avg_miss_latency::cpu6 20461.795442 # average overall miss latency system.cpu6.l1c.overall_avg_miss_latency::total 20461.795442 # average overall miss latency system.cpu6.l1c.blocked_cycles::no_mshrs 822508 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.blocked::no_mshrs 66430 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.381575 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.writebacks::writebacks 9969 # number of writebacks system.cpu6.l1c.writebacks::total 9969 # number of writebacks system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36696 # number of ReadReq MSHR misses system.cpu6.l1c.ReadReq_mshr_misses::total 36696 # number of ReadReq MSHR misses system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24079 # number of WriteReq MSHR misses system.cpu6.l1c.WriteReq_mshr_misses::total 24079 # number of WriteReq MSHR misses system.cpu6.l1c.demand_mshr_misses::cpu6 60775 # number of demand (read+write) MSHR misses system.cpu6.l1c.demand_mshr_misses::total 60775 # number of demand (read+write) MSHR misses system.cpu6.l1c.overall_mshr_misses::cpu6 60775 # number of overall MSHR misses system.cpu6.l1c.overall_mshr_misses::total 60775 # number of overall MSHR misses system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9782 # number of ReadReq MSHR uncacheable system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15220 # number of overall MSHR uncacheable misses system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 635806171 # number of ReadReq MSHR miss cycles system.cpu6.l1c.ReadReq_mshr_miss_latency::total 635806171 # number of ReadReq MSHR miss cycles system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 546984447 # number of WriteReq MSHR miss cycles system.cpu6.l1c.WriteReq_mshr_miss_latency::total 546984447 # number of WriteReq MSHR miss cycles system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1182790618 # number of demand (read+write) MSHR miss cycles system.cpu6.l1c.demand_mshr_miss_latency::total 1182790618 # number of demand (read+write) MSHR miss cycles system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1182790618 # number of overall MSHR miss cycles system.cpu6.l1c.overall_mshr_miss_latency::total 1182790618 # number of overall MSHR miss cycles system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 745377162 # number of ReadReq MSHR uncacheable cycles system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 745377162 # number of ReadReq MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 745377162 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_latency::total 745377162 # number of overall MSHR uncacheable cycles system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808175 # mshr miss rate for ReadReq accesses system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808175 # mshr miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954531 # mshr miss rate for WriteReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954531 # mshr miss rate for WriteReq accesses system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for demand accesses system.cpu6.l1c.demand_mshr_miss_rate::total 0.860446 # mshr miss rate for demand accesses system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for overall accesses system.cpu6.l1c.overall_mshr_miss_rate::total 0.860446 # mshr miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17326.307254 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17326.307254 # average ReadReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22716.244321 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22716.244321 # average WriteReq mshr miss latency system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 76198.851155 # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76198.851155 # average ReadReq mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 48973.532326 # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 48973.532326 # average overall mshr uncacheable latency system.cpu7.num_reads 99703 # number of read accesses completed system.cpu7.num_writes 55656 # number of write accesses completed system.cpu7.l1c.tags.replacements 22447 # number of replacements system.cpu7.l1c.tags.tagsinuse 392.675740 # Cycle average of tags in use system.cpu7.l1c.tags.total_refs 13542 # Total number of references to valid blocks. system.cpu7.l1c.tags.sampled_refs 22845 # Sample count of references to valid blocks. system.cpu7.l1c.tags.avg_refs 0.592777 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu7.l1c.tags.occ_blocks::cpu7 392.675740 # Average occupied blocks per requestor system.cpu7.l1c.tags.occ_percent::cpu7 0.766945 # Average percentage of cache occupancy system.cpu7.l1c.tags.occ_percent::total 0.766945 # Average percentage of cache occupancy system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id system.cpu7.l1c.tags.tag_accesses 338950 # Number of tag accesses system.cpu7.l1c.tags.data_accesses 338950 # Number of data accesses system.cpu7.l1c.ReadReq_hits::cpu7 8682 # number of ReadReq hits system.cpu7.l1c.ReadReq_hits::total 8682 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1173 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 1173 # number of WriteReq hits system.cpu7.l1c.demand_hits::cpu7 9855 # number of demand (read+write) hits system.cpu7.l1c.demand_hits::total 9855 # number of demand (read+write) hits system.cpu7.l1c.overall_hits::cpu7 9855 # number of overall hits system.cpu7.l1c.overall_hits::total 9855 # number of overall hits system.cpu7.l1c.ReadReq_misses::cpu7 36511 # number of ReadReq misses system.cpu7.l1c.ReadReq_misses::total 36511 # number of ReadReq misses system.cpu7.l1c.WriteReq_misses::cpu7 24145 # number of WriteReq misses system.cpu7.l1c.WriteReq_misses::total 24145 # number of WriteReq misses system.cpu7.l1c.demand_misses::cpu7 60656 # number of demand (read+write) misses system.cpu7.l1c.demand_misses::total 60656 # number of demand (read+write) misses system.cpu7.l1c.overall_misses::cpu7 60656 # number of overall misses system.cpu7.l1c.overall_misses::total 60656 # number of overall misses system.cpu7.l1c.ReadReq_miss_latency::cpu7 668215285 # number of ReadReq miss cycles system.cpu7.l1c.ReadReq_miss_latency::total 668215285 # number of ReadReq miss cycles system.cpu7.l1c.WriteReq_miss_latency::cpu7 564137498 # number of WriteReq miss cycles system.cpu7.l1c.WriteReq_miss_latency::total 564137498 # number of WriteReq miss cycles system.cpu7.l1c.demand_miss_latency::cpu7 1232352783 # number of demand (read+write) miss cycles system.cpu7.l1c.demand_miss_latency::total 1232352783 # number of demand (read+write) miss cycles system.cpu7.l1c.overall_miss_latency::cpu7 1232352783 # number of overall miss cycles system.cpu7.l1c.overall_miss_latency::total 1232352783 # number of overall miss cycles system.cpu7.l1c.ReadReq_accesses::cpu7 45193 # number of ReadReq accesses(hits+misses) system.cpu7.l1c.ReadReq_accesses::total 45193 # number of ReadReq accesses(hits+misses) system.cpu7.l1c.WriteReq_accesses::cpu7 25318 # number of WriteReq accesses(hits+misses) system.cpu7.l1c.WriteReq_accesses::total 25318 # number of WriteReq accesses(hits+misses) system.cpu7.l1c.demand_accesses::cpu7 70511 # number of demand (read+write) accesses system.cpu7.l1c.demand_accesses::total 70511 # number of demand (read+write) accesses system.cpu7.l1c.overall_accesses::cpu7 70511 # number of overall (read+write) accesses system.cpu7.l1c.overall_accesses::total 70511 # number of overall (read+write) accesses system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807891 # miss rate for ReadReq accesses system.cpu7.l1c.ReadReq_miss_rate::total 0.807891 # miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953669 # miss rate for WriteReq accesses system.cpu7.l1c.WriteReq_miss_rate::total 0.953669 # miss rate for WriteReq accesses system.cpu7.l1c.demand_miss_rate::cpu7 0.860235 # miss rate for demand accesses system.cpu7.l1c.demand_miss_rate::total 0.860235 # miss rate for demand accesses system.cpu7.l1c.overall_miss_rate::cpu7 0.860235 # miss rate for overall accesses system.cpu7.l1c.overall_miss_rate::total 0.860235 # miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18301.752486 # average ReadReq miss latency system.cpu7.l1c.ReadReq_avg_miss_latency::total 18301.752486 # average ReadReq miss latency system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23364.568151 # average WriteReq miss latency system.cpu7.l1c.WriteReq_avg_miss_latency::total 23364.568151 # average WriteReq miss latency system.cpu7.l1c.demand_avg_miss_latency::cpu7 20317.079646 # average overall miss latency system.cpu7.l1c.demand_avg_miss_latency::total 20317.079646 # average overall miss latency system.cpu7.l1c.overall_avg_miss_latency::cpu7 20317.079646 # average overall miss latency system.cpu7.l1c.overall_avg_miss_latency::total 20317.079646 # average overall miss latency system.cpu7.l1c.blocked_cycles::no_mshrs 824059 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.blocked::no_mshrs 66592 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.374745 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.writebacks::writebacks 9889 # number of writebacks system.cpu7.l1c.writebacks::total 9889 # number of writebacks system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36511 # number of ReadReq MSHR misses system.cpu7.l1c.ReadReq_mshr_misses::total 36511 # number of ReadReq MSHR misses system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24145 # number of WriteReq MSHR misses system.cpu7.l1c.WriteReq_mshr_misses::total 24145 # number of WriteReq MSHR misses system.cpu7.l1c.demand_mshr_misses::cpu7 60656 # number of demand (read+write) MSHR misses system.cpu7.l1c.demand_mshr_misses::total 60656 # number of demand (read+write) MSHR misses system.cpu7.l1c.overall_mshr_misses::cpu7 60656 # number of overall MSHR misses system.cpu7.l1c.overall_mshr_misses::total 60656 # number of overall MSHR misses system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9951 # number of ReadReq MSHR uncacheable system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5417 # number of WriteReq MSHR uncacheable system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15368 # number of overall MSHR uncacheable misses system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15368 # number of overall MSHR uncacheable misses system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 631704285 # number of ReadReq MSHR miss cycles system.cpu7.l1c.ReadReq_mshr_miss_latency::total 631704285 # number of ReadReq MSHR miss cycles system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 539994498 # number of WriteReq MSHR miss cycles system.cpu7.l1c.WriteReq_mshr_miss_latency::total 539994498 # number of WriteReq MSHR miss cycles system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1171698783 # number of demand (read+write) MSHR miss cycles system.cpu7.l1c.demand_mshr_miss_latency::total 1171698783 # number of demand (read+write) MSHR miss cycles system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1171698783 # number of overall MSHR miss cycles system.cpu7.l1c.overall_mshr_miss_latency::total 1171698783 # number of overall MSHR miss cycles system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 757938041 # number of ReadReq MSHR uncacheable cycles system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 757938041 # number of ReadReq MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 757938041 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_latency::total 757938041 # number of overall MSHR uncacheable cycles system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807891 # mshr miss rate for ReadReq accesses system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807891 # mshr miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953669 # mshr miss rate for WriteReq accesses system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953669 # mshr miss rate for WriteReq accesses system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for demand accesses system.cpu7.l1c.demand_mshr_miss_rate::total 0.860235 # mshr miss rate for demand accesses system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for overall accesses system.cpu7.l1c.overall_mshr_miss_rate::total 0.860235 # mshr miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17301.752486 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17301.752486 # average ReadReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22364.650984 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22364.650984 # average WriteReq mshr miss latency system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 76167.022510 # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76167.022510 # average ReadReq mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49319.237441 # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49319.237441 # average overall mshr uncacheable latency system.l2c.tags.replacements 13600 # number of replacements system.l2c.tags.tagsinuse 785.994901 # Cycle average of tags in use system.l2c.tags.total_refs 164496 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 14391 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 11.430477 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 730.947637 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0 6.698781 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1 6.684981 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2 7.056959 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu3 6.865777 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu4 6.833706 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu5 7.577663 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu6 6.826515 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu7 6.502881 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.713816 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0 0.006542 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1 0.006528 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2 0.006892 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3 0.006705 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu4 0.006674 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu5 0.007400 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu6 0.006667 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu7 0.006350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.767573 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 651 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.772461 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 2102241 # Number of tag accesses system.l2c.tags.data_accesses 2102241 # Number of data accesses system.l2c.WritebackDirty_hits::writebacks 77703 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 77703 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0 290 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1 290 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2 294 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu3 264 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu4 279 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu5 289 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu6 268 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2299 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu0 1816 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1 1719 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu2 1709 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu3 1840 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu4 1788 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu5 1754 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu6 1794 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu7 1762 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 14182 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0 10810 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1 10840 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu2 11008 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu3 10829 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu4 10875 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu5 10716 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu7 10910 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 86815 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0 12626 # number of demand (read+write) hits system.l2c.demand_hits::cpu1 12559 # number of demand (read+write) hits system.l2c.demand_hits::cpu2 12717 # number of demand (read+write) hits system.l2c.demand_hits::cpu3 12669 # number of demand (read+write) hits system.l2c.demand_hits::cpu4 12663 # number of demand (read+write) hits system.l2c.demand_hits::cpu5 12470 # number of demand (read+write) hits system.l2c.demand_hits::cpu6 12621 # number of demand (read+write) hits system.l2c.demand_hits::cpu7 12672 # number of demand (read+write) hits system.l2c.demand_hits::total 100997 # number of demand (read+write) hits system.l2c.overall_hits::cpu0 12626 # number of overall hits system.l2c.overall_hits::cpu1 12559 # number of overall hits system.l2c.overall_hits::cpu2 12717 # number of overall hits system.l2c.overall_hits::cpu3 12669 # number of overall hits system.l2c.overall_hits::cpu4 12663 # number of overall hits system.l2c.overall_hits::cpu5 12470 # number of overall hits system.l2c.overall_hits::cpu6 12621 # number of overall hits system.l2c.overall_hits::cpu7 12672 # number of overall hits system.l2c.overall_hits::total 100997 # number of overall hits system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1 2133 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2 2089 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3 2051 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu4 2132 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu6 2082 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu7 2039 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 16603 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0 4589 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1 4573 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2 4653 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3 4696 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu4 4757 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu5 4526 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu6 4651 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu7 4580 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 37025 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0 704 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1 708 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu2 710 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu3 726 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu5 758 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu6 689 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu7 675 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 5641 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0 5293 # number of demand (read+write) misses system.l2c.demand_misses::cpu1 5281 # number of demand (read+write) misses system.l2c.demand_misses::cpu2 5363 # number of demand (read+write) misses system.l2c.demand_misses::cpu3 5422 # number of demand (read+write) misses system.l2c.demand_misses::cpu4 5428 # number of demand (read+write) misses system.l2c.demand_misses::cpu5 5284 # number of demand (read+write) misses system.l2c.demand_misses::cpu6 5340 # number of demand (read+write) misses system.l2c.demand_misses::cpu7 5255 # number of demand (read+write) misses system.l2c.demand_misses::total 42666 # number of demand (read+write) misses system.l2c.overall_misses::cpu0 5293 # number of overall misses system.l2c.overall_misses::cpu1 5281 # number of overall misses system.l2c.overall_misses::cpu2 5363 # number of overall misses system.l2c.overall_misses::cpu3 5422 # number of overall misses system.l2c.overall_misses::cpu4 5428 # number of overall misses system.l2c.overall_misses::cpu5 5284 # number of overall misses system.l2c.overall_misses::cpu6 5340 # number of overall misses system.l2c.overall_misses::cpu7 5255 # number of overall misses system.l2c.overall_misses::total 42666 # number of overall misses system.l2c.UpgradeReq_miss_latency::cpu0 33033499 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1 37073999 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2 35504000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu3 34167500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu4 35922999 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu5 36683500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu6 35141499 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu7 35012999 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 282539995 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0 156097931 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1 156545440 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2 159419095 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3 159741454 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu4 162402934 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu5 154349443 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu6 159730395 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu7 156156442 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 1264443134 # number of ReadExReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0 50090895 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1 50336063 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu2 50437231 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu3 51704240 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu4 47729417 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu5 53673691 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu6 48908906 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu7 47302737 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 400183180 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0 206188826 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1 206881503 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2 209856326 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3 211445694 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu4 210132351 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu5 208023134 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu6 208639301 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu7 203459179 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 1664626314 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0 206188826 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1 206881503 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2 209856326 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3 211445694 # number of overall miss cycles system.l2c.overall_miss_latency::cpu4 210132351 # number of overall miss cycles system.l2c.overall_miss_latency::cpu5 208023134 # number of overall miss cycles system.l2c.overall_miss_latency::cpu6 208639301 # number of overall miss cycles system.l2c.overall_miss_latency::cpu7 203459179 # number of overall miss cycles system.l2c.overall_miss_latency::total 1664626314 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 77703 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 77703 # number of WritebackDirty accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0 2277 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1 2423 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2 2383 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3 2315 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu4 2411 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu5 2379 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu6 2350 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu7 2364 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 18902 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0 6405 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1 6292 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2 6362 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3 6536 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu4 6545 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu5 6280 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu6 6445 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu7 6342 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 51207 # number of ReadExReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0 11514 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1 11548 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu2 11718 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu3 11555 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu4 11546 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu5 11474 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu6 11516 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu7 11585 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::total 92456 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0 17919 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1 17840 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2 18080 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3 18091 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu4 18091 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu5 17754 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu6 17961 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu7 17927 # number of demand (read+write) accesses system.l2c.demand_accesses::total 143663 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0 17919 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1 17840 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2 18080 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3 18091 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu4 18091 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu5 17754 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu6 17961 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu7 17927 # number of overall (read+write) accesses system.l2c.overall_accesses::total 143663 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0 0.872639 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1 0.880314 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2 0.876626 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3 0.885961 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu4 0.884280 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu5 0.878520 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu6 0.885957 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu7 0.862521 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.878373 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0 0.716472 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1 0.726796 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2 0.731374 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3 0.718482 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu4 0.726814 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu5 0.720701 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu6 0.721645 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu7 0.722170 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.723046 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0 0.061143 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1 0.061309 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu2 0.060591 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu3 0.062830 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu4 0.058115 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu5 0.066062 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu6 0.059830 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu7 0.058265 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.061013 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0 0.295385 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1 0.296020 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2 0.296626 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3 0.299707 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu4 0.300039 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu5 0.297623 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu6 0.297311 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu7 0.293133 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.296987 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0 0.295385 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1 0.296020 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2 0.296626 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3 0.299707 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu4 0.300039 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu5 0.297623 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu6 0.297311 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu7 0.293133 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.296987 # miss rate for overall accesses system.l2c.UpgradeReq_avg_miss_latency::cpu0 16624.810770 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1 17381.152836 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2 16995.691719 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu3 16658.946855 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu4 16849.436679 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu5 17551.913876 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu6 16878.721902 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu7 17171.652281 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 17017.406192 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0 34015.674657 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1 34232.547562 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2 34261.572104 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3 34016.493612 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu4 34139.780114 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu5 34102.837605 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu6 34343.236938 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu7 34095.293013 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 34151.063714 # average ReadExReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0 71151.839489 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1 71096.134181 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu2 71038.353521 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu3 71217.961433 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu4 71131.769001 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70809.618734 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70985.349782 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70078.128889 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 70941.886190 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0 38955.002078 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1 39174.683393 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2 39130.398285 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3 38997.730358 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu4 38712.665991 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu5 39368.496215 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu6 39071.030150 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu7 38717.255756 # average overall miss latency system.l2c.demand_avg_miss_latency::total 39015.288848 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0 38955.002078 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1 39174.683393 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2 39130.398285 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3 38997.730358 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu4 38712.665991 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu5 39368.496215 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu6 39071.030150 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu7 38717.255756 # average overall miss latency system.l2c.overall_avg_miss_latency::total 39015.288848 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 20827 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 3189 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs 6.530887 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 6244 # number of writebacks system.l2c.writebacks::total 6244 # number of writebacks system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 5 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 8 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu0 10 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu4 4 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu6 10 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu7 15 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::total 77 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2 20 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 21 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 112 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2 20 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 21 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 112 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 1208 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 1208 # number of CleanEvict MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0 1987 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1 2132 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2 2088 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu3 2051 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu4 2132 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu5 2088 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu6 2082 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu7 2039 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 16599 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0 4587 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1 4571 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2 4648 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3 4690 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu4 4753 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu5 4524 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu6 4643 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu7 4574 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 36990 # number of ReadExReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0 694 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1 699 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu2 695 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu3 722 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu4 667 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu5 748 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu6 679 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu7 660 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::total 5564 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0 5281 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1 5270 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2 5343 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3 5412 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu4 5420 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu5 5272 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu6 5322 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu7 5234 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 42554 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0 5281 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1 5270 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2 5343 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3 5412 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu4 5420 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu5 5272 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu6 5322 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu7 5234 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 42554 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0 9909 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1 9863 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 78849 # number of ReadReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu1 5525 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu3 5537 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu4 5496 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu5 5409 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu7 5416 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 43679 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0 15285 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1 15388 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu3 15310 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu4 15297 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu5 15174 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu7 15367 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 122528 # number of overall MSHR uncacheable misses system.l2c.UpgradeReq_mshr_miss_latency::cpu0 41114731 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1 44135575 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2 43262560 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3 42495420 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu4 44129731 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43370592 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu6 43201403 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu7 42227606 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 343937618 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0 110096109 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1 110716645 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2 112771891 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3 112546795 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu4 114695609 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu5 108961847 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu6 112947605 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu7 110110769 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 892847270 # number of ReadExReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 42686190 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 42892571 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42733862 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 44195932 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40778543 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 45766520 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41640903 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 39953551 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::total 340648072 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0 152782299 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1 153609216 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2 155505753 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3 156742727 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu4 155474152 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu5 154728367 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu6 154588508 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu7 150064320 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 1233495342 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0 152782299 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1 153609216 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2 155505753 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3 156742727 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu4 155474152 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu5 154728367 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu6 154588508 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu7 150064320 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 1233495342 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 531934603 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 529144419 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 536612256 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 524755063 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 526637223 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 524048250 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 524701912 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 534783521 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 4232617247 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0 531934603 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1 529144419 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu2 536612256 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu3 524755063 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu4 526637223 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu5 524048250 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu6 524701912 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu7 534783521 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 4232617247 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.872639 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.879901 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.876206 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885961 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884280 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877680 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.885957 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.862521 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.878161 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716159 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726478 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730588 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.717564 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.726203 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720382 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720403 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721224 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.722362 # mshr miss rate for ReadExReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060274 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060530 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.059310 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062484 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057769 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065191 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058961 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.056970 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060180 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.296207 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.296207 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20691.862607 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20701.489212 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.616858 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20719.366163 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20698.748124 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20771.356322 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20749.953410 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20709.958803 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20720.381830 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24001.767822 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 24221.536863 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 24262.455034 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23997.184435 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24131.203240 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 24085.288904 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24326.427956 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 24073.189550 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 24137.530954 # average ReadExReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61507.478386 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 61362.762518 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 61487.571223 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 61213.202216 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 61137.245877 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 61185.187166 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 61326.808542 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60535.683333 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 61223.593098 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53681.966192 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53649.439217 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53634.408396 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53694.368464 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53733.009183 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53665.975422 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53639.533020 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53741.686363 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53680.037122 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 34801.086228 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 34386.822134 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 34649.206173 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 34275.314370 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 34427.484016 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 34535.933175 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 34474.501445 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 34800.775753 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 34544.081736 # average overall mshr uncacheable latency system.membus.snoop_filter.tot_requests 125015 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 119335 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 78845 # Transaction distribution system.membus.trans_dist::ReadResp 84388 # Transaction distribution system.membus.trans_dist::WriteReq 43678 # Transaction distribution system.membus.trans_dist::WriteResp 43672 # Transaction distribution system.membus.trans_dist::WritebackDirty 6244 # Transaction distribution system.membus.trans_dist::CleanEvict 1238 # Transaction distribution system.membus.trans_dist::UpgradeReq 61417 # Transaction distribution system.membus.trans_dist::ReadExReq 49074 # Transaction distribution system.membus.trans_dist::ReadExResp 3109 # Transaction distribution system.membus.trans_dist::ReadSharedReq 5552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377217 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 377217 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1076434 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 1076434 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 56879 # Total snoops (count) system.membus.snoop_fanout::samples 245548 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 245548 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 245548 # Request fanout histogram system.membus.reqLayer0.occupancy 288762573 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 57.6 # Layer utilization (%) system.membus.respLayer0.occupancy 244649000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 48.8 # Layer utilization (%) system.toL2Bus.snoop_filter.tot_requests 663848 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 283900 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 334405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 12239 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 5805 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 6434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 78849 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 372013 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 43679 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 43671 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 83947 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 105636 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 29816 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 29815 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 162678 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 162674 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 293185 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133340 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 134024 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133820 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133857 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133294 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133675 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133694 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 1069251 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781172 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1779932 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1786043 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802764 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1783744 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780612 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1792304 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1782917 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 14289488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 336712 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 624467 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.150434 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.985907 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 172892 27.69% 27.69% # Request fanout histogram system.toL2Bus.snoop_fanout::1 258676 41.42% 69.11% # Request fanout histogram system.toL2Bus.snoop_fanout::2 133601 21.39% 90.50% # Request fanout histogram system.toL2Bus.snoop_fanout::3 46619 7.47% 97.97% # Request fanout histogram system.toL2Bus.snoop_fanout::4 10890 1.74% 99.71% # Request fanout histogram system.toL2Bus.snoop_fanout::5 1624 0.26% 99.97% # Request fanout histogram system.toL2Bus.snoop_fanout::6 162 0.03% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::total 624467 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 494463871 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 98.6 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 102665881 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 102599371 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 102945420 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 102767709 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%) system.toL2Bus.respLayer4.occupancy 102912196 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%) system.toL2Bus.respLayer5.occupancy 102768177 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 102966672 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%) system.toL2Bus.respLayer7.occupancy 102752542 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%) ---------- End Simulation Statistics ----------