blob: 4b8dc46181d7772566e1f7736b6d84e40f6d5934 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
|
---------- Begin Simulation Statistics ----------
sim_seconds 1.929078 # Number of seconds simulated
sim_ticks 1929077876500 # Number of ticks simulated
final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 169237 # Simulator instruction rate (inst/s)
host_op_rate 169237 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5749129790 # Simulator tick rate (ticks/s)
host_mem_usage 339544 # Number of bytes of host memory used
host_seconds 335.54 # Real time elapsed on the host
sim_insts 56786201 # Number of instructions simulated
sim_ops 56786201 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 26268288 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 856320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 123072 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 979392 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7871488 # Number of bytes written to this memory
system.physmem.bytes_written::total 7871488 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13380 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 384427 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1923 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10697 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 410442 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 122992 # Number of write requests responded to by this memory
system.physmem.num_writes::total 122992 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 443901 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12753932 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 63798 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 354889 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13617018 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 443901 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 63798 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 507700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4080441 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4080441 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4080441 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 443901 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12753932 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 63798 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 354889 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17697459 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 410442 # Number of read requests accepted
system.physmem.writeReqs 122992 # Number of write requests accepted
system.physmem.readBursts 410442 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 122992 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue
system.physmem.bytesWritten 7869440 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26268288 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7871488 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 26358 # Per bank write bursts
system.physmem.perBankRdBursts::1 25853 # Per bank write bursts
system.physmem.perBankRdBursts::2 25982 # Per bank write bursts
system.physmem.perBankRdBursts::3 25455 # Per bank write bursts
system.physmem.perBankRdBursts::4 25391 # Per bank write bursts
system.physmem.perBankRdBursts::5 25779 # Per bank write bursts
system.physmem.perBankRdBursts::6 25718 # Per bank write bursts
system.physmem.perBankRdBursts::7 25362 # Per bank write bursts
system.physmem.perBankRdBursts::8 25502 # Per bank write bursts
system.physmem.perBankRdBursts::9 25880 # Per bank write bursts
system.physmem.perBankRdBursts::10 25847 # Per bank write bursts
system.physmem.perBankRdBursts::11 25125 # Per bank write bursts
system.physmem.perBankRdBursts::12 25573 # Per bank write bursts
system.physmem.perBankRdBursts::13 25368 # Per bank write bursts
system.physmem.perBankRdBursts::14 25415 # Per bank write bursts
system.physmem.perBankRdBursts::15 25720 # Per bank write bursts
system.physmem.perBankWrBursts::0 8608 # Per bank write bursts
system.physmem.perBankWrBursts::1 7821 # Per bank write bursts
system.physmem.perBankWrBursts::2 8027 # Per bank write bursts
system.physmem.perBankWrBursts::3 7496 # Per bank write bursts
system.physmem.perBankWrBursts::4 7316 # Per bank write bursts
system.physmem.perBankWrBursts::5 7320 # Per bank write bursts
system.physmem.perBankWrBursts::6 7241 # Per bank write bursts
system.physmem.perBankWrBursts::7 6937 # Per bank write bursts
system.physmem.perBankWrBursts::8 7156 # Per bank write bursts
system.physmem.perBankWrBursts::9 7588 # Per bank write bursts
system.physmem.perBankWrBursts::10 7741 # Per bank write bursts
system.physmem.perBankWrBursts::11 7304 # Per bank write bursts
system.physmem.perBankWrBursts::12 7945 # Per bank write bursts
system.physmem.perBankWrBursts::13 8097 # Per bank write bursts
system.physmem.perBankWrBursts::14 8174 # Per bank write bursts
system.physmem.perBankWrBursts::15 8189 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 1929076824500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 410442 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 122992 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 318267 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 37921 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 29360 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 24678 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1676 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3020 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4727 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6854 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8917 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7788 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8406 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8757 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7842 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6881 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65334 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 522.399241 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 318.882184 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 410.899985 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14976 22.92% 22.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11360 17.39% 40.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5432 8.31% 48.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2850 4.36% 52.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2530 3.87% 56.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1671 2.56% 59.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3857 5.90% 65.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1188 1.82% 67.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 21470 32.86% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65334 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5522 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 74.304962 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2840.771031 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5519 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5522 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5522 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.267294 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 19.111227 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 20.252131 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4917 89.04% 89.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 44 0.80% 89.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 22 0.40% 90.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 38 0.69% 90.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 207 3.75% 94.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 6 0.11% 94.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 12 0.22% 95.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 27 0.49% 95.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 186 3.37% 98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 6 0.11% 98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 8 0.14% 99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 4 0.07% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 2 0.04% 99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 8 0.14% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 6 0.11% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 2 0.04% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 4 0.07% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 5 0.09% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 3 0.05% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 3 0.05% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 1 0.02% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 3 0.05% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 1 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 1 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 3 0.05% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5522 # Writes before turning the bus around for reads
system.physmem.totQLat 4416821750 # Total ticks spent queuing
system.physmem.totMemAccLat 12110471750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10764.12 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29514.12 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.08 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.62 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.08 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.77 # Average write queue length when enqueuing
system.physmem.readRowHits 369361 # Number of row buffer hits during reads
system.physmem.writeRowHits 98593 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.16 # Row buffer hit rate for writes
system.physmem.avgGap 3616336.46 # Average gap between requests
system.physmem.pageHitRate 87.74 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 246047760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 134252250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1606004400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 393763680 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 63271865610 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1101943260750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1293592968690 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.576874 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1832974418500 # Time in different power states
system.physmem_0.memoryStateTime::REF 64416040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 31684384000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 247877280 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 135250500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1594554000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 403017120 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 63221156415 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1101987750750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1293587380305 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.573972 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1833051648500 # Time in different power states
system.physmem_1.memoryStateTime::REF 64416040000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 31607167750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu0.branchPred.lookups 17100345 # Number of BP lookups
system.cpu0.branchPred.condPredicted 14625316 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 474432 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 10759421 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4832502 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 44.914145 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 945329 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 34555 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 5020643 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 507910 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 4512733 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 209375 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 9634816 # DTB read hits
system.cpu0.dtb.read_misses 36704 # DTB read misses
system.cpu0.dtb.read_acv 586 # DTB read access violations
system.cpu0.dtb.read_accesses 618265 # DTB read accesses
system.cpu0.dtb.write_hits 5807101 # DTB write hits
system.cpu0.dtb.write_misses 8981 # DTB write misses
system.cpu0.dtb.write_acv 421 # DTB write access violations
system.cpu0.dtb.write_accesses 195454 # DTB write accesses
system.cpu0.dtb.data_hits 15441917 # DTB hits
system.cpu0.dtb.data_misses 45685 # DTB misses
system.cpu0.dtb.data_acv 1007 # DTB access violations
system.cpu0.dtb.data_accesses 813719 # DTB accesses
system.cpu0.itb.fetch_hits 1375653 # ITB hits
system.cpu0.itb.fetch_misses 7396 # ITB misses
system.cpu0.itb.fetch_acv 601 # ITB acv
system.cpu0.itb.fetch_accesses 1383049 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 146500468 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 26225748 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 74880065 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 17100345 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 6285741 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 112740313 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1369370 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 398 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 30412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 147220 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 425638 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 504 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 8642043 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 322305 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 140254918 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.533885 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.795707 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 126345960 90.08% 90.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 903115 0.64% 90.73% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1906918 1.36% 92.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 803345 0.57% 92.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2649453 1.89% 94.55% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 589849 0.42% 94.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 700559 0.50% 95.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 843084 0.60% 96.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 5512635 3.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 140254918 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.116726 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.511125 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 20974212 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 107876486 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 8907132 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1841497 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 655590 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 626155 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 29675 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 64967024 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 87739 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 655590 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 21855511 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 78567360 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 18275925 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9798485 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 11102045 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 62456562 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 201631 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 2042440 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 306402 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 7083961 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 42144620 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 75447660 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 75312247 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 126226 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 34366321 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 7778299 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1457881 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 236313 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 12541674 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 10026235 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6171298 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1512964 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 977849 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 55240015 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1897630 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 53565100 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 74212 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 9657224 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 4199823 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1322202 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 140254918 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.381912 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.107336 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 118450817 84.45% 84.45% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 9324559 6.65% 91.10% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3896910 2.78% 93.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2805800 2.00% 95.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2901850 2.07% 97.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1433856 1.02% 98.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 954902 0.68% 99.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 366563 0.26% 99.91% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 119661 0.09% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 140254918 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 172960 16.73% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 530801 51.33% 68.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 330287 31.94% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3306 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 36704403 68.52% 68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 56318 0.11% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 27375 0.05% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 10076531 18.81% 87.50% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5896825 11.01% 98.51% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 798690 1.49% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 53565100 # Type of FU issued
system.cpu0.iq.rate 0.365631 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1034048 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019305 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 247915569 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 66533789 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 51792941 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 577809 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 279350 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 262536 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 54284218 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 311624 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 608466 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2001818 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 4069 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 18629 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 679305 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 18387 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 376944 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 655590 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 75078561 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 955285 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 60714699 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 160012 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 10026235 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6171298 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1682472 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 42874 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 711273 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18629 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 185912 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 515422 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 701334 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 52870028 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 9698038 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 695072 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 3577054 # number of nop insts executed
system.cpu0.iew.exec_refs 15531241 # number of memory reference insts executed
system.cpu0.iew.exec_branches 8401878 # Number of branches executed
system.cpu0.iew.exec_stores 5833203 # Number of stores executed
system.cpu0.iew.exec_rate 0.360886 # Inst execution rate
system.cpu0.iew.wb_sent 52244753 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 52055477 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 26703720 # num instructions producing a value
system.cpu0.iew.wb_consumers 36905470 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.355326 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.723571 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 10154720 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 575428 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 626255 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 138489248 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.363854 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.249176 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 120648787 87.12% 87.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7115506 5.14% 92.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 3823437 2.76% 95.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2034446 1.47% 96.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1589267 1.15% 97.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 580000 0.42% 98.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 430694 0.31% 98.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 453916 0.33% 98.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1813195 1.31% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 138489248 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 50389922 # Number of instructions committed
system.cpu0.commit.committedOps 50389922 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 13516410 # Number of memory references committed
system.cpu0.commit.loads 8024417 # Number of loads committed
system.cpu0.commit.membars 195679 # Number of memory barriers committed
system.cpu0.commit.branches 7630866 # Number of branches committed
system.cpu0.commit.fp_insts 253714 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 46654336 # Number of committed integer instructions.
system.cpu0.commit.function_calls 644656 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 2912807 5.78% 5.78% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 32876835 65.24% 71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 54961 0.11% 71.13% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.13% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 26901 0.05% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 1652 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.19% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 8220096 16.31% 87.50% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 5497981 10.91% 98.41% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 798689 1.59% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 50389922 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1813195 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 197034230 # The number of ROB reads
system.cpu0.rob.rob_writes 122856265 # The number of ROB writes
system.cpu0.timesIdled 490676 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 6245550 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3710936476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 47480420 # Number of Instructions Simulated
system.cpu0.committedOps 47480420 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 3.085492 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 3.085492 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.324097 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.324097 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 69229174 # number of integer regfile reads
system.cpu0.int_regfile_writes 37925510 # number of integer regfile writes
system.cpu0.fp_regfile_reads 125098 # number of floating regfile reads
system.cpu0.fp_regfile_writes 133204 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1692059 # number of misc regfile reads
system.cpu0.misc_regfile_writes 801866 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 1263704 # number of replacements
system.cpu0.dcache.tags.tagsinuse 506.064166 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10905904 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1264137 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 8.627154 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.064166 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988407 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.988407 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 433 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.845703 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 58069444 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 58069444 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6953524 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6953524 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3586613 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3586613 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 178977 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 178977 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184325 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 184325 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10540137 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 10540137 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10540137 # number of overall hits
system.cpu0.dcache.overall_hits::total 10540137 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1569058 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1569058 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1703592 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1703592 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20226 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 20226 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2959 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 2959 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3272650 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3272650 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3272650 # number of overall misses
system.cpu0.dcache.overall_misses::total 3272650 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54620758000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 54620758000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 110116261626 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 348212000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 348212000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46063500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 46063500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 164737019626 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 164737019626 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8522582 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8522582 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5290205 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5290205 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 199203 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 199203 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187284 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 187284 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13812787 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 13812787 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13812787 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 13812787 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184106 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.184106 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322028 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.322028 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101535 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101535 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015800 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015800 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236929 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.236929 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236929 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.236929 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks
system.cpu0.dcache.writebacks::total 741086 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 2009094 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 2009094 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 2009094 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 2009094 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1009199 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 1009199 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254357 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 254357 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14659 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14659 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2959 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2959 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263556 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1263556 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263556 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1263556 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10105 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17136 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43480023500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43480023500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17474692057 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17474692057 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 173733500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 173733500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.091477 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.091477 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements 911237 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.992675 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 196 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 9554008 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 9554008 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 7675800 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 7675800 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 7675800 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 7675800 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 7675800 # number of overall hits
system.cpu0.icache.overall_hits::total 7675800 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 966240 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 966240 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 966240 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 966240 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 966240 # number of overall misses
system.cpu0.icache.overall_misses::total 966240 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14731064486 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14731064486 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14731064486 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14731064486 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14731064486 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14731064486 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 8642040 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 8642040 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 8642040 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 8642040 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 8642040 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 8642040 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111807 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.111807 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111807 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.111807 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111807 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.111807 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 15245.761391 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks
system.cpu0.icache.writebacks::total 911237 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 911968 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 911968 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 911968 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 911968 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 911968 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 911968 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12931897989 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12931897989 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12931897989 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 12931897989 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12931897989 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 12931897989 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105527 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.105527 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency
system.cpu1.branchPred.lookups 4129053 # Number of BP lookups
system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 8217 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 1287279 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 153619 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1133660 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 37557 # Number of mispredicted indirect branches.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 2247369 # DTB read hits
system.cpu1.dtb.read_misses 13283 # DTB read misses
system.cpu1.dtb.read_acv 72 # DTB read access violations
system.cpu1.dtb.read_accesses 382556 # DTB read accesses
system.cpu1.dtb.write_hits 1356336 # DTB write hits
system.cpu1.dtb.write_misses 3091 # DTB write misses
system.cpu1.dtb.write_acv 71 # DTB write access violations
system.cpu1.dtb.write_accesses 152961 # DTB write accesses
system.cpu1.dtb.data_hits 3603705 # DTB hits
system.cpu1.dtb.data_misses 16374 # DTB misses
system.cpu1.dtb.data_acv 143 # DTB access violations
system.cpu1.dtb.data_accesses 535517 # DTB accesses
system.cpu1.itb.fetch_hits 615373 # ITB hits
system.cpu1.itb.fetch_misses 3011 # ITB misses
system.cpu1.itb.fetch_acv 117 # ITB acv
system.cpu1.itb.fetch_accesses 618384 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 16726806 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 6696452 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 16370488 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 4129053 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1187433 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 8741861 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 347188 # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles 25893 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 58137 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 49356 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 1820963 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 76422 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 15745356 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.039703 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.449166 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 12876670 81.78% 81.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 185062 1.18% 82.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 297924 1.89% 84.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 209767 1.33% 86.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 372753 2.37% 88.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 143050 0.91% 89.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 159866 1.02% 90.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 207293 1.32% 91.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 1292971 8.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 15745356 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.246852 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.978698 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 5498623 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 7777976 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 2045729 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 256320 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 166707 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 143442 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 7016 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 13354105 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 22028 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 166707 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 5670233 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 826473 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 5769862 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 2131801 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 1180278 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 12651091 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 3750 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 88341 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 32960 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 615086 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 8374295 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 15046844 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 14984377 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 56291 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 6609856 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1764431 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 476570 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 48769 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2080322 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 2346654 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 1454994 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 292964 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 152733 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 11085695 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 541496 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 10671183 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 25309 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2321405 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 1075261 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 398456 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 15745356 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.677735 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.406788 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 11382155 72.29% 72.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 1870956 11.88% 84.17% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 802175 5.09% 89.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 575742 3.66% 92.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 534921 3.40% 96.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 285738 1.81% 98.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 185455 1.18% 99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 78165 0.50% 99.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 30049 0.19% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 15745356 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 27488 9.05% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 170713 56.19% 65.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 105586 34.76% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 3991 0.04% 0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 6611083 61.95% 61.99% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 16524 0.15% 62.14% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 12068 0.11% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1990 0.02% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 2360403 22.12% 84.40% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 1384355 12.97% 97.37% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 280769 2.63% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 10671183 # Type of FU issued
system.cpu1.iq.rate 0.637969 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 303787 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 37199457 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 13849868 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 10195275 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 217360 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 103372 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 100900 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 10854739 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 116240 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 112250 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 494389 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 1075 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 4794 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 168808 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 442 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 89761 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 166707 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 440216 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 341566 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 12247032 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 53191 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 2346654 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 1454994 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 491166 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 5461 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 335179 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 4794 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 42007 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 137108 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 179115 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 10495256 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 2269179 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 175926 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 619841 # number of nop insts executed
system.cpu1.iew.exec_refs 3634984 # number of memory reference insts executed
system.cpu1.iew.exec_branches 1567515 # Number of branches executed
system.cpu1.iew.exec_stores 1365805 # Number of stores executed
system.cpu1.iew.exec_rate 0.627451 # Inst execution rate
system.cpu1.iew.wb_sent 10344393 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 10296175 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 4904906 # num instructions producing a value
system.cpu1.iew.wb_consumers 6922372 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.615549 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.708559 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 2337439 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 143040 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 155210 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 15327667 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.637432 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.616488 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 11807980 77.04% 77.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 1622081 10.58% 87.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 578152 3.77% 91.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 357481 2.33% 93.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 274261 1.79% 95.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 117588 0.77% 96.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 104376 0.68% 96.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 117710 0.77% 97.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 348038 2.27% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 15327667 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 9770342 # Number of instructions committed
system.cpu1.commit.committedOps 9770342 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 3138451 # Number of memory references committed
system.cpu1.commit.loads 1852265 # Number of loads committed
system.cpu1.commit.membars 45725 # Number of memory barriers committed
system.cpu1.commit.branches 1397481 # Number of branches committed
system.cpu1.commit.fp_insts 99132 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 9064844 # Number of committed integer instructions.
system.cpu1.commit.function_calls 152839 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 468541 4.80% 4.80% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 5805964 59.42% 64.22% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 16275 0.17% 64.39% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.39% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 12061 0.12% 64.51% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 1990 0.02% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 1897990 19.43% 83.96% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 1286752 13.17% 97.13% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 280769 2.87% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 9770342 # Class of committed instruction
system.cpu1.commit.bw_lim_events 348038 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 26989101 # The number of ROB reads
system.cpu1.rob.rob_writes 24630830 # The number of ROB writes
system.cpu1.timesIdled 131471 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 981450 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3841428948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 9305781 # Number of Instructions Simulated
system.cpu1.committedOps 9305781 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.797464 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.797464 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.556339 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.556339 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 13488576 # number of integer regfile reads
system.cpu1.int_regfile_writes 7349661 # number of integer regfile writes
system.cpu1.fp_regfile_reads 55714 # number of floating regfile reads
system.cpu1.fp_regfile_writes 55051 # number of floating regfile writes
system.cpu1.misc_regfile_reads 538402 # number of misc regfile reads
system.cpu1.misc_regfile_writes 228232 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 120114 # number of replacements
system.cpu1.dcache.tags.tagsinuse 486.559727 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 2854712 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 120626 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 23.665810 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 62007957000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.559727 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950312 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.950312 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 13510694 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 13510694 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 1801260 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1801260 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 972413 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 972413 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 37246 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 37246 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 33039 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 33039 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 2773673 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 2773673 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 2773673 # number of overall hits
system.cpu1.dcache.overall_hits::total 2773673 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 221542 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 221542 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 271468 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 271468 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5109 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5109 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3089 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 3089 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 493010 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 493010 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 493010 # number of overall misses
system.cpu1.dcache.overall_misses::total 493010 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2936746000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2936746000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12570320655 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 12570320655 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51167000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 51167000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47352500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 47352500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 15507066655 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 15507066655 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 15507066655 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 15507066655 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2022802 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2022802 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1243881 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1243881 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 42355 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 42355 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 36128 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 36128 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3266683 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3266683 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3266683 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 3266683 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109522 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.109522 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218243 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.218243 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120623 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120623 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085502 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085502 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.150921 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.150921 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.150921 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.150921 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks
system.cpu1.dcache.writebacks::total 79554 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 362730 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 362730 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 362730 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 362730 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 85141 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 85141 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45139 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 45139 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4420 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4420 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3085 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 3085 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 130280 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 130280 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 130280 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 130280 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2990 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3152 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1075350000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1075350000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2078906462 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2078906462 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39137500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39137500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.039881 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.039881 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8854.638009 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8854.638009 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency
system.cpu1.icache.tags.replacements 244089 # number of replacements
system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.916867 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 2065632 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 2065632 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 1565201 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1565201 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1565201 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1565201 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1565201 # number of overall hits
system.cpu1.icache.overall_hits::total 1565201 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 255762 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 255762 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 255762 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 255762 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 255762 # number of overall misses
system.cpu1.icache.overall_misses::total 255762 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3690348499 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 3690348499 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 3690348499 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 3690348499 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 3690348499 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 3690348499 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 1820963 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 1820963 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 1820963 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 1820963 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 1820963 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 1820963 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.140454 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.140454 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.140454 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.140454 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.140454 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.140454 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14428.838135 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14428.838135 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14428.838135 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14428.838135 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 721 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks
system.cpu1.icache.writebacks::total 244089 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 11093 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 11093 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 11093 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 11093 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 11093 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244669 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 244669 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 244669 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 244669 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 244669 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 244669 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3289647499 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3289647499 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3289647499 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3289647499 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3289647499 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3289647499 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.134362 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.134362 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7368 # Transaction distribution
system.iobus.trans_dist::ReadResp 7368 # Transaction distribution
system.iobus.trans_dist::WriteReq 54647 # Transaction distribution
system.iobus.trans_dist::WriteResp 54647 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11984 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 40576 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 124030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47936 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 74130 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2735754 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 12444500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 814000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 176000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 14015000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 6047501 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 215709165 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 27481000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41695 # number of replacements
system.iocache.tags.tagsinuse 0.551900 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1726981964000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.551900 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.034494 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.034494 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375543 # Number of tag accesses
system.iocache.tags.data_accesses 375543 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
system.iocache.overall_misses::total 41727 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles
system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
system.l2c.tags.replacements 345263 # number of replacements
system.l2c.tags.tagsinuse 65201.794559 # Cycle average of tags in use
system.l2c.tags.total_refs 4034348 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 410346 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 9.831576 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 11176866000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 52690.467957 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5287.969178 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6933.387030 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 211.163837 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 78.806558 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.803993 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.080688 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.105795 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003222 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.001202 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.994900 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65083 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 2881 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 4427 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6690 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 50867 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.993088 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 38726936 # Number of tag accesses
system.l2c.tags.data_accesses 38726936 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 820640 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 820640 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 876939 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 876939 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 168 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 310 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 478 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 64 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 92 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 147156 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 30074 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 177230 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 898431 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 242687 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1141118 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 728799 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 77527 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 806326 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 898431 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 875955 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 242687 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 107601 # number of demand (read+write) hits
system.l2c.demand_hits::total 2124674 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 898431 # number of overall hits
system.l2c.overall_hits::cpu0.data 875955 # number of overall hits
system.l2c.overall_hits::cpu1.inst 242687 # number of overall hits
system.l2c.overall_hits::cpu1.data 107601 # number of overall hits
system.l2c.overall_hits::total 2124674 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 2711 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1120 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 3831 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 434 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 447 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 881 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 111239 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 9907 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 121146 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 13382 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 1940 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 15322 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 273731 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 890 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 274621 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst 13382 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 384970 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1940 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 10797 # number of demand (read+write) misses
system.l2c.demand_misses::total 411089 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 13382 # number of overall misses
system.l2c.overall_misses::cpu0.data 384970 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1940 # number of overall misses
system.l2c.overall_misses::cpu1.data 10797 # number of overall misses
system.l2c.overall_misses::total 411089 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 2600500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 17055500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 19656000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2906500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 391500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 3298000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 15395495000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1589168500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 16984663500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1798650500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 264551500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 2063202000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 33996713000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 123865000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 34120578000 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1798650500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 49392208000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 264551500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1713033500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 53168443500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1798650500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 49392208000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 264551500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1713033500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 53168443500 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 820640 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 820640 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 876939 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 876939 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2879 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1430 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 4309 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 475 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 973 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 258395 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 39981 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 298376 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 911813 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 244627 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 1156440 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 1002530 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 78417 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 1080947 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 911813 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1260925 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 244627 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 118398 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2535763 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 911813 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1260925 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 244627 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 118398 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2535763 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941646 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783217 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.889069 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.871486 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.941053 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.905447 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.430500 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.247793 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.406018 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014676 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007930 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.013249 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273040 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.011350 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.254056 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014676 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.305308 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.007930 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.091192 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.162116 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014676 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.305308 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.007930 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.091192 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.162116 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 959.240133 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15228.125000 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5130.775255 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6697.004608 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 875.838926 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 3743.473326 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138400.156420 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 160408.650449 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 140199.952949 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 134408.197579 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 136366.752577 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 134656.180655 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124197.526038 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139174.157303 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 124246.062756 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 134408.197579 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 128301.446866 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 136366.752577 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 158658.284709 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 129335.602509 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 134408.197579 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 128301.446866 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 136366.752577 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 158658.284709 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 129335.602509 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.writebacks::writebacks 81472 # number of writebacks
system.l2c.writebacks::total 81472 # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 12 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 12 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2711 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1120 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 3831 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 434 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 447 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 881 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 111239 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 9907 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 121146 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13381 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1923 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 15304 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 273731 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 890 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 274621 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 13381 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 384970 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 1923 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 10797 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 411071 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 13381 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 384970 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 1923 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 10797 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 411071 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 7193 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 13095 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 20288 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187020000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 77299500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 264319500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29765500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 30815000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 60580500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14283104501 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1490098001 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 15773202502 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1664693504 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 243245008 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 1907938512 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31265371007 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 114963503 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 31380334510 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1664693504 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 45548475508 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 243245008 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1605061504 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 49061475524 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1664693504 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 45548475508 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 243245008 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1605061504 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 49061475524 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1471043500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30151000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1501194500 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1471043500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30151000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1501194500 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941646 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783217 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.889069 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.871486 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.941053 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.905447 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430500 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.247793 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.406018 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013234 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273040 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.011350 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254056 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.305308 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.091192 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.162109 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014675 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.305308 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007861 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.091192 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.162109 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68985.614165 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69017.410714 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68994.909945 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68584.101382 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68937.360179 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68763.337117 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128400.151934 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150408.600081 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130199.944711 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124669.270256 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114219.328490 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129172.475281 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114267.789098 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118316.948095 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 148658.099843 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 119350.368973 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118316.948095 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 148658.099843 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 119350.368973 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 85845.208917 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 9565.672589 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 73994.208399 # average overall mshr uncacheable latency
system.membus.trans_dist::ReadReq 7193 # Transaction distribution
system.membus.trans_dist::ReadResp 297247 # Transaction distribution
system.membus.trans_dist::WriteReq 13095 # Transaction distribution
system.membus.trans_dist::WriteResp 13095 # Transaction distribution
system.membus.trans_dist::WritebackDirty 122992 # Transaction distribution
system.membus.trans_dist::CleanEvict 263076 # Transaction distribution
system.membus.trans_dist::UpgradeReq 10346 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 5952 # Transaction distribution
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 121253 # Transaction distribution
system.membus.trans_dist::ReadExResp 120834 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 290100 # Transaction distribution
system.membus.trans_dist::BadAddressError 46 # Transaction distribution
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40576 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182230 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 92 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1222898 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1306335 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 74130 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31481536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 31555666 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 34213906 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 12142 # Total snoops (count)
system.membus.snoop_fanout::samples 875570 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 875570 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 875570 # Request fanout histogram
system.membus.reqLayer0.occupancy 36438999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1356482971 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 2177455750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 936113 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 5114760 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2557108 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 345514 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1336 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2266679 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13095 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13095 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 943643 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1155325 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 827144 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 10512 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 6044 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 16556 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 299688 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 299688 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1156637 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1102911 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 46 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2735017 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3843601 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 733385 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 384537 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7696540 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116675136 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128186756 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31277824 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12692238 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 288831954 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 463427 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3024601 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.120612 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.326035 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 2660134 87.95% 87.95% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 364147 12.04% 99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 303 0.01% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 17 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3024601 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 4550078915 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 295885 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1369499398 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1926492121 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 368355265 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 200907831 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 180918 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 63985 40.38% 40.38% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.08% 40.47% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1935 1.22% 41.69% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 191 0.12% 41.81% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 92196 58.19% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 158438 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 62993 49.19% 49.19% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1935 1.51% 50.81% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 191 0.15% 50.96% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 62802 49.04% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 128052 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1871632607000 97.04% 97.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 66355000 0.00% 97.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 578065000 0.03% 97.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 91849500 0.00% 97.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 56349581000 2.92% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1928718457500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.984496 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.681179 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.808215 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 7 3.68% 3.68% # number of syscalls executed
system.cpu0.kern.syscall::3 15 7.89% 11.58% # number of syscalls executed
system.cpu0.kern.syscall::4 4 2.11% 13.68% # number of syscalls executed
system.cpu0.kern.syscall::6 28 14.74% 28.42% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.53% 28.95% # number of syscalls executed
system.cpu0.kern.syscall::17 8 4.21% 33.16% # number of syscalls executed
system.cpu0.kern.syscall::19 7 3.68% 36.84% # number of syscalls executed
system.cpu0.kern.syscall::20 4 2.11% 38.95% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.53% 39.47% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.58% 41.05% # number of syscalls executed
system.cpu0.kern.syscall::33 6 3.16% 44.21% # number of syscalls executed
system.cpu0.kern.syscall::41 2 1.05% 45.26% # number of syscalls executed
system.cpu0.kern.syscall::45 31 16.32% 61.58% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.58% 63.16% # number of syscalls executed
system.cpu0.kern.syscall::48 8 4.21% 67.37% # number of syscalls executed
system.cpu0.kern.syscall::54 9 4.74% 72.11% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.53% 72.63% # number of syscalls executed
system.cpu0.kern.syscall::59 5 2.63% 75.26% # number of syscalls executed
system.cpu0.kern.syscall::71 21 11.05% 86.32% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.58% 87.89% # number of syscalls executed
system.cpu0.kern.syscall::74 5 2.63% 90.53% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.53% 91.05% # number of syscalls executed
system.cpu0.kern.syscall::90 2 1.05% 92.11% # number of syscalls executed
system.cpu0.kern.syscall::92 7 3.68% 95.79% # number of syscalls executed
system.cpu0.kern.syscall::97 2 1.05% 96.84% # number of syscalls executed
system.cpu0.kern.syscall::98 2 1.05% 97.89% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.53% 98.42% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.53% 98.95% # number of syscalls executed
system.cpu0.kern.syscall::147 2 1.05% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 190 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 292 0.18% 0.18% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3426 2.05% 2.23% # number of callpals executed
system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed
system.cpu0.kern.callpal::swpipl 151781 91.02% 93.28% # number of callpals executed
system.cpu0.kern.callpal::rdps 6336 3.80% 97.08% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.08% # number of callpals executed
system.cpu0.kern.callpal::wrusp 2 0.00% 97.08% # number of callpals executed
system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 97.09% # number of callpals executed
system.cpu0.kern.callpal::rti 4399 2.64% 99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys 318 0.19% 99.92% # number of callpals executed
system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 166759 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 6855 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1159 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1159
system.cpu0.kern.mode_good::user 1159
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.169074 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.289244 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1925885387000 99.90% 99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1988942000 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3427 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2571 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 58929 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 18404 37.04% 37.04% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1933 3.89% 40.93% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 292 0.59% 41.51% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 29063 58.49% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 49692 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 18019 47.45% 47.45% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1933 5.09% 52.55% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 292 0.77% 53.31% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 17727 46.69% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 37971 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1882485952500 97.58% 97.58% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 565596500 0.03% 97.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 145516500 0.01% 97.62% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 45879988500 2.38% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1929077054000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.979081 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.609951 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.764127 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 1 0.74% 0.74% # number of syscalls executed
system.cpu1.kern.syscall::3 15 11.03% 11.76% # number of syscalls executed
system.cpu1.kern.syscall::6 14 10.29% 22.06% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.74% 22.79% # number of syscalls executed
system.cpu1.kern.syscall::17 7 5.15% 27.94% # number of syscalls executed
system.cpu1.kern.syscall::19 3 2.21% 30.15% # number of syscalls executed
system.cpu1.kern.syscall::20 2 1.47% 31.62% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.21% 33.82% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.21% 36.03% # number of syscalls executed
system.cpu1.kern.syscall::33 5 3.68% 39.71% # number of syscalls executed
system.cpu1.kern.syscall::45 23 16.91% 56.62% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.21% 58.82% # number of syscalls executed
system.cpu1.kern.syscall::48 2 1.47% 60.29% # number of syscalls executed
system.cpu1.kern.syscall::54 1 0.74% 61.03% # number of syscalls executed
system.cpu1.kern.syscall::59 2 1.47% 62.50% # number of syscalls executed
system.cpu1.kern.syscall::71 33 24.26% 86.76% # number of syscalls executed
system.cpu1.kern.syscall::74 11 8.09% 94.85% # number of syscalls executed
system.cpu1.kern.syscall::90 1 0.74% 95.59% # number of syscalls executed
system.cpu1.kern.syscall::92 2 1.47% 97.06% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.21% 99.26% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.74% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 136 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 191 0.37% 0.37% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed
system.cpu1.kern.callpal::swpctx 1171 2.27% 2.65% # number of callpals executed
system.cpu1.kern.callpal::tbi 5 0.01% 2.66% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed
system.cpu1.kern.callpal::swpipl 44279 85.92% 88.59% # number of callpals executed
system.cpu1.kern.callpal::rdps 2440 4.73% 93.33% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.33% # number of callpals executed
system.cpu1.kern.callpal::wrusp 5 0.01% 93.34% # number of callpals executed
system.cpu1.kern.callpal::rdusp 1 0.00% 93.34% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.01% 93.34% # number of callpals executed
system.cpu1.kern.callpal::rti 3187 6.18% 99.53% # number of callpals executed
system.cpu1.kern.callpal::callsys 197 0.38% 99.91% # number of callpals executed
system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 51536 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1550 # number of protection mode switches
system.cpu1.kern.mode_switch::user 578 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 794
system.cpu1.kern.mode_good::user 578
system.cpu1.kern.mode_good::idle 216
system.cpu1.kern.mode_switch_good::kernel 0.512258 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.088670 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.347940 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 4980780500 0.26% 0.26% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 920793000 0.05% 0.31% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1923175472500 99.69% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1172 # number of times the context was actually changed
---------- End Simulation Statistics ----------
|