1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.832863 # Number of seconds simulated
sim_ticks 2832863135500 # Number of ticks simulated
final_tick 2832863135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 89708 # Simulator instruction rate (inst/s)
host_op_rate 108808 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2246897924 # Simulator tick rate (ticks/s)
host_mem_usage 584736 # Number of bytes of host memory used
host_seconds 1260.79 # Real time elapsed on the host
sim_insts 113102806 # Number of instructions simulated
sim_ops 137183832 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1320448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9385192 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10708200 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1320448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1320448 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8027392 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::total 8044916 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147164 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 170083 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 125428 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::total 129809 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 466118 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3312971 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3779992 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 466118 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 466118 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2833667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2839853 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2833667 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 466118 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3319156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6619845 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 170084 # Number of read requests accepted
system.physmem.writeReqs 129809 # Number of write requests accepted
system.physmem.readBursts 170084 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 129809 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10877056 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
system.physmem.bytesWritten 8057984 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10708264 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8044916 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11273 # Per bank write bursts
system.physmem.perBankRdBursts::1 10590 # Per bank write bursts
system.physmem.perBankRdBursts::2 10987 # Per bank write bursts
system.physmem.perBankRdBursts::3 11172 # Per bank write bursts
system.physmem.perBankRdBursts::4 12956 # Per bank write bursts
system.physmem.perBankRdBursts::5 9956 # Per bank write bursts
system.physmem.perBankRdBursts::6 10483 # Per bank write bursts
system.physmem.perBankRdBursts::7 10745 # Per bank write bursts
system.physmem.perBankRdBursts::8 10596 # Per bank write bursts
system.physmem.perBankRdBursts::9 10173 # Per bank write bursts
system.physmem.perBankRdBursts::10 10343 # Per bank write bursts
system.physmem.perBankRdBursts::11 9301 # Per bank write bursts
system.physmem.perBankRdBursts::12 10027 # Per bank write bursts
system.physmem.perBankRdBursts::13 11029 # Per bank write bursts
system.physmem.perBankRdBursts::14 10190 # Per bank write bursts
system.physmem.perBankRdBursts::15 10133 # Per bank write bursts
system.physmem.perBankWrBursts::0 8501 # Per bank write bursts
system.physmem.perBankWrBursts::1 7944 # Per bank write bursts
system.physmem.perBankWrBursts::2 8565 # Per bank write bursts
system.physmem.perBankWrBursts::3 8669 # Per bank write bursts
system.physmem.perBankWrBursts::4 7612 # Per bank write bursts
system.physmem.perBankWrBursts::5 7365 # Per bank write bursts
system.physmem.perBankWrBursts::6 7701 # Per bank write bursts
system.physmem.perBankWrBursts::7 8000 # Per bank write bursts
system.physmem.perBankWrBursts::8 7958 # Per bank write bursts
system.physmem.perBankWrBursts::9 7673 # Per bank write bursts
system.physmem.perBankWrBursts::10 7751 # Per bank write bursts
system.physmem.perBankWrBursts::11 6981 # Per bank write bursts
system.physmem.perBankWrBursts::12 7673 # Per bank write bursts
system.physmem.perBankWrBursts::13 8385 # Per bank write bursts
system.physmem.perBankWrBursts::14 7646 # Per bank write bursts
system.physmem.perBankWrBursts::15 7482 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
system.physmem.totGap 2832862903500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 166532 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 125428 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 150650 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 16386 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2178 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 724 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1889 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2915 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6620 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6351 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7046 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8385 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7879 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7515 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7295 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 366 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 302 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 228 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 224 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 61981 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 305.496459 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.645422 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.944153 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 23140 37.33% 37.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14875 24.00% 61.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6518 10.52% 71.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3622 5.84% 77.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2531 4.08% 81.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1654 2.67% 84.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1506 2.43% 86.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1111 1.79% 88.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7024 11.33% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 61981 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6159 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.593765 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 568.835471 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6158 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6159 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6159 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.442604 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.500292 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.099847 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5468 88.78% 88.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 102 1.66% 90.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 31 0.50% 90.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 55 0.89% 91.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 28 0.45% 92.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 20 0.32% 92.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 47 0.76% 93.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 12 0.19% 93.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 146 2.37% 95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 14 0.23% 96.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 5 0.08% 96.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 12 0.19% 96.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 62 1.01% 97.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.10% 97.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 7 0.11% 97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 23 0.37% 98.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 90 1.46% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.05% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 8 0.13% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 3 0.05% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 5 0.08% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6159 # Writes before turning the bus around for reads
system.physmem.totQLat 2118470000 # Total ticks spent queuing
system.physmem.totMemAccLat 5305107500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 849770000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12464.96 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 31214.96 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing
system.physmem.readRowHits 139692 # Number of row buffer hits during reads
system.physmem.writeRowHits 94186 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes
system.physmem.avgGap 9446245.51 # Average gap between requests
system.physmem.pageHitRate 79.05 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 242388720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 132255750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 687663600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 417033360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 83434510665 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1626525439500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1896467659275 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.454308 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2705731371250 # Time in different power states
system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 32529373750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 226187640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 123415875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 637969800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 398837520 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 82104234975 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1627692348000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1896211361490 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.363834 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2707689162500 # Time in different power states
system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30578679500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu.branchPred.lookups 46808005 # Number of BP lookups
system.cpu.branchPred.condPredicted 23978413 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1175283 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29454237 # Number of BTB lookups
system.cpu.branchPred.BTBHits 13525326 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 45.919798 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11724965 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 34889 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 7914908 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 7768670 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 146238 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60204 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.walker.walks 9709 # Table walker walks requested
system.cpu.checker.dtb.walker.walksShort 9709 # Table walker walks initiated with short descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 9709 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 9709 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 9709 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walkPageSizes::4K 6239 82.69% 82.69% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::1M 1306 17.31% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 7545 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9709 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9709 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7545 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7545 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17254 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 24576844 # DTB read hits
system.cpu.checker.dtb.read_misses 8297 # DTB read misses
system.cpu.checker.dtb.write_hits 19632942 # DTB write hits
system.cpu.checker.dtb.write_misses 1412 # DTB write misses
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 24585141 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19634354 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 44209786 # DTB hits
system.cpu.checker.dtb.misses 9709 # DTB misses
system.cpu.checker.dtb.accesses 44219495 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested
system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.inst_hits 115801229 # ITB inst hits
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
system.cpu.checker.itb.inst_accesses 115806054 # ITB inst accesses
system.cpu.checker.itb.hits 115801229 # DTB hits
system.cpu.checker.itb.misses 4825 # DTB misses
system.cpu.checker.itb.accesses 115806054 # DTB accesses
system.cpu.checker.numCycles 139034298 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 72355 # Table walker walks requested
system.cpu.dtb.walker.walksShort 72355 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29395 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23194 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 19766 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 52589 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 463.728156 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2807.068133 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-8191 51286 97.52% 97.52% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.24% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-24575 316 0.60% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-49151 23 0.04% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 52589 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17730 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 8394.043940 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 17507 98.74% 98.74% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535 217 1.22% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 17730 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 131327621316 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.619198 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.492781 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 131267451816 99.95% 99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 41041000 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 8807000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 6837500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 1021000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 576000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 474000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 131327621316 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6380 82.61% 82.61% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1343 17.39% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7723 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72355 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72355 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7723 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7723 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 80078 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 25411177 # DTB read hits
system.cpu.dtb.read_misses 62688 # DTB read misses
system.cpu.dtb.write_hits 19865478 # DTB write hits
system.cpu.dtb.write_misses 9667 # DTB write misses
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1317 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25473865 # DTB read accesses
system.cpu.dtb.write_accesses 19875145 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 45276655 # DTB hits
system.cpu.dtb.misses 72355 # DTB misses
system.cpu.dtb.accesses 45349010 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 12837 # Table walker walks requested
system.cpu.itb.walker.walksShort 12837 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3369 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7745 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 1723 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11114 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 758.457801 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 3142.171422 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.66% 94.66% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::4096-8191 120 1.08% 95.74% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-12287 234 2.11% 97.85% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383 132 1.19% 99.04% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479 45 0.40% 99.44% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 11114 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 5038 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12015.680826 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 9674.005789 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7624.491394 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 4083 81.04% 81.04% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 936 18.58% 99.62% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 5038 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 23953376916 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.632532 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.482296 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 8804085500 36.76% 36.76% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 15147384416 63.24% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 1819000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 23953376916 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12837 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 12837 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 16152 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 65992511 # ITB inst hits
system.cpu.itb.inst_misses 12837 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 3079 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 2160 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 66005348 # ITB inst accesses
system.cpu.itb.hits 65992511 # DTB hits
system.cpu.itb.misses 12837 # DTB misses
system.cpu.itb.accesses 66005348 # DTB accesses
system.cpu.numCycles 278422079 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 104965644 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184047232 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46808005 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33018961 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 161470061 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6057656 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 190492 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 8321 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 345001 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 554797 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 65991288 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1042618 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6254 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 270563337 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.829471 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.217030 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 171642539 63.44% 63.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29152189 10.77% 74.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14033587 5.19% 79.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55735022 20.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 270563337 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.168119 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.661037 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 77947938 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 121878006 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64302075 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3866348 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2568970 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3407378 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 156978056 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3511118 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2568970 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83705242 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11815574 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76555831 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62411209 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 33506511 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146428655 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 918489 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 467718 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 65503 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 18531 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 30749318 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150222579 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 676982359 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 163959933 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10887 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141740582 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8481991 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2839527 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2643996 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13883864 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26339284 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21214862 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1704584 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2138851 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143220356 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2117775 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143040703 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 261102 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8154295 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14292577 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 121903 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 270563337 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.528677 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865235 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 182376042 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45230245 16.72% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31877858 11.78% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10262059 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 817100 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 270563337 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 7341205 32.76% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5622623 25.09% 57.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9446888 42.15% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 95846012 67.01% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 114315 0.08% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 8579 0.01% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26129650 18.27% 85.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 20939810 14.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 143040703 # Type of FU issued
system.cpu.iq.rate 0.513755 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22410748 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156674 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 579280960 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153497939 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 139990284 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35633 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165425721 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23393 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 323902 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1435157 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 717 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18681 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 624055 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 88621 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6303 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 2568970 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1238473 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 546153 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145518660 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 26339284 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21214862 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1094251 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17896 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 509714 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18681 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 277446 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471378 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 748824 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142140939 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25734314 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 827514 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 180529 # number of nop insts executed
system.cpu.iew.exec_refs 46562087 # number of memory reference insts executed
system.cpu.iew.exec_branches 26490837 # Number of branches executed
system.cpu.iew.exec_stores 20827773 # Number of stores executed
system.cpu.iew.exec_rate 0.510523 # Inst execution rate
system.cpu.iew.wb_sent 141772110 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140001653 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63237844 # num instructions producing a value
system.cpu.iew.wb_consumers 95709593 # num instructions consuming a value
system.cpu.iew.wb_rate 0.502840 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660726 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7370888 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995872 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 715425 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 267671554 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.513087 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.118264 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 194234773 72.56% 72.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43288369 16.17% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15457266 5.77% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4372596 1.63% 96.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6412647 2.40% 98.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1623966 0.61% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 797879 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 412108 0.15% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1071950 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 267671554 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113257711 # Number of instructions committed
system.cpu.commit.committedOps 137338737 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 45494934 # Number of memory references committed
system.cpu.commit.loads 24904127 # Number of loads committed
system.cpu.commit.membars 814876 # Number of memory barriers committed
system.cpu.commit.branches 26024432 # Number of branches committed
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
system.cpu.commit.int_insts 120166310 # Number of committed integer instructions.
system.cpu.commit.function_calls 4884393 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 91722407 66.79% 66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 24904127 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20590807 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 137338737 # Class of committed instruction
system.cpu.commit.bw_lim_events 1071950 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389122780 # The number of ROB reads
system.cpu.rob.rob_writes 292297911 # The number of ROB writes
system.cpu.timesIdled 890833 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7858742 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5387304193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113102806 # Number of Instructions Simulated
system.cpu.committedOps 137183832 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.461673 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.461673 # CPI: Total CPI of All Threads
system.cpu.ipc 0.406228 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.406228 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155527774 # number of integer regfile reads
system.cpu.int_regfile_writes 88490356 # number of integer regfile writes
system.cpu.fp_regfile_reads 9528 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
system.cpu.cc_regfile_reads 502164459 # number of cc regfile reads
system.cpu.cc_regfile_writes 53130606 # number of cc regfile writes
system.cpu.misc_regfile_reads 347857043 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521711 # number of misc regfile writes
system.cpu.dcache.tags.replacements 838824 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40057266 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 839336 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.724947 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 179127418 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179127418 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23264892 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264892 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542105 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15542105 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345700 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345700 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441341 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441341 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38806997 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38806997 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39152697 # number of overall hits
system.cpu.dcache.overall_hits::total 39152697 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 704654 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 704654 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3607879 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3607879 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177723 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177723 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 27366 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 27366 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 4312533 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4312533 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4490256 # number of overall misses
system.cpu.dcache.overall_misses::total 4490256 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11719889500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11719889500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 232482188697 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 232482188697 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376930500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 376930500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 276000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 244202078197 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 244202078197 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244202078197 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244202078197 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23969546 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23969546 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19149984 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19149984 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523423 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523423 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468707 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468707 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43119530 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43119530 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43642953 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43642953 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029398 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029398 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188401 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188401 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339540 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339540 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058386 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058386 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.100013 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.100013 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102886 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102886 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16632.119452 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16632.119452 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64437.357433 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64437.357433 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13773.679018 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13773.679018 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55200 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55200 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56626.135544 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56626.135544 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.889903 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54384.889903 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 869086 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6864 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 126.615093 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 696811 # number of writebacks
system.cpu.dcache.writebacks::total 696811 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290488 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 290488 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307970 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3307970 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18888 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18888 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3598458 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3598458 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3598458 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3598458 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414166 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 414166 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299909 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 299909 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119577 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119577 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8478 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8478 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 714075 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 714075 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 833652 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 833652 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6390908000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6390908000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19966536471 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19966536471 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1698802000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1698802000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127413000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127413000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26357444471 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26357444471 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28056246471 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28056246471 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276240500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276240500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075717451 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075717451 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11351957951 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11351957951 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017279 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017279 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015661 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015661 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228452 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228452 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018088 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018088 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016560 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016560 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019102 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019102 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15430.788621 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15430.788621 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66575.316083 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66575.316083 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14206.762170 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14206.762170 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15028.662420 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.662420 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54200 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54200 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36911.311096 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36911.311096 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33654.626236 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33654.626236 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.370073 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.370073 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.807722 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.807722 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193343.290374 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193343.290374 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1886159 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154154 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64010374 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1886671 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 33.927682 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.154154 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 67874994 # Number of tag accesses
system.cpu.icache.tags.data_accesses 67874994 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 64010374 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64010374 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64010374 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64010374 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64010374 # number of overall hits
system.cpu.icache.overall_hits::total 64010374 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1977910 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1977910 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1977910 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1977910 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1977910 # number of overall misses
system.cpu.icache.overall_misses::total 1977910 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28157815494 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28157815494 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28157815494 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28157815494 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28157815494 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28157815494 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 65988284 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 65988284 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 65988284 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 65988284 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 65988284 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 65988284 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029974 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029974 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029974 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029974 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029974 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029974 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.145979 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14236.145979 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.145979 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14236.145979 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.145979 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14236.145979 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 5784 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.096774 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 1886159 # number of writebacks
system.cpu.icache.writebacks::total 1886159 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91199 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91199 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91199 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91199 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91199 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91199 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1886711 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1886711 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1886711 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1886711 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1886711 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1886711 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25184628997 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25184628997 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25184628997 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25184628997 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25184628997 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25184628997 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377605500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377605500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377605500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 377605500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028592 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028592 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028592 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13348.429620 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13348.429620 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13348.429620 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13348.429620 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13348.429620 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13348.429620 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 96795 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65029.426786 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5006508 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 162120 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 30.881495 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 49617.960434 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.737497 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.672901 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10365.912312 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5032.143644 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.757110 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000164 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000041 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158171 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.076784 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.992270 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65312 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2859 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6695 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55598 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 44296397 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44296397 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58090 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12107 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 70197 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 696811 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 696811 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1848237 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1848237 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 57 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 57 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 161756 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 161756 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1866721 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1866721 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 528738 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 528738 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 58090 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 12107 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1866721 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 690494 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2627412 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 58090 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 12107 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1866721 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 690494 # number of overall hits
system.cpu.l2cache.overall_hits::total 2627412 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 25 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2715 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2715 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 135513 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 135513 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19912 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19912 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13351 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 13351 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 19912 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148864 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 168801 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 19912 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148864 # number of overall misses
system.cpu.l2cache.overall_misses::total 168801 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2632000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 796000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3428000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2728500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 2728500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17603481500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 17603481500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2636949500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2636949500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1801415000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1801415000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2632000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 796000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2636949500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19404896500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22045274000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2632000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 796000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2636949500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19404896500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22045274000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 58109 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12113 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 70222 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 696811 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 696811 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1848237 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1848237 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2772 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2772 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 297269 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 297269 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1886633 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1886633 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542089 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 542089 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 58109 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12113 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1886633 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 839358 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2796213 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 58109 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12113 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1886633 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 839358 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2796213 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000327 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000356 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.979437 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.979437 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455860 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.455860 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010554 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010554 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024629 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024629 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000327 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010554 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.177355 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060368 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000327 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010554 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.177355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060368 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138526.315789 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132666.666667 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137120 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1004.972376 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1004.972376 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129902.529647 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129902.529647 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132430.167738 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132430.167738 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134927.346266 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134927.346266 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132666.666667 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132430.167738 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130353.184786 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 130599.190763 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132666.666667 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132430.167738 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130353.184786 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 130599.190763 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 89238 # number of writebacks
system.cpu.l2cache.writebacks::total 89238 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 25 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2715 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2715 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135513 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 135513 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19886 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19886 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13239 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13239 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19886 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148752 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 168663 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19886 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148752 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 168663 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61717 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2442000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 736000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3178000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 184658000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 184658000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 211500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 211500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16248351500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16248351500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2434936503 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2434936503 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655244000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655244000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2442000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 736000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2434936503 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17903595500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20341710003 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2442000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 736000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2434936503 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17903595500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20341710003 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887116000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227183500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756897000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756897000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644013000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984080500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000356 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.979437 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.979437 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455860 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455860 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010540 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024422 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024422 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177221 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060318 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177221 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060318 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127120 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.996317 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.996317 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119902.529647 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119902.529647 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122444.760284 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122444.760284 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125027.872196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125027.872196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122444.760284 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120358.687614 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120605.645595 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122444.760284 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120358.687614 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120605.645595 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.984580 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.143326 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172445.060721 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172445.060721 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181285.775113 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177974.958277 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 5483816 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757778 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2557705 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 822252 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1886159 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 149793 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2777 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 297269 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 297269 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886711 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 542312 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665508 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640654 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30972 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133892 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8471026 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241506672 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98506345 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48452 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232436 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 340293905 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 194298 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3054873 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.024677 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.155138 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2979489 97.53% 97.53% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 75384 2.47% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3054873 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5401857499 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2834033066 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1305567557 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 18867982 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 75841383 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43093000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6154500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 33075500 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 187134993 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36413 # number of replacements
system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328023 # Number of tag accesses
system.iocache.tags.data_accesses 328023 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses
system.iocache.demand_misses::total 223 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 223 # number of overall misses
system.iocache.overall_misses::total 223 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 28155877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28155877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4550151116 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4550151116 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28155877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28155877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28155877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28155877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 126259.538117 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126259.538117 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125611.503865 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125611.503865 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126259.538117 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126259.538117 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126259.538117 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126259.538117 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17005877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 17005877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737535612 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2737535612 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 17005877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 17005877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 17005877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 17005877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76259.538117 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76259.538117 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75572.427451 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75572.427451 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76259.538117 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76259.538117 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76259.538117 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76259.538117 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 34132 # Transaction distribution
system.membus.trans_dist::ReadResp 67504 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
system.membus.trans_dist::WritebackDirty 125428 # Transaction distribution
system.membus.trans_dist::CleanEvict 7780 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4584 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 133644 # Transaction distribution
system.membus.trans_dist::ReadExResp 133644 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33373 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450558 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558126 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 631001 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16435996 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16599385 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 18916505 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 487 # Total snoops (count)
system.membus.snoop_fanout::samples 402766 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 402766 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 402766 # Request fanout histogram
system.membus.reqLayer0.occupancy 83667000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1740000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 876048370 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 978678250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
|