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|
---------- Begin Simulation Statistics ----------
sim_seconds 47.381683 # Number of seconds simulated
sim_ticks 47381683294000 # Number of ticks simulated
final_tick 47381683294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 169119 # Simulator instruction rate (inst/s)
host_op_rate 198983 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9178439782 # Simulator tick rate (ticks/s)
host_mem_usage 757568 # Number of bytes of host memory used
host_seconds 5162.28 # Real time elapsed on the host
sim_insts 873041938 # Number of instructions simulated
sim_ops 1027205539 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 75648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 7273408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 37833736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 11654720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 106816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 96448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3691584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 15254352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 10772160 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 424448 # Number of bytes read from this memory
system.physmem.bytes_read::total 87268888 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 7273408 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3691584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10964992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 68656704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 68677288 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1182 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 113647 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 591165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 182105 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1669 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1507 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 57681 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 238362 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 168315 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6632 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1363602 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1072761 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1075335 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1806 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1597 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 798489 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 245975 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2254 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 77912 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 321946 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 227349 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8958 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1841828 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 77912 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 231418 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1449014 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1449448 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1449014 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1806 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1597 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 798923 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 245975 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2254 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 77912 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 321946 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 227349 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8958 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3291276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1363603 # Number of read requests accepted
system.physmem.writeReqs 1075335 # Number of write requests accepted
system.physmem.readBursts 1363603 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1075335 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 87237120 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue
system.physmem.bytesWritten 68675712 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 87268952 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 68677288 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 497625 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 80650 # Per bank write bursts
system.physmem.perBankRdBursts::1 88729 # Per bank write bursts
system.physmem.perBankRdBursts::2 73569 # Per bank write bursts
system.physmem.perBankRdBursts::3 80330 # Per bank write bursts
system.physmem.perBankRdBursts::4 79168 # Per bank write bursts
system.physmem.perBankRdBursts::5 89219 # Per bank write bursts
system.physmem.perBankRdBursts::6 76757 # Per bank write bursts
system.physmem.perBankRdBursts::7 80146 # Per bank write bursts
system.physmem.perBankRdBursts::8 80110 # Per bank write bursts
system.physmem.perBankRdBursts::9 145487 # Per bank write bursts
system.physmem.perBankRdBursts::10 85462 # Per bank write bursts
system.physmem.perBankRdBursts::11 91495 # Per bank write bursts
system.physmem.perBankRdBursts::12 74671 # Per bank write bursts
system.physmem.perBankRdBursts::13 80575 # Per bank write bursts
system.physmem.perBankRdBursts::14 75276 # Per bank write bursts
system.physmem.perBankRdBursts::15 81436 # Per bank write bursts
system.physmem.perBankWrBursts::0 65415 # Per bank write bursts
system.physmem.perBankWrBursts::1 72062 # Per bank write bursts
system.physmem.perBankWrBursts::2 62920 # Per bank write bursts
system.physmem.perBankWrBursts::3 67234 # Per bank write bursts
system.physmem.perBankWrBursts::4 65543 # Per bank write bursts
system.physmem.perBankWrBursts::5 71204 # Per bank write bursts
system.physmem.perBankWrBursts::6 63108 # Per bank write bursts
system.physmem.perBankWrBursts::7 65618 # Per bank write bursts
system.physmem.perBankWrBursts::8 64627 # Per bank write bursts
system.physmem.perBankWrBursts::9 73983 # Per bank write bursts
system.physmem.perBankWrBursts::10 67070 # Per bank write bursts
system.physmem.perBankWrBursts::11 71654 # Per bank write bursts
system.physmem.perBankWrBursts::12 63584 # Per bank write bursts
system.physmem.perBankWrBursts::13 67795 # Per bank write bursts
system.physmem.perBankWrBursts::14 63419 # Per bank write bursts
system.physmem.perBankWrBursts::15 67822 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
system.physmem.totGap 47381681282500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1363573 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1072761 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 866656 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 332331 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 37458 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 26767 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 22591 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 20794 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 18575 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 16649 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 13953 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2927 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1423 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 882 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 650 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 423 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 256 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 225 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 182 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 162 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 18197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 20578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 39692 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 50721 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 56749 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 59564 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 63294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 64512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 67826 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 69607 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 74517 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 70375 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 69942 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 75013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 68273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 64139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 61949 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1753 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 769 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 540 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 417 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 363 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 392 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 845070 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 184.496716 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 112.937858 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 245.074486 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 518646 61.37% 61.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 158346 18.74% 80.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 53030 6.28% 86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 28124 3.33% 89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 18210 2.15% 91.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11789 1.40% 93.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8638 1.02% 94.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8488 1.00% 95.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 39799 4.71% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 845070 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 60101 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 22.679190 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 352.199560 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 60098 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 60101 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 60101 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.854245 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.273539 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.223401 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 56328 93.72% 93.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1584 2.64% 96.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 235 0.39% 96.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 339 0.56% 97.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 81 0.13% 97.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 304 0.51% 97.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 166 0.28% 98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 108 0.18% 98.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 84 0.14% 98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 101 0.17% 98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 39 0.06% 98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 59 0.10% 98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 433 0.72% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 41 0.07% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 33 0.05% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 91 0.15% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 21 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 4 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 60101 # Writes before turning the bus around for reads
system.physmem.totQLat 33864601554 # Total ticks spent queuing
system.physmem.totMemAccLat 59422351554 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6815400000 # Total ticks spent in databus transfers
system.physmem.avgQLat 24844.18 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 43594.18 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.84 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
system.physmem.readRowHits 1093420 # Number of row buffer hits during reads
system.physmem.writeRowHits 497646 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 46.38 # Row buffer hit rate for writes
system.physmem.avgGap 19427177.44 # Average gap between requests
system.physmem.pageHitRate 65.31 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3178488600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1734294375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 5058697800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3454513920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1187868500820 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27387019861500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31683055542135 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.677294 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45560417443643 # Time in different power states
system.physmem_0.memoryStateTime::REF 1582178520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 239087007607 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3210233040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1751615250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 5573178000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3498901920 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1203743481615 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27373094439750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31685613034695 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.731270 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45537111526279 # Time in different power states
system.physmem_1.memoryStateTime::REF 1582178520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 262392956221 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 132357688 # Number of BP lookups
system.cpu0.branchPred.condPredicted 93633614 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5912907 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 98988393 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 72530253 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 73.271472 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 15763072 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 1049472 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 265700 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 265700 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9033 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73083 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 265700 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 265700 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 265700 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 82116 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22524.489746 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 20895.928471 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16961.244602 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 81335 99.05% 99.05% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 195 0.24% 99.29% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 500 0.61% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 82116 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 73083 89.00% 89.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 9033 11.00% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 82116 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 265700 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 265700 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 82116 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 82116 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 347816 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 86394812 # DTB read hits
system.cpu0.dtb.read_misses 220998 # DTB read misses
system.cpu0.dtb.write_hits 74903999 # DTB write hits
system.cpu0.dtb.write_misses 44702 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 37665 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 8673 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 10301 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 86615810 # DTB read accesses
system.cpu0.dtb.write_accesses 74948701 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 161298811 # DTB hits
system.cpu0.dtb.misses 265700 # DTB misses
system.cpu0.dtb.accesses 161564511 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 59769 # Table walker walks requested
system.cpu0.itb.walker.walksLong 59769 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 498 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49758 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 59769 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 59769 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 59769 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 50256 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25230.221267 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23083.004989 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 19430.494891 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 46691 92.91% 92.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 2859 5.69% 98.60% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 7 0.01% 98.61% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 383 0.76% 99.37% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 254 0.51% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 9 0.02% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 25 0.05% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 50256 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 49758 99.01% 99.01% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 498 0.99% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 50256 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59769 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59769 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50256 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50256 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 110025 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 238646690 # ITB inst hits
system.cpu0.itb.inst_misses 59769 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 27225 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 203945 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 238706459 # ITB inst accesses
system.cpu0.itb.hits 238646690 # DTB hits
system.cpu0.itb.misses 59769 # DTB misses
system.cpu0.itb.accesses 238706459 # DTB accesses
system.cpu0.numCycles 1007854766 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 441362500 # Number of instructions committed
system.cpu0.committedOps 518398273 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 43962057 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 93756283149 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.283508 # CPI: cycles per instruction
system.cpu0.ipc 0.437923 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 5202 # number of quiesce instructions executed
system.cpu0.tickCycles 710760418 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 297094348 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements 5529190 # number of replacements
system.cpu0.dcache.tags.tagsinuse 480.574807 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 153025870 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5529699 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.673454 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.574807 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938623 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 325514940 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 325514940 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 79084139 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 79084139 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 69445340 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 69445340 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 251787 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 251787 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143392 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 143392 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1790882 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1790882 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1762255 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1762255 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 148529479 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 148529479 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 148781266 # number of overall hits
system.cpu0.dcache.overall_hits::total 148781266 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3438422 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3438422 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 2286291 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2286291 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 632969 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 632969 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 749661 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 749661 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167888 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 167888 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194810 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 194810 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 5724713 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 5724713 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 6357682 # number of overall misses
system.cpu0.dcache.overall_misses::total 6357682 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57301041000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 57301041000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 58503452500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 58503452500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 69078584500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 69078584500 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2562226000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2562226000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5482087500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 5482087500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5099500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5099500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 115804493500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 115804493500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 115804493500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 115804493500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 82522561 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 82522561 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 71731631 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 71731631 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 884756 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 884756 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 893053 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 893053 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1958770 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 1958770 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1957065 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 1957065 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 154254192 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 154254192 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 155138948 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 155138948 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041666 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.041666 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031873 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.031873 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.715416 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.715416 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839436 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.839436 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085711 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085711 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037112 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.037112 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040981 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.040981 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16664.923910 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16664.923910 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25588.804094 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25588.804094 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92146.429519 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92146.429519 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15261.519584 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15261.519584 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28140.688363 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28140.688363 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20228.873220 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20228.873220 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18214.892393 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18214.892393 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 5529208 # number of writebacks
system.cpu0.dcache.writebacks::total 5529208 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 425438 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 425438 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 937459 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 937459 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 53 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 53 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41154 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41154 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 15 # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total 15 # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1362897 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1362897 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1362897 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1362897 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3012984 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3012984 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1348832 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1348832 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 631309 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 631309 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 749608 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 749608 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126734 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126734 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194795 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 194795 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4361816 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4361816 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4993125 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4993125 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15485 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16430 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31915 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44936822000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44936822000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34248227000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34248227000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15688131000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15688131000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 68324152500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 68324152500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1728085500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1728085500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5286161500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5286161500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5009500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5009500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79185049000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 79185049000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94873180000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 94873180000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2777500000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2777500000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2891122000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2891122000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5668622000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5668622000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036511 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.713540 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.713540 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.839377 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.839377 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099534 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099534 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028277 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028277 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032185 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032185 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14914.391182 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14914.391182 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25391.024976 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25391.024976 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24850.162123 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24850.162123 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91146.509242 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91146.509242 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13635.531901 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13635.531901 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27137.049206 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27137.049206 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18154.147034 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18154.147034 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19000.762048 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19000.762048 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179367.129480 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179367.129480 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175966.037736 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175966.037736 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177616.230613 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177616.230613 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 8961850 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 229474819 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 8962362 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 25.604279 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 485836753 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 485836753 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 229474819 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 229474819 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 229474819 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 229474819 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 229474819 # number of overall hits
system.cpu0.icache.overall_hits::total 229474819 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 8962372 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 8962372 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 8962372 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 8962372 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 8962372 # number of overall misses
system.cpu0.icache.overall_misses::total 8962372 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94471116000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 94471116000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 94471116000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 94471116000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 94471116000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 94471116000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 238437191 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 238437191 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 238437191 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 238437191 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 238437191 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 238437191 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037588 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.037588 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037588 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.037588 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037588 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.037588 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10540.860835 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10540.860835 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10540.860835 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10540.860835 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 8961850 # number of writebacks
system.cpu0.icache.writebacks::total 8961850 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8962372 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 8962372 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 8962372 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 8962372 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8962372 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 8962372 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89989930500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 89989930500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89989930500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 89989930500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89989930500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 89989930500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037588 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.037588 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.037588 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10040.860890 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7773827 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7774021 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 173 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1015459 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2700718 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16213.055668 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 22438549 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2716794 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 8.259201 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15223.315465 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 55.903430 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.295505 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 879.541268 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.929157 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003412 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003314 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053683 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.989566 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1224 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14798 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 814 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 215 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 997 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6189 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2013 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.074707 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903198 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 488653498 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 488653498 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 497387 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 151168 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 648555 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 3589798 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 3589798 # number of WritebackDirty hits
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system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7977745499 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7977745499 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3820823499 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3820823499 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4591998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4591998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14771566500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14771566500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 22450783500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 22450783500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32316263992 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32316263992 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 62472768000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 62472768000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 277497500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 22450783500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 47087830492 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 70180932992 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 277497500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 22450783500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 47087830492 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35765340066 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 105946273058 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2653464500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9649619500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2767850000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2767850000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5421314500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12417469500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028229 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998643 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998643 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.242429 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.242429 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079332 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260815 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.260815 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.775614 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.775614 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136550 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189248 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34093.365180 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46802.000652 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31159.903678 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31159.903678 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19615.493408 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19615.493408 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 510222 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 510222 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55365.484012 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55365.484012 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31576.214868 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32859.363553 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32859.363553 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107694.400725 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107694.400725 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35442.839203 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38605.937054 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171357.087504 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142337.367614 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168463.177115 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168463.177115 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169867.288109 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 147433.860895 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests 29837081 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15255646 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2671 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 2145858 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2145409 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 449 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 816702 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 13639128 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 16430 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 16430 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 5128977 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 10898588 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 2922524 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 983530 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 456186 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 346923 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 512261 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1174017 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1108975 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8962372 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4744543 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 755832 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 747915 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26989618 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17891664 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 337201 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1079102 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 46297585 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1150395968 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671911459 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1269832 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4069344 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1827646603 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 7092856 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 22718303 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.108382 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.310926 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 20256496 89.16% 89.16% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2461358 10.83% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 449 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 22718303 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 29677749987 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 177431926 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 13525621280 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 7933800899 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 178529385 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 570584194 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 131141392 # Number of BP lookups
system.cpu1.branchPred.condPredicted 92458444 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6313157 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 97645974 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 70218111 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 71.910913 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 15567912 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 1046402 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 286101 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 286101 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9457 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80855 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 286101 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 286101 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 286101 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 90312 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23344.699486 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21447.607691 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 19228.959334 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 89271 98.85% 98.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 163 0.18% 99.03% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 728 0.81% 99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 35 0.04% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 43 0.05% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 28 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 30 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 90312 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 80855 89.53% 89.53% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 9457 10.47% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 90312 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 286101 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 286101 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90312 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90312 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 376413 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 84597106 # DTB read hits
system.cpu1.dtb.read_misses 236435 # DTB read misses
system.cpu1.dtb.write_hits 75395592 # DTB write hits
system.cpu1.dtb.write_misses 49666 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 35920 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1878 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 8819 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 11434 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 84833541 # DTB read accesses
system.cpu1.dtb.write_accesses 75445258 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 159992698 # DTB hits
system.cpu1.dtb.misses 286101 # DTB misses
system.cpu1.dtb.accesses 160278799 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 70499 # Table walker walks requested
system.cpu1.itb.walker.walksLong 70499 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 664 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63113 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 70499 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 70499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 70499 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 63777 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26275.796917 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23950.266979 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 21020.894290 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 62694 98.30% 98.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 8 0.01% 98.31% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 977 1.53% 99.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.03% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 63777 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 63113 98.96% 98.96% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 664 1.04% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 63777 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 70499 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 70499 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63777 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63777 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 134276 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 232338774 # ITB inst hits
system.cpu1.itb.inst_misses 70499 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 25488 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 208774 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 232409273 # ITB inst accesses
system.cpu1.itb.hits 232338774 # DTB hits
system.cpu1.itb.misses 70499 # DTB misses
system.cpu1.itb.accesses 232409273 # DTB accesses
system.cpu1.numCycles 934140798 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 431679438 # Number of instructions committed
system.cpu1.committedOps 508807266 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 44929639 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 4564 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 93829974504 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.163969 # CPI: cycles per instruction
system.cpu1.ipc 0.462114 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 13472 # number of quiesce instructions executed
system.cpu1.tickCycles 702823433 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 231317365 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements 5070717 # number of replacements
system.cpu1.dcache.tags.tagsinuse 459.449189 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 152180192 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5071229 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 30.008543 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.449189 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897362 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.897362 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 322309894 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 322309894 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 77705355 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 77705355 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 70371137 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 70371137 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 247594 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 247594 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 180643 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 180643 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624088 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1624088 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1588942 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1588942 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 148076492 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 148076492 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 148324086 # number of overall hits
system.cpu1.dcache.overall_hits::total 148324086 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3222913 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3222913 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 2183254 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 2183254 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 592382 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 592382 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 513289 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 513289 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 153645 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 153645 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187516 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 187516 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 5406167 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 5406167 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 5998549 # number of overall misses
system.cpu1.dcache.overall_misses::total 5998549 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52049628500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 52049628500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 47596189000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 47596189000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20614887000 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 20614887000 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2521232500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2521232500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5224495500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 5224495500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4869500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4869500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 99645817500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 99645817500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 99645817500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 99645817500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 80928268 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 80928268 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 72554391 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 72554391 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 839976 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 839976 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 693932 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 693932 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1777733 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1777733 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1776458 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1776458 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 153482659 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 153482659 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 154322635 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 154322635 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039824 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.039824 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030091 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.030091 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.705237 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.705237 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739682 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739682 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086427 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086427 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105556 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105556 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035223 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.035223 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038870 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.038870 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16149.870785 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16149.870785 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21800.573364 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21800.573364 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40162.339345 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 40162.339345 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16409.466628 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16409.466628 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27861.598477 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27861.598477 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18431.879278 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18431.879278 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16611.653502 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16611.653502 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 5070732 # number of writebacks
system.cpu1.dcache.writebacks::total 5070732 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 348629 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 348629 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 899898 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 899898 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 110 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 110 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43396 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43396 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 20 # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total 20 # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1248527 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1248527 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1248527 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1248527 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2874284 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2874284 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1283356 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1283356 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 591957 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 591957 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 513179 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 513179 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 110249 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 110249 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187496 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 187496 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4157640 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4157640 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4749597 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 4749597 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22695 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22695 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21647 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44342 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44342 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41633767000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41633767000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28169318500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 28169318500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14402198000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14402198000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20089556500 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20089556500 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1594381500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1594381500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5035777500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5035777500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4638000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4638000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69803085500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 69803085500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84205283500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 84205283500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4145895000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4145895000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4016889500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4016889500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8162784500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8162784500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035516 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035516 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017688 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017688 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.704731 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.704731 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.739523 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739523 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062017 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062017 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105545 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105545 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027089 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.027089 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030777 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.030777 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14484.917635 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14484.917635 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21949.730628 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21949.730628 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24329.804361 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24329.804361 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39147.269276 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 39147.269276 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14461.641375 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14461.641375 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26858.052972 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26858.052972 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16789.112453 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16789.112453 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17728.932265 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17728.932265 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182678.783873 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182678.783873 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185563.334411 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185563.334411 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184086.971720 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 184086.971720 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 9965841 # number of replacements
system.cpu1.icache.tags.tagsinuse 506.684865 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 222156193 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 9966353 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 22.290621 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684865 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 474211445 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 474211445 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 222156193 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 222156193 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 222156193 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 222156193 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 222156193 # number of overall hits
system.cpu1.icache.overall_hits::total 222156193 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 9966353 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 9966353 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 9966353 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 9966353 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 9966353 # number of overall misses
system.cpu1.icache.overall_misses::total 9966353 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 101175482500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 101175482500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 101175482500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 101175482500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 101175482500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 101175482500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 232122546 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 232122546 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 232122546 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 232122546 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 232122546 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 232122546 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.042936 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.042936 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.042936 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.042936 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.042936 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.042936 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10151.705694 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10151.705694 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10151.705694 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10151.705694 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10151.705694 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10151.705694 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 9965841 # number of writebacks
system.cpu1.icache.writebacks::total 9965841 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9966353 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 9966353 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 9966353 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 9966353 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 9966353 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 9966353 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 96192306000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 96192306000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 96192306000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 96192306000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 96192306000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 96192306000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.042936 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.042936 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.042936 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9651.705694 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6510084 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6511152 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 939 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 783896 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2135895 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13423.461637 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 24573645 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2151628 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 11.420954 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9991507442000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12589.805999 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.598025 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.072993 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 692.984620 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.768421 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004460 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.042296 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.819303 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 945 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14692 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 44 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1194 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4753 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8241 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.057678 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896729 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 506241329 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 506241329 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 551867 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186859 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 738726 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3212995 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3212995 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 11821046 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 11821046 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 371 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 371 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 838525 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 838525 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 9300099 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 9300099 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2698124 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2698124 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 249185 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 249185 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 551867 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186859 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 9300099 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3536649 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 13575474 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 551867 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186859 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 9300099 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3536649 # number of overall hits
system.cpu1.l2cache.overall_hits::total 13575474 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10809 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8103 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 18912 # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 204693 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 204693 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 187493 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 187493 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 242458 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 242458 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 666254 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 666254 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 877979 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 877979 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 262039 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 262039 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10809 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8103 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 666254 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1120437 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1805603 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10809 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8103 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 666254 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1120437 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1805603 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 470190500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 378267000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 848457500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3269531500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 3269531500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1816771500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1816771500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4553499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4553499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12943476999 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 12943476999 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 25012449000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 25012449000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34434512490 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34434512490 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17540729000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 17540729000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 470190500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 378267000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 25012449000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 47377989489 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 73238895989 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 470190500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 378267000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 25012449000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 47377989489 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 73238895989 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 562676 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 194962 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 757638 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3212997 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3212997 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 11821046 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 11821046 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205064 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 205064 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187493 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 187493 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1080983 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1080983 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9966353 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 9966353 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3576103 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3576103 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 511224 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 511224 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 562676 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 194962 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 9966353 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4657086 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 15381077 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 562676 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 194962 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 9966353 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4657086 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 15381077 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.041562 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.024962 # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998191 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998191 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224294 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224294 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.066850 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.066850 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245513 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245513 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.512572 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.512572 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.041562 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.066850 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.240588 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.117391 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.041562 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.066850 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.240588 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.117391 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46682.339874 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44863.446489 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15972.854470 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15972.854470 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9689.809753 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9689.809753 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1517833 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1517833 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53384.408842 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53384.408842 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37541.911943 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37541.911943 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39220.200586 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39220.200586 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 66939.383069 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 66939.383069 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46682.339874 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37541.911943 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42285.277520 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 40562.015010 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46682.339874 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37541.911943 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42285.277520 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 40562.015010 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 1050489 # number of writebacks
system.cpu1.l2cache.writebacks::total 1050489 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5853 # number of ReadExReq MSHR hits
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system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 8 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1181 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1181 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7034 # number of demand (read+write) MSHR hits
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system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7034 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 7045 # number of overall MSHR hits
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system.cpu1.l2cache.ReadReq_mshr_misses::total 18909 # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 706258 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 706258 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 204693 # number of UpgradeReq MSHR misses
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system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 666246 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1113403 # number of demand (read+write) MSHR misses
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system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 666246 # number of overall MSHR misses
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system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22695 # number of ReadReq MSHR uncacheable
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system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
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system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44342 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44434 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 329621500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 734958000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32803670450 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32803670450 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6637113997 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6637113997 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3625235500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3625235500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4217499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4217499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10699007999 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10699007999 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 21014773500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 21014773500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29089304990 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29089304990 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15968495000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15968495000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 329621500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 21014773500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39788312989 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 61538044489 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 329621500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 21014773500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39788312989 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32803670450 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 94341714939 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3964210500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3976425000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3854486000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3854486000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7818696500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7830911000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024958 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998191 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998191 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.218879 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.218879 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.066850 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245183 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245183 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.512572 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.512572 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.116933 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.162850 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38868.158020 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46447.148846 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32424.723840 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32424.723840 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19335.311185 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19335.311185 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1405833 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1405833 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45218.858431 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45218.858431 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31542.063292 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33176.746514 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33176.746514 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60939.383069 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60939.383069 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34215.212681 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37664.129796 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174673.298083 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174504.103217 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178060.978427 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178060.978427 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 176327.105228 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 176236.913175 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests 30858357 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15723821 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1980391 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1980008 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 383 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 850137 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 14487242 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 21647 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 21647 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4268815 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 11821046 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 2688015 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 913599 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 423664 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342986 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 458900 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1168045 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1089891 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9966353 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4640105 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 517058 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 511224 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 29897221 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16450144 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405579 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179409 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 47932353 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1275569664 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 629289128 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1559696 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4501408 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1910919896 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 6428198 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 22587485 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.100846 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.301181 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 20310003 89.92% 89.92% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2277099 10.08% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 383 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 22587485 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 30765191484 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 188815582 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 14953353610 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 7474900412 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 210684864 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 616864733 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 40414 # Transaction distribution
system.iobus.trans_dist::ReadResp 40414 # Transaction distribution
system.iobus.trans_dist::WriteReq 136987 # Transaction distribution
system.iobus.trans_dist::WriteResp 136987 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47846 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122988 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231734 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231734 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 354802 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47866 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 156003 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355288 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7355288 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7513377 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 47239500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 315000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 26112500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 36405000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 566670204 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92988000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 148174000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115848 # number of replacements
system.iocache.tags.tagsinuse 11.264479 # Cycle average of tags in use
system.iocache.tags.total_refs 11 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115864 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000095 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9145999585000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 7.415083 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 3.849396 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.463443 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.240587 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.704030 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1043144 # Number of tag accesses
system.iocache.tags.data_accesses 1043144 # Number of data accesses
system.iocache.WriteLineReq_hits::realview.ide 6 # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total 6 # number of WriteLineReq hits
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106978 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106978 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8883 # number of demand (read+write) misses
system.iocache.demand_misses::total 8923 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8883 # number of overall misses
system.iocache.overall_misses::total 8923 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5243500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1665415552 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1670659052 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 14002624152 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 14002624152 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5612500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1665415552 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1671028052 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5612500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1665415552 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1671028052 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8883 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8923 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8883 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8923 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 0.999944 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 0.999944 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141716.216216 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 187483.457391 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 187293.615695 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130892.558769 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130892.558769 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 187271.999552 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 187271.999552 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 35141 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3655 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.614501 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106943 # number of writebacks
system.iocache.writebacks::total 106943 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106978 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106978 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8883 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8923 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8883 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8923 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3393500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1221265552 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1224659052 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8653724152 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8653724152 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3612500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1221265552 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1224878052 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3612500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1221265552 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1224878052 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999944 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.999944 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91716.216216 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137483.457391 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 137293.615695 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80892.558769 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80892.558769 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1253630 # number of replacements
system.l2c.tags.tagsinuse 63075.564404 # Cycle average of tags in use
system.l2c.tags.total_refs 6221998 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1313632 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.736485 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 23067.685004 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.868876 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 206.473413 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5441.439609 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6307.681817 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8428.958067 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 140.047033 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 198.225362 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4720.872050 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 6856.377655 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7560.935517 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.351985 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002241 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003151 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.083030 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.096248 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.128616 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002137 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003025 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.072035 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.104620 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.115371 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.962457 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 9537 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 50225 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 233 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 325 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 1551 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 7383 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 11674 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 35545 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.145523 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.766373 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 75571866 # Number of tag accesses
system.l2c.tags.data_accesses 75571866 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 2585563 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2585563 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 160084 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 122219 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 282303 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 41093 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 37320 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 78413 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 164973 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 176191 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 341164 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5942 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3808 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 649495 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 595249 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 326607 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6405 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4811 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 608519 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 523825 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 313790 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 3038451 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 5942 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3808 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 649495 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 760222 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 326607 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6405 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4811 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 608519 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 700016 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 313790 # number of demand (read+write) hits
system.l2c.demand_hits::total 3379615 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 5942 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3808 # number of overall hits
system.l2c.overall_hits::cpu0.inst 649495 # number of overall hits
system.l2c.overall_hits::cpu0.data 760222 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 326607 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6405 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4811 # number of overall hits
system.l2c.overall_hits::cpu1.inst 608519 # number of overall hits
system.l2c.overall_hits::cpu1.data 700016 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 313790 # number of overall hits
system.l2c.overall_hits::total 3379615 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 64947 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 58762 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 123709 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 12100 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 11098 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 23198 # number of SCUpgradeReq misses
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3486351500 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4862884000 # number of overall MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7041952000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 17812781000 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.288614 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.324686 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.304693 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.227474 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.229212 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228302 # mshr miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.439009 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.643834 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.163993 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167515 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.186681 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.279962 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.279962 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73377.861964 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73523.799428 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73447.182525 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76403.760331 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76486.574158 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76443.378740 # average SCUpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 125228.249202 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 128509.558709 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127658.044796 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128778.627801 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140016.532293 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153344.559251 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156682.699511 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130693.494077 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151451.217285 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161054.718899 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156910.864827 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152369.857434 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 158817.140280 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 138452.781060 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 90579 # Transaction distribution
system.membus.trans_dist::ReadResp 797028 # Transaction distribution
system.membus.trans_dist::WriteReq 38077 # Transaction distribution
system.membus.trans_dist::WriteResp 38077 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1072761 # Transaction distribution
system.membus.trans_dist::CleanEvict 234796 # Transaction distribution
system.membus.trans_dist::UpgradeReq 432847 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 303767 # Transaction distribution
system.membus.trans_dist::UpgradeResp 155875 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 628014 # Transaction distribution
system.membus.trans_dist::ReadExResp 607752 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 706453 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106976 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106976 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122988 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24302 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4826718 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4974060 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342886 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 342886 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5316946 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156003 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48604 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 148677184 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 148883115 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7268800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 156151915 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 604039 # Total snoops (count)
system.membus.snoop_fanout::samples 3616779 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3616779 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3616779 # Request fanout histogram
system.membus.reqLayer0.occupancy 110163500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 20375999 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 7677665405 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 7558802547 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 229140974 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests 11857284 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6410159 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2032721 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 132920 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 118959 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 13961 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 90581 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4604579 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38077 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38077 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 3658344 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1620073 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 706187 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 382180 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1088365 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1100091 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1100091 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4521240 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 106976 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8903542 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7167245 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 16070787 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267379155 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202223448 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 469602603 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2985982 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 8314965 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.369241 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.486066 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 5258700 63.24% 63.24% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3042304 36.59% 99.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 13961 0.17% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 8314965 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 8970776631 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2598924 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 5002984602 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4113788553 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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