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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.062555 # Number of seconds simulated
sim_ticks 62555455500 # Number of ticks simulated
final_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 428742 # Simulator instruction rate (inst/s)
host_op_rate 430877 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 296018745 # Simulator tick rate (ticks/s)
host_mem_usage 404460 # Number of bytes of host memory used
host_seconds 211.32 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory
system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15575 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 993 # Per bank write bursts
system.physmem.perBankRdBursts::1 891 # Per bank write bursts
system.physmem.perBankRdBursts::2 949 # Per bank write bursts
system.physmem.perBankRdBursts::3 1027 # Per bank write bursts
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
system.physmem.perBankRdBursts::10 938 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 904 # Per bank write bursts
system.physmem.perBankRdBursts::13 867 # Per bank write bursts
system.physmem.perBankRdBursts::14 876 # Per bank write bursts
system.physmem.perBankRdBursts::15 906 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 62555354500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 15575 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
system.physmem.totQLat 211097500 # Total ticks spent queuing
system.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14028 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 4016395.15 # Average gap between requests
system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ)
system.physmem_0.averagePower 252.613756 # Core power per rank (mW)
system.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states
system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states
system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ)
system.physmem_1.averagePower 254.503090 # Core power per rank (mW)
system.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states
system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 20806620 # Number of BP lookups
system.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8843232 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 24793 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 1418 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 125110911 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602850 # Number of instructions committed
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.380872 # CPI: cycles per instruction
system.cpu.ipc 0.724180 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction
system.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91054081 # Class of committed instruction
system.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked
system.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 946104 # number of replacements
system.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits
system.cpu.dcache.overall_hits::total 26266839 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses
system.cpu.dcache.overall_misses::total 980819 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks
system.cpu.dcache.writebacks::total 943285 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
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system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34134.686939 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34134.686939 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.629259 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.629259 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.766681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.766681 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 689.583421 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27839479 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34712.567332 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 689.583421 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.336711 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.336711 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55681364 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55681364 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
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system.cpu.icache.ReadReq_hits::total 27839479 # number of ReadReq hits
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system.cpu.icache.demand_hits::total 27839479 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27839479 # number of overall hits
system.cpu.icache.overall_hits::total 27839479 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.icache.overall_misses::total 802 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 71421000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 71421000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 71421000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 71421000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 71421000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 71421000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27840281 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27840281 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 27840281 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27840281 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27840281 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89053.615960 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 89053.615960 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 89053.615960 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 89053.615960 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 5 # number of writebacks
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70619000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 70619000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70619000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 70619000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70619000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 70619000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88053.615960 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88053.615960 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 11308.105127 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1881379 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15575 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 120.794799 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.588306 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.516821 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 15575 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475311 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15191263 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15191263 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 943285 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 943285 # number of WritebackDirty hits
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system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
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system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903173 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 903173 # number of ReadSharedReq hits
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system.cpu.l2cache.demand_hits::cpu.data 935393 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 935393 # number of overall hits
system.cpu.l2cache.overall_hits::total 935420 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses
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system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses
system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
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system.cpu.l2cache.ReadExReq_miss_latency::total 1182333500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69109000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 69109000 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadSharedReq_miss_latency::total 49239000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 69109000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1231572500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1300681500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 1231572500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1300681500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 943285 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 943285 # number of WritebackDirty accesses(hits+misses)
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system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses)
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system.cpu.l2cache.ReadSharedReq_accesses::total 903436 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966334 # miss rate for ReadCleanReq accesses
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system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses
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system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81293.557481 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81293.557481 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89172.903226 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89172.903226 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187220.532319 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187220.532319 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 83473.334617 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 83473.334617 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036893500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036893500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61295500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61295500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46236000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46236000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61295500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083129500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1144425000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61295500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083129500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1144425000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71293.557481 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 15575 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15575 # Request fanout histogram
system.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
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