1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.452564 # Number of seconds simulated
sim_ticks 452563515000 # Number of ticks simulated
final_tick 452563515000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 57394 # Simulator instruction rate (inst/s)
host_op_rate 70660 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40544083 # Simulator tick rate (ticks/s)
host_mem_usage 306292 # Number of bytes of host memory used
host_seconds 11162.26 # Real time elapsed on the host
sim_insts 640649299 # Number of instructions simulated
sim_ops 788724958 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 234304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 48000768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 12823616 # Number of bytes read from this memory
system.physmem.bytes_read::total 61058688 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 234304 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 234304 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4243456 # Number of bytes written to this memory
system.physmem.bytes_written::total 4243456 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3661 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 750012 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 200369 # Number of read requests responded to by this memory
system.physmem.num_reads::total 954042 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66304 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66304 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 517726 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 106064158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 28335506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 134917389 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 517726 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 517726 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 9376487 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 9376487 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 9376487 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 517726 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 106064158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 28335506 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 144293877 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 954043 # Number of read requests accepted
system.physmem.writeReqs 66304 # Number of write requests accepted
system.physmem.readBursts 954043 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66304 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 61040512 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue
system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 61058752 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4243456 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 53 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 19632 # Per bank write bursts
system.physmem.perBankRdBursts::1 19241 # Per bank write bursts
system.physmem.perBankRdBursts::2 656774 # Per bank write bursts
system.physmem.perBankRdBursts::3 20103 # Per bank write bursts
system.physmem.perBankRdBursts::4 19565 # Per bank write bursts
system.physmem.perBankRdBursts::5 20788 # Per bank write bursts
system.physmem.perBankRdBursts::6 19429 # Per bank write bursts
system.physmem.perBankRdBursts::7 19781 # Per bank write bursts
system.physmem.perBankRdBursts::8 19292 # Per bank write bursts
system.physmem.perBankRdBursts::9 19805 # Per bank write bursts
system.physmem.perBankRdBursts::10 19337 # Per bank write bursts
system.physmem.perBankRdBursts::11 19452 # Per bank write bursts
system.physmem.perBankRdBursts::12 19407 # Per bank write bursts
system.physmem.perBankRdBursts::13 20952 # Per bank write bursts
system.physmem.perBankRdBursts::14 19359 # Per bank write bursts
system.physmem.perBankRdBursts::15 20841 # Per bank write bursts
system.physmem.perBankWrBursts::0 4254 # Per bank write bursts
system.physmem.perBankWrBursts::1 4107 # Per bank write bursts
system.physmem.perBankWrBursts::2 4140 # Per bank write bursts
system.physmem.perBankWrBursts::3 4154 # Per bank write bursts
system.physmem.perBankWrBursts::4 4243 # Per bank write bursts
system.physmem.perBankWrBursts::5 4230 # Per bank write bursts
system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
system.physmem.perBankWrBursts::7 4093 # Per bank write bursts
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4155 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 452563504500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 954043 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66304 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 760089 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 121450 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 14329 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 8751 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 9237 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 8035 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 3854 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 2788 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1992 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1474 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 900 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1786 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3816 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4468 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4997 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4895 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 77 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 205577 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 317.529062 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 201.622998 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 287.021434 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 59787 29.08% 29.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 62582 30.44% 59.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 15931 7.75% 67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3214 1.56% 68.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3392 1.65% 70.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 47997 23.35% 93.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7735 3.76% 97.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 205577 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 209.250931 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 40.553257 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2756.803776 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 4005 99.40% 99.40% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.70% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.78% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671 2 0.05% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::61440-65535 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::94208-98303 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::114688-118783 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.396271 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.276876 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3401 84.41% 84.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 9 0.22% 84.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 462 11.47% 96.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 50 1.24% 97.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 36 0.89% 98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 16 0.40% 98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 18 0.45% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 10 0.25% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 6 0.15% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 6 0.15% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 4 0.10% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 4 0.10% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads
system.physmem.totQLat 15078460254 # Total ticks spent queuing
system.physmem.totMemAccLat 32961422754 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4768790000 # Total ticks spent in databus transfers
system.physmem.avgQLat 15809.52 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 34559.52 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 134.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 9.37 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 134.92 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.13 # Data bus utilization in percentage
system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing
system.physmem.readRowHits 788510 # Number of row buffer hits during reads
system.physmem.writeRowHits 25885 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes
system.physmem.avgGap 443538.82 # Average gap between requests
system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1031660280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 562909875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 6203308800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 216399600 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 305467849845 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 3582027000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 346623188280 # Total energy per rank (pJ)
system.physmem_0.averagePower 765.915744 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 4235605578 # Time in different power states
system.physmem_0.memoryStateTime::REF 15111980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 433212896922 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 522411120 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 285045750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1235535600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 212738400 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 96975747585 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 186469836000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 315260347335 # Total energy per rank (pJ)
system.physmem_1.averagePower 696.614859 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 309568131397 # Time in different power states
system.physmem_1.memoryStateTime::REF 15111980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 127880371103 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 234612924 # Number of BP lookups
system.cpu.branchPred.condPredicted 162473080 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15514448 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 121580360 # Number of BTB lookups
system.cpu.branchPred.BTBHits 107626063 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 88.522573 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 25035646 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1300027 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 905127031 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 85998683 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1202051079 # Number of instructions fetch has processed
system.cpu.fetch.Branches 234612924 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 132661709 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 803240111 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 31064493 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1917 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 3269 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 370084311 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 652880 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 904776257 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.657297 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.229901 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 222804793 24.63% 24.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 224059137 24.76% 49.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 98313262 10.87% 60.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 359599065 39.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 904776257 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.259204 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.328047 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 121900634 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 244061321 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 484657119 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 38638613 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 15518570 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 24546046 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 13813 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1248144936 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 39968729 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 15518570 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 178911503 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 163289745 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 206869 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 464319515 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 82530055 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1190655236 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 24276259 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 24947259 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2269584 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 41529012 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 1706231 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 1226042317 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5813738555 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1358185798 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 40876436 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 351264087 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 7264 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 108789745 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 367388846 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 236095095 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1811043 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5312656 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1169837126 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 12332 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1017086167 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 18990404 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 381124500 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1038523748 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 904776257 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.124130 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.093860 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 347117204 38.36% 38.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 227104713 25.10% 63.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 217802755 24.07% 87.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 96630403 10.68% 98.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 16121175 1.78% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 904776257 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 63882217 18.87% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 158029640 46.67% 65.73% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 116058922 34.27% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 456367665 44.87% 44.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 322074351 31.67% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 215594127 21.20% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1017086167 # Type of FU issued
system.cpu.iq.rate 1.123694 # Inst issue rate
system.cpu.iq.fu_busy_cnt 338625811 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.332937 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3234688378 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1507427240 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 934273902 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 61876428 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 43565689 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1321902233 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 9959480 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 115147908 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 107114599 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2065775 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 19869 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 15518570 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 35329075 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 27772 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1169855013 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 367388846 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 236095095 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6592 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 88 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 30218 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 15437101 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3784620 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 19221721 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 974751329 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 303296690 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 42334838 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 5555 # number of nop insts executed
system.cpu.iew.exec_refs 497768330 # number of memory reference insts executed
system.cpu.iew.exec_branches 150610966 # Number of branches executed
system.cpu.iew.exec_stores 194471640 # Number of stores executed
system.cpu.iew.exec_rate 1.076922 # Inst execution rate
system.cpu.iew.wb_sent 963724922 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 960426352 # cumulative count of insts written-back
system.cpu.iew.wb_producers 536046741 # num instructions producing a value
system.cpu.iew.wb_consumers 893290325 # num instructions consuming a value
system.cpu.iew.wb_rate 1.061096 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.600081 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 357426439 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 15500772 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 853952830 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.923623 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.715196 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 515313788 60.34% 60.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 174402011 20.42% 80.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 72937800 8.54% 89.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 32899590 3.85% 93.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8538808 1.00% 94.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14259214 1.67% 95.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7267758 0.85% 96.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 5975049 0.70% 97.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 22358812 2.62% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 853952830 # Number of insts commited each cycle
system.cpu.commit.committedInsts 640654411 # Number of instructions committed
system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 381221434 # Number of memory references committed
system.cpu.commit.loads 252240938 # Number of loads committed
system.cpu.commit.membars 5740 # Number of memory barriers committed
system.cpu.commit.branches 137364860 # Number of branches committed
system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
system.cpu.commit.function_calls 19275340 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction
system.cpu.commit.bw_lim_events 22358812 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 1977741776 # The number of ROB reads
system.cpu.rob.rob_writes 2343140199 # The number of ROB writes
system.cpu.timesIdled 648615 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 350774 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 640649299 # Number of Instructions Simulated
system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.412828 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.412828 # CPI: Total CPI of All Threads
system.cpu.ipc 0.707800 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.707800 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 995808121 # number of integer regfile reads
system.cpu.int_regfile_writes 567906123 # number of integer regfile writes
system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads
system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes
system.cpu.cc_regfile_reads 3794435958 # number of cc regfile reads
system.cpu.cc_regfile_writes 384896498 # number of cc regfile writes
system.cpu.misc_regfile_reads 715821566 # number of misc regfile reads
system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
system.cpu.dcache.tags.replacements 2756183 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.937153 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 414216547 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2756695 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 150.258388 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.937153 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 839347867 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 839347867 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 286293756 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 286293756 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 127906808 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 127906808 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 414200564 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 414200564 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 414203721 # number of overall hits
system.cpu.dcache.overall_hits::total 414203721 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 3035071 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 3035071 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1044669 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1044669 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 4079740 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4079740 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4080386 # number of overall misses
system.cpu.dcache.overall_misses::total 4080386 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 76845731000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 76845731000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10002174850 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10002174850 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 86847905850 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 86847905850 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 86847905850 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 86847905850 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 289328827 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 289328827 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 418280304 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 418280304 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 418284107 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 418284107 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.008101 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.491873 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.491873 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21287.607997 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21284.237778 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 351058 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 4882 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 71.908644 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2756183 # number of writebacks
system.cpu.dcache.writebacks::total 2756183 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999866 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 999866 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323646 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 323646 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1323512 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1323512 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1323512 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1323512 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035205 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 2035205 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2756228 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2756228 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2756869 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2756869 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65547149000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 65547149000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5956550350 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5956550350 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5499000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5499000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71503699350 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 71503699350 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71509198350 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 71509198350 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8261.248740 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8261.248740 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8578.783151 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8578.783151 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25938.555060 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25938.555060 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 5169029 # number of replacements
system.cpu.icache.tags.tagsinuse 510.720775 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 364910405 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5169539 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 70.588578 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.720775 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997502 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997502 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 745338281 # Number of tag accesses
system.cpu.icache.tags.data_accesses 745338281 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 364910416 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 364910416 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 364910416 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 364910416 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 364910416 # number of overall hits
system.cpu.icache.overall_hits::total 364910416 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5173868 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5173868 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5173868 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5173868 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5173868 # number of overall misses
system.cpu.icache.overall_misses::total 5173868 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 41967552420 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 41967552420 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 41967552420 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 41967552420 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 41967552420 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 41967552420 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 370084284 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 370084284 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 370084284 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 370084284 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 370084284 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 370084284 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013980 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013980 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013980 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013980 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013980 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013980 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.446295 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 8111.446295 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 8111.446295 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 8111.446295 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 79493 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3635 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 21.868776 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 5169029 # number of writebacks
system.cpu.icache.writebacks::total 5169029 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169715 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 5169715 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 5169715 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 5169715 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 5169715 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 5169715 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39342077434 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 39342077434 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39342077434 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 39342077434 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39342077434 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 39342077434 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013969 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013969 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013969 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.105670 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.105670 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 1350427 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 1355108 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 4095 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4790132 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 301513 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16356.090183 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 13598662 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 317875 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 42.779904 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 60356537500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9848.276079 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6507.814104 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.601091 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397205 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 6290 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 10072 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 146 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1301 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4827 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1956 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7712 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.383911 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.614746 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 244370866 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 244370866 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 735261 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 735261 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6545775 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6545775 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 718468 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 718468 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5165879 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 5165879 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286323 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1286323 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5165879 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2004791 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7170670 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 5165879 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2004791 # number of overall hits
system.cpu.l2cache.overall_hits::total 7170670 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 174 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 174 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 2381 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2381 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3663 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3663 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749523 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 749523 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3663 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 751904 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 755567 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3663 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 751904 # number of overall misses
system.cpu.l2cache.overall_misses::total 755567 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195784000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 195784000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 268224500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 268224500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 54132437000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 54132437000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 268224500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 54328221000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 54596445500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 268224500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 54328221000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 54596445500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 735261 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 735261 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 6545775 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 6545775 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 174 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 174 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5169542 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 5169542 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2035846 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 2035846 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 5169542 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2756695 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 7926237 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 5169542 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2756695 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 7926237 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003303 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003303 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.000709 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.000709 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368163 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368163 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000709 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.272756 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.095325 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000709 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.272756 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.095325 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82227.635447 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82227.635447 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73225.361725 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73225.361725 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72222.516187 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72222.516187 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73225.361725 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72254.198674 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72258.906887 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73225.361725 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72254.198674 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72258.906887 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 66304 # number of writebacks
system.cpu.l2cache.writebacks::total 66304 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1019 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 1019 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 873 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 873 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 1892 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1893 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 1892 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1893 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200459 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 200459 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1362 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1362 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3662 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3662 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748650 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748650 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3662 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 750012 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 753674 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3662 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 750012 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200459 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 954133 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16513318471 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16513318471 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2453000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2453000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133666500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133666500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 246204000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 246204000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49598643500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49598643500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246204000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49732310000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 49978514000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246204000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49732310000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16513318471 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 66491832471 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367734 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367734 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.095086 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.120377 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 15851796 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925416 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 760180 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116881 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7205559 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 801565 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 7189951 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 987519 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 243847 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169715 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035846 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508284 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8269921 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 23778205 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661668416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352824192 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1014492608 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1297843 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 9224254 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.222027 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.558758 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 7819520 84.77% 84.77% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 761435 8.25% 93.03% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 643299 6.97% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 9224254 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 15851110000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7754813511 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 4135160937 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.membus.trans_dist::ReadResp 952680 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66304 # Transaction distribution
system.membus.trans_dist::CleanEvict 227429 # Transaction distribution
system.membus.trans_dist::UpgradeReq 174 # Transaction distribution
system.membus.trans_dist::ReadExReq 1362 # Transaction distribution
system.membus.trans_dist::ReadExResp 1362 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 952681 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2201992 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2201992 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65302144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 65302144 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1247950 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1247950 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1247950 # Request fanout histogram
system.membus.reqLayer0.occupancy 1752348040 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 5020538027 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
|