1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.060131 # Number of seconds simulated
sim_ticks 60130734500 # Number of ticks simulated
final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 310652 # Simulator instruction rate (inst/s)
host_op_rate 397278 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 263409545 # Simulator tick rate (ticks/s)
host_mem_usage 281384 # Number of bytes of host memory used
host_seconds 228.28 # Real time elapsed on the host
sim_insts 70915150 # Number of instructions simulated
sim_ops 90690106 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory
system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory
system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory
system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory
system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 128515 # Number of read requests accepted
system.physmem.writeReqs 86552 # Number of write requests accepted
system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 8086 # Per bank write bursts
system.physmem.perBankRdBursts::1 8335 # Per bank write bursts
system.physmem.perBankRdBursts::2 8257 # Per bank write bursts
system.physmem.perBankRdBursts::3 8155 # Per bank write bursts
system.physmem.perBankRdBursts::4 8301 # Per bank write bursts
system.physmem.perBankRdBursts::5 8413 # Per bank write bursts
system.physmem.perBankRdBursts::6 8070 # Per bank write bursts
system.physmem.perBankRdBursts::7 7917 # Per bank write bursts
system.physmem.perBankRdBursts::8 8054 # Per bank write bursts
system.physmem.perBankRdBursts::9 7613 # Per bank write bursts
system.physmem.perBankRdBursts::10 7771 # Per bank write bursts
system.physmem.perBankRdBursts::11 7825 # Per bank write bursts
system.physmem.perBankRdBursts::12 7888 # Per bank write bursts
system.physmem.perBankRdBursts::13 7870 # Per bank write bursts
system.physmem.perBankRdBursts::14 7981 # Per bank write bursts
system.physmem.perBankRdBursts::15 7974 # Per bank write bursts
system.physmem.perBankWrBursts::0 5400 # Per bank write bursts
system.physmem.perBankWrBursts::1 5549 # Per bank write bursts
system.physmem.perBankWrBursts::2 5475 # Per bank write bursts
system.physmem.perBankWrBursts::3 5349 # Per bank write bursts
system.physmem.perBankWrBursts::4 5387 # Per bank write bursts
system.physmem.perBankWrBursts::5 5586 # Per bank write bursts
system.physmem.perBankWrBursts::6 5325 # Per bank write bursts
system.physmem.perBankWrBursts::7 5260 # Per bank write bursts
system.physmem.perBankWrBursts::8 5187 # Per bank write bursts
system.physmem.perBankWrBursts::9 5135 # Per bank write bursts
system.physmem.perBankWrBursts::10 5306 # Per bank write bursts
system.physmem.perBankWrBursts::11 5279 # Per bank write bursts
system.physmem.perBankWrBursts::12 5541 # Per bank write bursts
system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
system.physmem.perBankWrBursts::14 5706 # Per bank write bursts
system.physmem.perBankWrBursts::15 5441 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 60130703000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 128515 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 86552 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads
system.physmem.totQLat 3048956750 # Total ticks spent queuing
system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers
system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.79 # Data bus utilization in percentage
system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing
system.physmem.readRowHits 112228 # Number of row buffer hits during reads
system.physmem.writeRowHits 69923 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes
system.physmem.avgGap 279590.56 # Average gap between requests
system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ)
system.physmem_0.averagePower 386.883743 # Core power per rank (mW)
system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states
system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ)
system.physmem_1.averagePower 383.200220 # Core power per rank (mW)
system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states
system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 14827796 # Number of BP lookups
system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 120261469 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915150 # Number of instructions committed
system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.695850 # CPI: cycles per instruction
system.cpu.ipc 0.589675 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction
system.cpu.op_class_0::MemWrite 20555707 22.67% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 90690106 # Class of committed instruction
system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked
system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 156451 # number of replacements
system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits
system.cpu.dcache.overall_hits::total 42605457 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses
system.cpu.dcache.overall_misses::total 299788 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks
system.cpu.dcache.writebacks::total 128145 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 43545 # number of replacements
system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses
system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits
system.cpu.icache.overall_hits::total 25048343 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses
system.cpu.icache.overall_misses::total 45588 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 43545 # number of writebacks
system.cpu.icache.writebacks::total 43545 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 97176 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41101 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 41101 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 41101 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 77547 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 41101 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits
system.cpu.l2cache.overall_hits::total 77547 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4487 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 4487 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 4487 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 128588 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses
system.cpu.l2cache.overall_misses::total 128588 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks
system.cpu.l2cache.writebacks::total 86552 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 97176 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 26198 # Transaction distribution
system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution
system.membus.trans_dist::CleanEvict 7237 # Transaction distribution
system.membus.trans_dist::ReadExReq 102317 # Transaction distribution
system.membus.trans_dist::ReadExResp 102317 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 128515 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 128515 # Request fanout histogram
system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
|