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|
---------- Begin Simulation Statistics ----------
sim_seconds 1.128034 # Number of seconds simulated
sim_ticks 1128033563500 # Number of ticks simulated
final_tick 1128033563500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 296898 # Simulator instruction rate (inst/s)
host_op_rate 319862 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 216832014 # Simulator tick rate (ticks/s)
host_mem_usage 266856 # Number of bytes of host memory used
host_seconds 5202.34 # Real time elapsed on the host
sim_insts 1544563088 # Number of instructions simulated
sim_ops 1664032481 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 130888128 # Number of bytes read from this memory
system.physmem.bytes_read::total 130938240 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67194432 # Number of bytes written to this memory
system.physmem.bytes_written::total 67194432 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2045127 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2045910 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1049913 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1049913 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 44424 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 116032122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 116076546 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 44424 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 44424 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 59567759 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 59567759 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 59567759 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 44424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 116032122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 175644306 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2045910 # Number of read requests accepted
system.physmem.writeReqs 1049913 # Number of write requests accepted
system.physmem.readBursts 2045910 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1049913 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 130851840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 86400 # Total number of bytes read from write queue
system.physmem.bytesWritten 67192960 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 130938240 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 67194432 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1350 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 127234 # Per bank write bursts
system.physmem.perBankRdBursts::1 124635 # Per bank write bursts
system.physmem.perBankRdBursts::2 121565 # Per bank write bursts
system.physmem.perBankRdBursts::3 123578 # Per bank write bursts
system.physmem.perBankRdBursts::4 122544 # Per bank write bursts
system.physmem.perBankRdBursts::5 122632 # Per bank write bursts
system.physmem.perBankRdBursts::6 123221 # Per bank write bursts
system.physmem.perBankRdBursts::7 123735 # Per bank write bursts
system.physmem.perBankRdBursts::8 131340 # Per bank write bursts
system.physmem.perBankRdBursts::9 133478 # Per bank write bursts
system.physmem.perBankRdBursts::10 132036 # Per bank write bursts
system.physmem.perBankRdBursts::11 133242 # Per bank write bursts
system.physmem.perBankRdBursts::12 133211 # Per bank write bursts
system.physmem.perBankRdBursts::13 133326 # Per bank write bursts
system.physmem.perBankRdBursts::14 129274 # Per bank write bursts
system.physmem.perBankRdBursts::15 129509 # Per bank write bursts
system.physmem.perBankWrBursts::0 66120 # Per bank write bursts
system.physmem.perBankWrBursts::1 64398 # Per bank write bursts
system.physmem.perBankWrBursts::2 62563 # Per bank write bursts
system.physmem.perBankWrBursts::3 62980 # Per bank write bursts
system.physmem.perBankWrBursts::4 62981 # Per bank write bursts
system.physmem.perBankWrBursts::5 63086 # Per bank write bursts
system.physmem.perBankWrBursts::6 64437 # Per bank write bursts
system.physmem.perBankWrBursts::7 65431 # Per bank write bursts
system.physmem.perBankWrBursts::8 67296 # Per bank write bursts
system.physmem.perBankWrBursts::9 67792 # Per bank write bursts
system.physmem.perBankWrBursts::10 67535 # Per bank write bursts
system.physmem.perBankWrBursts::11 67858 # Per bank write bursts
system.physmem.perBankWrBursts::12 67312 # Per bank write bursts
system.physmem.perBankWrBursts::13 67784 # Per bank write bursts
system.physmem.perBankWrBursts::14 66474 # Per bank write bursts
system.physmem.perBankWrBursts::15 65843 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1128033469500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 2045910 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1049913 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1917702 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 126844 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 32849 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 34013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 57015 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 61217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 61623 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 61654 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 61600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 61647 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 61568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 61682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 61684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 62149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 62542 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 61998 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 62533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 61281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 61114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1910047 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 103.685692 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.827100 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 125.490486 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1485463 77.77% 77.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 305174 15.98% 93.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 52509 2.75% 96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20929 1.10% 97.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 13256 0.69% 98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7619 0.40% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5519 0.29% 98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5102 0.27% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 14476 0.76% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1910047 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61113 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 33.412400 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 159.518866 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 61065 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 24 0.04% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 61113 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61113 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.179487 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.144319 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.100540 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 26981 44.15% 44.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1028 1.68% 45.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 28814 47.15% 92.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3825 6.26% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 400 0.65% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 47 0.08% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61113 # Writes before turning the bus around for reads
system.physmem.totQLat 38097515250 # Total ticks spent queuing
system.physmem.totMemAccLat 76433015250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 10222800000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18633.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 37383.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 59.57 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 116.08 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 59.57 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.37 # Data bus utilization in percentage
system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
system.physmem.readRowHits 772369 # Number of row buffer hits during reads
system.physmem.writeRowHits 412032 # Number of row buffer hits during writes
system.physmem.readRowHitRate 37.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 39.24 # Row buffer hit rate for writes
system.physmem.avgGap 364372.73 # Average gap between requests
system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 7040703600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3841653750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 7715315400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3317734080 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 423036881190 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 305734953750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 824364871770 # Total energy per rank (pJ)
system.physmem_0.averagePower 730.798394 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 505893058250 # Time in different power states
system.physmem_0.memoryStateTime::REF 37667500000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 584472684250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 7399251720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 4037290125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 8232221400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3485553120 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 432494110575 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 297439138500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 826765195440 # Total energy per rank (pJ)
system.physmem_1.averagePower 732.926278 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 492041493250 # Time in different power states
system.physmem_1.memoryStateTime::REF 37667500000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 598324400250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 240019627 # Number of BP lookups
system.cpu.branchPred.condPredicted 186610234 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 131647639 # Number of BTB lookups
system.cpu.branchPred.BTBHits 122324320 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 92.917975 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15657430 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 534 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 232 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 302 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2256067127 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563088 # Number of instructions committed
system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
system.cpu.discardedOps 41363716 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.460651 # CPI: cycles per instruction
system.cpu.ipc 0.684626 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction
system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 1664032481 # Class of committed instruction
system.cpu.tickCycles 1844612574 # Number of cycles that the object actually ticked
system.cpu.idleCycles 411454553 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9220101 # number of replacements
system.cpu.dcache.tags.tagsinuse 4085.702912 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 624495427 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9224197 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.701874 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 9818932500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.702912 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997486 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997486 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1240 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1277391791 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1277391791 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 454164210 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 454164210 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170331094 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170331094 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 624495304 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 624495304 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 624495305 # number of overall hits
system.cpu.dcache.overall_hits::total 624495305 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7333415 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7333415 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 2254953 # number of WriteReq misses
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system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 9588368 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9588368 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 9588370 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 190988166000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 190988166000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 108977258000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 108977258000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 299965424000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 299965424000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 299965424000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 299965424000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 461497625 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 461497625 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 634083672 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 634083672 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 634083675 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26043.550788 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26043.550788 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48327.950960 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48327.950960 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 31284.304482 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.297957 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31284.297957 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3684499 # number of writebacks
system.cpu.dcache.writebacks::total 3684499 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364123 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 364123 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 364172 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 364172 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 364172 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 7333366 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses
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system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9224196 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9224196 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 9224197 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183652478000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 183652478000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84692070000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84692070000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268344548000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 268344548000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268344622000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 268344622000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25043.408170 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.408170 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44790.948948 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44790.948948 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.375335 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.375335 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.380204 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.380204 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 30 # number of replacements
system.cpu.icache.tags.tagsinuse 660.287317 # Cycle average of tags in use
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system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 569297.205128 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 660.287317 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::total 0.322406 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 752 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 932511279 # Number of tag accesses
system.cpu.icache.tags.data_accesses 932511279 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 466254411 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 466254411 # number of ReadReq hits
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system.cpu.icache.demand_hits::total 466254411 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 466254411 # number of overall hits
system.cpu.icache.overall_hits::total 466254411 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 819 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61690000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 61690000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 61690000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 61690000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 61690000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 466255230 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 466255230 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 466255230 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 466255230 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75323.565324 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75323.565324 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75323.565324 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75323.565324 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 30 # number of writebacks
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system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses
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system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 60871000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60871000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 60871000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60871000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 60871000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74323.565324 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74323.565324 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 2013239 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31266.385554 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14508014 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2043015 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.101276 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 59831992000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14855.828649 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.313947 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 16384.242958 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.453364 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000803 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.954174 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12853 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 151482269 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 151482269 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3684499 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3684499 # number of WritebackDirty hits
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system.cpu.l2cache.WritebackClean_hits::total 30 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1089818 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1089818 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089246 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6089246 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7179064 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7179100 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7179064 # number of overall hits
system.cpu.l2cache.overall_hits::total 7179100 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 801012 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 801012 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 783 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244121 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1244121 # number of ReadSharedReq misses
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system.cpu.l2cache.demand_misses::cpu.data 2045133 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2045133 # number of overall misses
system.cpu.l2cache.overall_misses::total 2045916 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70389294000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 70389294000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59232000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 59232000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108712178500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 108712178500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 59232000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 179101472500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 179160704500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 59232000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 179101472500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 179160704500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684499 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3684499 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 30 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 30 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890830 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1890830 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 819 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 819 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333367 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7333367 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9224197 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9225016 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9224197 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9225016 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423630 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.423630 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169652 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169652 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.221714 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.221779 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.221714 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.221779 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87875.455049 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87875.455049 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75647.509579 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75647.509579 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87380.711764 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87380.711764 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75647.509579 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87574.486598 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87569.921981 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75647.509579 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87574.486598 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87569.921981 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1049913 # number of writebacks
system.cpu.l2cache.writebacks::total 1049913 # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801012 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 801012 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244115 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244115 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2045127 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2045910 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2045127 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2045910 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62379174000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62379174000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51402000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51402000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96270618000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96270618000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51402000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158649792000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 158701194000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51402000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158649792000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 158701194000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423630 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423630 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169651 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169651 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.221778 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.221778 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77875.455049 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77875.455049 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65647.509579 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65647.509579 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77380.803222 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77380.803222 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18445147 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220143 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1285 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7334186 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4734412 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 30 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6498928 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333367 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1668 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668495 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27670163 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826156544 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 826210880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 2013239 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 67194432 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 11238255 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.016087 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11235364 99.97% 99.97% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2885 0.03% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11238255 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12907102500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13836298494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
system.membus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1244898 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1049913 # Transaction distribution
system.membus.trans_dist::CleanEvict 962255 # Transaction distribution
system.membus.trans_dist::ReadExReq 801012 # Transaction distribution
system.membus.trans_dist::ReadExResp 801012 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1244898 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6103988 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6103988 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198132672 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 198132672 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 4058078 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4058078 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 4058078 # Request fanout histogram
system.membus.reqLayer0.occupancy 8755432500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 11187827500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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