blob: 2c8dfca63523bf2541bb1f6da7e0c80a23ff7321 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.053438 # Number of seconds simulated
sim_ticks 53437621500 # Number of ticks simulated
final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 247892 # Simulator instruction rate (inst/s)
host_op_rate 247892 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 144138078 # Simulator tick rate (ticks/s)
host_mem_usage 256712 # Number of bytes of host memory used
host_seconds 370.74 # Real time elapsed on the host
sim_insts 91903089 # Number of instructions simulated
sim_ops 91903089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory
system.physmem.bytes_read::total 340608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 202880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 202880 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5322 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 340608 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 340608 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 468 # Per bank write bursts
system.physmem.perBankRdBursts::1 295 # Per bank write bursts
system.physmem.perBankRdBursts::2 308 # Per bank write bursts
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
system.physmem.perBankRdBursts::4 224 # Per bank write bursts
system.physmem.perBankRdBursts::5 238 # Per bank write bursts
system.physmem.perBankRdBursts::6 222 # Per bank write bursts
system.physmem.perBankRdBursts::7 289 # Per bank write bursts
system.physmem.perBankRdBursts::8 254 # Per bank write bursts
system.physmem.perBankRdBursts::9 282 # Per bank write bursts
system.physmem.perBankRdBursts::10 254 # Per bank write bursts
system.physmem.perBankRdBursts::11 261 # Per bank write bursts
system.physmem.perBankRdBursts::12 410 # Per bank write bursts
system.physmem.perBankRdBursts::13 344 # Per bank write bursts
system.physmem.perBankRdBursts::14 501 # Per bank write bursts
system.physmem.perBankRdBursts::15 448 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 53437285500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 5322 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation
system.physmem.totQLat 132267250 # Total ticks spent queuing
system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers
system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4338 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 10040827.79 # Average gap between requests
system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ)
system.physmem_0.averagePower 250.626273 # Core power per rank (mW)
system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states
system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states
system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states
system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ)
system.physmem_1.averagePower 251.716611 # Core power per rank (mW)
system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states
system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states
system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 11450652 # Number of BP lookups
system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 2073 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20415218 # DTB read hits
system.cpu.dtb.read_misses 43383 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20458601 # DTB read accesses
system.cpu.dtb.write_hits 6579912 # DTB write hits
system.cpu.dtb.write_misses 276 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6580188 # DTB write accesses
system.cpu.dtb.data_hits 26995130 # DTB hits
system.cpu.dtb.data_misses 43659 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 27038789 # DTB accesses
system.cpu.itb.fetch_hits 22968644 # ITB hits
system.cpu.itb.fetch_misses 90 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 22968734 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 106875243 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903089 # Number of instructions committed
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.162912 # CPI: cycles per instruction
system.cpu.ipc 0.859910 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction
system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91903089 # Class of committed instruction
system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits
system.cpu.dcache.overall_hits::total 26572187 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses
system.cpu.dcache.overall_misses::total 3415 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1743 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2231 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 13865 # number of replacements
system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses
system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits
system.cpu.icache.overall_hits::total 22952813 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses
system.cpu.icache.overall_misses::total 15831 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 456439000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 456439000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 456439000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 456439000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 456439000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 456439000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22968644 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22968644 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22968644 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22968644 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22968644 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22968644 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 13865 # number of writebacks
system.cpu.icache.writebacks::total 13865 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15831 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15831 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15831 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13865 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12660 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 12660 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12660 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 12739 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12660 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 12739 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1717 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1717 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3170 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3170 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 435 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 435 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2152 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5322 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses
system.cpu.l2cache.overall_misses::total 5322 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 13865 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1743 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1743 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15830 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15830 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 488 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 488 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15830 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2231 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 18061 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15830 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2231 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 18061 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985083 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985083 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200253 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200253 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.891393 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.891393 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200253 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964590 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.294668 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1717 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1717 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3170 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3170 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 435 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 435 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2152 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5322 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200253 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.891393 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.891393 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1743 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1743 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15830 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 488 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45525 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4619 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 50144 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1900480 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2050112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 18061 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 18061 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 18061 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 30013500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23745000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3605 # Transaction distribution
system.membus.trans_dist::ReadExReq 1717 # Transaction distribution
system.membus.trans_dist::ReadExResp 1717 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3605 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10644 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10644 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 340608 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 5322 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 5322 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5322 # Request fanout histogram
system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
|