blob: a216e15cb4c2ab73778bb87008720e053f27b318 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000026 # Number of seconds simulated
sim_ticks 25552000 # Number of ticks simulated
final_tick 25552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 78387 # Simulator instruction rate (inst/s)
host_op_rate 78372 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 313333088 # Simulator tick rate (ticks/s)
host_mem_usage 263656 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 751408892 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 420788979 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1172197871 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 751408892 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 751408892 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 751408892 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 420788979 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1172197871 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 65 # Per bank write bursts
system.physmem.perBankRdBursts::1 29 # Per bank write bursts
system.physmem.perBankRdBursts::2 27 # Per bank write bursts
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
system.physmem.perBankRdBursts::4 41 # Per bank write bursts
system.physmem.perBankRdBursts::5 19 # Per bank write bursts
system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdBursts::7 3 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdBursts::10 19 # Per bank write bursts
system.physmem.perBankRdBursts::11 25 # Per bank write bursts
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
system.physmem.perBankRdBursts::13 119 # Per bank write bursts
system.physmem.perBankRdBursts::14 46 # Per bank write bursts
system.physmem.perBankRdBursts::15 12 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 25537500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 469 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 313 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 86 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 330.418605 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 204.922237 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 319.300576 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 27 31.40% 31.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 21 24.42% 55.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 10 11.63% 67.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 8 9.30% 76.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1 1.16% 77.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 3.49% 81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7 8.14% 89.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 2.33% 91.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7 8.14% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 86 # Bytes accessed per row activation
system.physmem.totQLat 3845750 # Total ticks spent queuing
system.physmem.totMemAccLat 12639500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8199.89 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26949.89 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1174.70 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1174.70 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 9.18 # Data bus utilization in percentage
system.physmem.busUtilRead 9.18 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 378 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 54450.96 # Average gap between requests
system.physmem.pageHitRate 80.60 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 13500 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22839000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 1172197871 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 396 # Transaction distribution
system.membus.trans_dist::ReadResp 395 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 29952 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4371000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 1632 # Number of BP lookups
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1266 # Number of BTB lookups
system.cpu.branchPred.BTBHits 352 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 27.804107 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 890 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 893 # DTB write accesses
system.cpu.dtb.data_hits 2073 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2083 # DTB accesses
system.cpu.itb.fetch_hits 915 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 932 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 51105 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5177 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9744 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 2973 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2152 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 645 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 406 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.370124 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4448 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11594 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 43730 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7375 # Number of cycles cpu stages are processed.
system.cpu.activity 14.431073 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed
system.cpu.comNops 17 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 3254 # Number of Integer instructions committed
system.cpu.comFloats 2 # Number of Floating Point instructions committed
system.cpu.committedInsts 6390 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
system.cpu.cpi 7.997653 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 7.997653 # CPI: Total CPI of All Threads
system.cpu.ipc 0.125037 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.125037 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 46181 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 9.635065 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 47212 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.617650 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 46944 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.142060 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 49775 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1330 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.602485 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 46641 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4464 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.734957 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 142.073249 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 142.073249 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.069372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.069372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.146973 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2131 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2131 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 560 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 560 # number of overall hits
system.cpu.icache.overall_hits::total 560 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 355 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 355 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 355 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
system.cpu.icache.overall_misses::total 355 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24875750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24875750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24875750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24875750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24875750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24875750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.387978 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.387978 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70072.535211 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70072.535211 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70072.535211 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70072.535211 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 53 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 53 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 53 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21058500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 21058500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21058500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 21058500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21058500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21058500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69730.132450 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69730.132450 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 1174702567 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 508000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 198.803908 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.109548 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.694360 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001730 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006067 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012054 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4228 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4228 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20740000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7180750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 27920750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5181250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5181250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 20740000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12362000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 33102000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 20740000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12362000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 33102000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68903.654485 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75586.842105 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70506.944444 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70976.027397 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70976.027397 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70579.957356 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70579.957356 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16969500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5998750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22968250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4278250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4278250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16969500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10277000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 27246500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16969500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10277000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 27246500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56377.076412 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63144.736842 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58000.631313 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58606.164384 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58606.164384 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.396801 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 103.396801 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025243 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025243 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits
system.cpu.dcache.overall_hits::total 1601 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
system.cpu.dcache.overall_misses::total 447 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7625750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7625750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22645250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 22645250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 30271000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 30271000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 30271000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 30271000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78615.979381 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 78615.979381 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64700.714286 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64700.714286 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67720.357942 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67720.357942 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.307692 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7282250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7282250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5258750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5258750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12541000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12541000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12541000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12541000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76655.263158 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76655.263158 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72037.671233 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72037.671233 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|