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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated
sim_ticks 24794500 # Number of ticks simulated
final_tick 24794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50796 # Simulator instruction rate (inst/s)
host_op_rate 50792 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 98611945 # Simulator tick rate (ticks/s)
host_mem_usage 229596 # Number of bytes of host memory used
host_seconds 0.25 # Real time elapsed on the host
sim_insts 12770 # Number of instructions simulated
sim_ops 12770 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 40320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory
system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 40320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 40320 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 630 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory
system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1626167094 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 890520075 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2516687169 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1626167094 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1626167094 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1626167094 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 890520075 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2516687169 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 975 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 85 # Per bank write bursts
system.physmem.perBankRdBursts::1 151 # Per bank write bursts
system.physmem.perBankRdBursts::2 78 # Per bank write bursts
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
system.physmem.perBankRdBursts::4 86 # Per bank write bursts
system.physmem.perBankRdBursts::5 49 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 50 # Per bank write bursts
system.physmem.perBankRdBursts::8 43 # Per bank write bursts
system.physmem.perBankRdBursts::9 39 # Per bank write bursts
system.physmem.perBankRdBursts::10 29 # Per bank write bursts
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
system.physmem.perBankRdBursts::14 68 # Per bank write bursts
system.physmem.perBankRdBursts::15 37 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 24650000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 975 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 354 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 215 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 283.088372 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.093050 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 284.959526 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 71 33.02% 33.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 62 28.84% 61.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 23 10.70% 72.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 14 6.51% 79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 10 4.65% 83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 14 6.51% 90.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5 2.33% 92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 1.40% 93.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 13 6.05% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 215 # Bytes accessed per row activation
system.physmem.totQLat 13049000 # Total ticks spent queuing
system.physmem.totMemAccLat 31330250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13383.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 32133.59 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2516.69 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2516.69 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 19.66 # Data bus utilization in percentage
system.physmem.busUtilRead 19.66 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 751 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 25282.05 # Average gap between requests
system.physmem.pageHitRate 77.03 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4531800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 16120170 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 23622915 # Total energy per rank (pJ)
system.physmem_0.averagePower 998.485338 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 22869500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2854800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 15614010 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 495000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 21576195 # Total energy per rank (pJ)
system.physmem_1.averagePower 912.216256 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 727500 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22158250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 6577 # Number of BP lookups
system.cpu.branchPred.condPredicted 3752 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1243 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 4859 # Number of BTB lookups
system.cpu.branchPred.BTBHits 1038 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 21.362420 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1078 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 4547 # DTB read hits
system.cpu.dtb.read_misses 85 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 4632 # DTB read accesses
system.cpu.dtb.write_hits 2078 # DTB write hits
system.cpu.dtb.write_misses 69 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 2147 # DTB write accesses
system.cpu.dtb.data_hits 6625 # DTB hits
system.cpu.dtb.data_misses 154 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 6779 # DTB accesses
system.cpu.itb.fetch_hits 5175 # ITB hits
system.cpu.itb.fetch_misses 51 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 5226 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
system.cpu.numCycles 49590 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 1137 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 37512 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6577 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2116 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 11769 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1328 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 5175 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 779 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 28288 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.326075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.708941 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21788 77.02% 77.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 562 1.99% 79.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 445 1.57% 80.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 567 2.00% 82.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 586 2.07% 84.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 389 1.38% 86.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 492 1.74% 87.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 554 1.96% 89.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2905 10.27% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 28288 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.132628 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.756443 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 38487 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 11291 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 4912 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 546 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1060 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 470 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 278 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 30785 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 643 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1060 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 39027 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 4538 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1512 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 4932 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5227 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 29058 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 481 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 927 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 3808 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 21804 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 36221 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 36203 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 12650 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 60 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2095 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2679 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1390 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.memDep1.insertedLoads 2734 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep1.insertedStores 1411 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 25901 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21580 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 13182 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 7478 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 28288 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.762868 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.484406 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 20144 71.21% 71.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2630 9.30% 80.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1862 6.58% 87.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1311 4.63% 91.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1169 4.13% 95.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 655 2.32% 98.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 329 1.16% 99.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 136 0.48% 99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 52 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 28288 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 37 11.97% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 189 61.17% 73.14% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 83 26.86% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 7104 66.24% 66.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.29% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2483 23.15% 89.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1132 10.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10724 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_1::IntAlu 7199 66.31% 66.33% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.34% # Type of FU issued
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.34% # Type of FU issued
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued
system.cpu.iq.FU_type_1::MemRead 2532 23.32% 89.68% # Type of FU issued
system.cpu.iq.FU_type_1::MemWrite 1120 10.32% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::total 10856 # Type of FU issued
system.cpu.iq.FU_type::total 21580 0.00% 0.00% # Type of FU issued
system.cpu.iq.rate 0.435168 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 153 # FU busy when requested
system.cpu.iq.fu_busy_cnt::1 156 # FU busy when requested
system.cpu.iq.fu_busy_cnt::total 309 # FU busy when requested
system.cpu.iq.fu_busy_rate::0 0.007090 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1 0.007229 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.014319 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 71845 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 39156 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19068 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 21863 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1494 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 525 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 275 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread1.squashedLoads 1549 # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation 25 # Number of memory ordering violations
system.cpu.iew.lsq.thread1.squashedStores 546 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread1.cacheBlocked 273 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1060 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2492 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 405 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 26102 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 214 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 5413 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2801 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 43 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 158 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1006 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1164 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20390 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 2303 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::1 2335 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::total 4638 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
system.cpu.iew.exec_nop::0 75 # number of nop insts executed
system.cpu.iew.exec_nop::1 74 # number of nop insts executed
system.cpu.iew.exec_nop::total 149 # number of nop insts executed
system.cpu.iew.exec_refs::0 3395 # number of memory reference insts executed
system.cpu.iew.exec_refs::1 3403 # number of memory reference insts executed
system.cpu.iew.exec_refs::total 6798 # number of memory reference insts executed
system.cpu.iew.exec_branches::0 1585 # Number of branches executed
system.cpu.iew.exec_branches::1 1614 # Number of branches executed
system.cpu.iew.exec_branches::total 3199 # Number of branches executed
system.cpu.iew.exec_stores::0 1092 # Number of stores executed
system.cpu.iew.exec_stores::1 1068 # Number of stores executed
system.cpu.iew.exec_stores::total 2160 # Number of stores executed
system.cpu.iew.exec_rate 0.411172 # Inst execution rate
system.cpu.iew.wb_sent::0 9687 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::1 9764 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::total 19451 # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0 9532 # cumulative count of insts written-back
system.cpu.iew.wb_count::1 9556 # cumulative count of insts written-back
system.cpu.iew.wb_count::total 19088 # cumulative count of insts written-back
system.cpu.iew.wb_producers::0 5025 # num instructions producing a value
system.cpu.iew.wb_producers::1 5077 # num instructions producing a value
system.cpu.iew.wb_producers::total 10102 # num instructions producing a value
system.cpu.iew.wb_consumers::0 6671 # num instructions consuming a value
system.cpu.iew.wb_consumers::1 6701 # num instructions consuming a value
system.cpu.iew.wb_consumers::total 13372 # num instructions consuming a value
system.cpu.iew.wb_rate::0 0.192216 # insts written-back per cycle
system.cpu.iew.wb_rate::1 0.192700 # insts written-back per cycle
system.cpu.iew.wb_rate::total 0.384916 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.753260 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.757648 # average fanout of values written-back
system.cpu.iew.wb_fanout::total 0.755459 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 13275 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 976 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 28256 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.453143 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.335890 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 23155 81.95% 81.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 2552 9.03% 90.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1012 3.58% 94.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 380 1.34% 95.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 269 0.95% 96.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 177 0.63% 97.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 194 0.69% 98.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 173 0.61% 98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 344 1.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 28256 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
system.cpu.commit.refs::0 2050 # Number of memory references committed
system.cpu.commit.refs::1 2050 # Number of memory references committed
system.cpu.commit.refs::total 4100 # Number of memory references committed
system.cpu.commit.loads::0 1185 # Number of loads committed
system.cpu.commit.loads::1 1185 # Number of loads committed
system.cpu.commit.loads::total 2370 # Number of loads committed
system.cpu.commit.membars::0 0 # Number of memory barriers committed
system.cpu.commit.membars::1 0 # Number of memory barriers committed
system.cpu.commit.membars::total 0 # Number of memory barriers committed
system.cpu.commit.branches::0 1056 # Number of branches committed
system.cpu.commit.branches::1 1056 # Number of branches committed
system.cpu.commit.branches::total 2112 # Number of branches committed
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions.
system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions.
system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions.
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction
system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction
system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction
system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction
system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
system.cpu.commit.bw_lim_events 344 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 128366 # The number of ROB reads
system.cpu.rob.rob_writes 54620 # The number of ROB writes
system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21302 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated
system.cpu.cpi::0 7.766641 # CPI: Cycles Per Instruction
system.cpu.cpi::1 7.766641 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.883320 # CPI: Total CPI of All Threads
system.cpu.ipc::0 0.128756 # IPC: Instructions Per Cycle
system.cpu.ipc::1 0.128756 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.257512 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 25695 # number of integer regfile reads
system.cpu.int_regfile_writes 14528 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 213.419877 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4643 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 345 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.457971 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 213.419877 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.052104 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.052104 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.084229 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 11689 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 11689 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3618 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3618 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1025 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1025 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 4643 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4643 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4643 # number of overall hits
system.cpu.dcache.overall_hits::total 4643 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 705 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 705 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1029 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1029 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1029 # number of overall misses
system.cpu.dcache.overall_misses::total 1029 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25567500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25567500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 52147927 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 52147927 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 77715427 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 77715427 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 77715427 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 77715427 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 5672 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5672 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5672 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5672 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082192 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.082192 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.407514 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.407514 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.181417 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.181417 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.181417 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.181417 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78912.037037 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 78912.037037 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73968.690780 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73968.690780 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75525.196307 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75525.196307 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75525.196307 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75525.196307 # average overall miss latency
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system.cpu.dcache.blocked::no_mshrs 120 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.216667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 123 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 561 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 561 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 17683500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 12260990 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29944490 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29944490 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29944490 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29944490 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050989 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.060825 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.060825 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87977.611940 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85145.763889 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85145.763889 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86795.623188 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 86795.623188 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86795.623188 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 86795.623188 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.tags.replacements::1 0 # number of replacements
system.cpu.icache.tags.replacements::total 8 # number of replacements
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system.cpu.icache.tags.total_refs 4245 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 632 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.716772 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_percent::total 0.154899 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 624 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.304688 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 10968 # Number of tag accesses
system.cpu.icache.tags.data_accesses 10968 # Number of data accesses
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system.cpu.icache.overall_hits::total 4245 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 923 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 923 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 923 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 69430495 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 69430495 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 69430495 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 69430495 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5168 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5168 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5168 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5168 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5168 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5168 # number of overall (read+write) accesses
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system.cpu.icache.overall_miss_rate::total 0.178599 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::total 75222.638137 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75222.638137 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75222.638137 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75222.638137 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75222.638137 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 3541 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 68 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 291 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 291 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 291 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 291 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 291 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 632 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 632 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 632 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 632 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 632 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 632 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 51837997 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51837997 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 51837997 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51837997 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 51837997 # number of overall MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.122291 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.122291 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.122291 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.122291 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82022.147152 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82022.147152 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82022.147152 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 82022.147152 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82022.147152 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 82022.147152 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 439.367315 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 831 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.012034 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.958632 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 121.408683 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009703 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003705 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.013408 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 831 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 509 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025360 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 8855 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 8855 # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks 8 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 8 # number of WritebackClean hits
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system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadExReq_misses::total 144 # number of ReadExReq misses
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system.cpu.l2cache.ReadCleanReq_misses::total 630 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 201 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 201 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 630 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 345 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 630 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 345 # number of overall misses
system.cpu.l2cache.overall_misses::total 975 # number of overall misses
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system.cpu.l2cache.ReadCleanReq_miss_latency::total 50862500 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 29412000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 80274500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 8 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 8 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 144 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 632 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 345 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 345 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80734.126984 # average ReadCleanReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85252.173913 # average overall miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 144 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadCleanReq_mshr_misses::total 630 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 201 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 201 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 630 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44562500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25962000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 70524500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996835 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73597.222222 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73597.222222 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70734.126984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70734.126984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76437.810945 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76437.810945 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 985 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 833 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 632 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 201 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40960 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 63040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002047 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.045222 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 975 99.80% 99.80% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 500500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 948000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 517500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 831 # Transaction distribution
system.membus.trans_dist::ReadExReq 144 # Transaction distribution
system.membus.trans_dist::ReadExResp 144 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 831 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 975 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 975 # Request fanout histogram
system.membus.reqLayer0.occupancy 1186000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 4.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 5196500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 21.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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