blob: 4c33c60ec862bb92153a995b02e0af5508f4274c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000165 # Number of seconds simulated
sim_ticks 165091500 # Number of ticks simulated
final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 261359 # Simulator instruction rate (inst/s)
host_op_rate 261351 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 380682439 # Simulator tick rate (ticks/s)
host_mem_usage 261856 # Number of bytes of host memory used
host_seconds 0.43 # Real time elapsed on the host
sim_insts 113337 # Number of instructions simulated
sim_ops 113337 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 49984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory
system.physmem.bytes_read::total 66752 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49984 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49984 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 781 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 262 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1043 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 302765436 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 101567918 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 404333355 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 302765436 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302765436 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 302765436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 101567918 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 404333355 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1043 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 1043 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 66752 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 66752 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 93 # Per bank write bursts
system.physmem.perBankRdBursts::1 5 # Per bank write bursts
system.physmem.perBankRdBursts::2 17 # Per bank write bursts
system.physmem.perBankRdBursts::3 108 # Per bank write bursts
system.physmem.perBankRdBursts::4 59 # Per bank write bursts
system.physmem.perBankRdBursts::5 95 # Per bank write bursts
system.physmem.perBankRdBursts::6 66 # Per bank write bursts
system.physmem.perBankRdBursts::7 26 # Per bank write bursts
system.physmem.perBankRdBursts::8 58 # Per bank write bursts
system.physmem.perBankRdBursts::9 78 # Per bank write bursts
system.physmem.perBankRdBursts::10 82 # Per bank write bursts
system.physmem.perBankRdBursts::11 51 # Per bank write bursts
system.physmem.perBankRdBursts::12 133 # Per bank write bursts
system.physmem.perBankRdBursts::13 67 # Per bank write bursts
system.physmem.perBankRdBursts::14 98 # Per bank write bursts
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 164764000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1043 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 988 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 312.956938 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 206.620752 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 291.549711 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 58 27.75% 27.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 50 23.92% 51.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 39 18.66% 70.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 19 9.09% 79.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 9 4.31% 83.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 8 3.83% 87.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation
system.physmem.totQLat 16727250 # Total ticks spent queuing
system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers
system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.16 # Data bus utilization in percentage
system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 829 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 157971.24 # Average gap between requests
system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 778260 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 409860 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3348660 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ)
system.physmem_0.averagePower 555.750261 # Core power per rank (mW)
system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states
system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states
system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ)
system.physmem_1.averagePower 547.351788 # Core power per rank (mW)
system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states
system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states
system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 31695 # Number of BP lookups
system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15330 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 45 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 165091500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 330183 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 113337 # Number of instructions committed
system.cpu.committedOps 113337 # Number of ops (including micro ops) committed
system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 2.913285 # CPI: cycles per instruction
system.cpu.ipc 0.343255 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction
system.cpu.op_class_0::IntAlu 69651 61.45% 61.49% # Class of committed instruction
system.cpu.op_class_0::IntMult 122 0.11% 61.60% # Class of committed instruction
system.cpu.op_class_0::IntDiv 26 0.02% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.63% # Class of committed instruction
system.cpu.op_class_0::MemRead 23780 20.98% 82.61% # Class of committed instruction
system.cpu.op_class_0::MemWrite 19713 17.39% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 113337 # Class of committed instruction
system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked
system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits
system.cpu.dcache.overall_hits::total 43871 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 453 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses
system.cpu.dcache.overall_misses::total 453 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 186 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 186 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 190 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 198 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 198 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 263 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010045 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 14 # number of replacements
system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses
system.cpu.icache.tags.data_accesses 101683 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits
system.cpu.icache.overall_hits::total 49670 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses
system.cpu.icache.overall_misses::total 781 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 14 # number of writebacks
system.cpu.icache.writebacks::total 14 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1043 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 556 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 437 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031830 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 9507 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 9507 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 14 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 14 # number of WritebackClean hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 198 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 198 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 781 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 781 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 781 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 262 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1043 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 781 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 262 # number of overall misses
system.cpu.l2cache.overall_misses::total 1043 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 198 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 781 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 781 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 781 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 263 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1044 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 781 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 263 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1044 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.984615 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.984615 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.996198 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.999042 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 198 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 198 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 781 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 781 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 262 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1043 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 262 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.984615 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.984615 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.999042 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 846 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 14 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 781 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 526 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2102 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 67712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1044 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.030949 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1043 99.90% 99.90% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1044 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 543000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1171500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 394500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 1043 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 845 # Transaction distribution
system.membus.trans_dist::ReadExReq 198 # Transaction distribution
system.membus.trans_dist::ReadExResp 198 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 845 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2086 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2086 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66752 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 66752 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1043 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1043 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1043 # Request fanout histogram
system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
|