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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000535 # Number of seconds simulated
sim_ticks 535115500 # Number of ticks simulated
final_tick 535115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 114251239 # Simulator tick rate (ticks/s)
host_mem_usage 237088 # Number of bytes of host memory used
host_seconds 4.68 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 81574 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 80110 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 79121 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 81238 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 80899 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 79820 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 79202 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 79066 # Number of bytes read from this memory
system.physmem.bytes_read::total 641030 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 406208 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5473 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5509 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5540 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5388 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5404 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5375 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5435 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5475 # Number of bytes written to this memory
system.physmem.bytes_written::total 449807 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 11077 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 10999 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10829 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10993 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 11032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10961 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10910 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 11026 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87827 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6347 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5473 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5509 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5540 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5388 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5404 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5375 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5435 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5475 # Number of write requests responded to by this memory
system.physmem.num_writes::total 49946 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 152441856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 149705998 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 147857799 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 151813954 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 151180446 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 149164059 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 148009168 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 147755017 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1197928298 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 759103409 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 10227699 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 10294974 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 10352905 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 10068854 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 10098754 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 10044560 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 10156686 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 10231436 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 840579277 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 759103409 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 162669555 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 160000972 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 158210704 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 161882808 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 161279200 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 159208619 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 158165854 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 157986453 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2038507575 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.num_reads 100000 # number of read accesses completed
system.cpu0.num_writes 55271 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22387 # number of replacements
system.cpu0.l1c.tags.tagsinuse 391.751313 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13331 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.584873 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0 391.751313 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.765139 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.765139 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 338274 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 338274 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8660 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8660 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1174 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1174 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9834 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9834 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9834 # number of overall hits
system.cpu0.l1c.overall_hits::total 9834 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36517 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36517 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23979 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23979 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60496 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60496 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60496 # number of overall misses
system.cpu0.l1c.overall_misses::total 60496 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 647463503 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 647463503 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 554640697 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 554640697 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1202104200 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1202104200 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1202104200 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1202104200 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 45177 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 45177 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 25153 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 70330 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 70330 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808310 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.808310 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953326 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.953326 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.860173 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.860173 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.860173 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.860173 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17730.468083 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 17730.468083 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23130.268026 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 23130.268026 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 19870.804681 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 19870.804681 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 19870.804681 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 19870.804681 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 749854 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs 59820 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.535172 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks 9840 # number of writebacks
system.cpu0.l1c.writebacks::total 9840 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36517 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36517 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23979 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23979 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60496 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60496 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60496 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60496 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9959 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9959 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5475 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15434 # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15434 # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 610946503 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 610946503 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 530662697 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 530662697 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1141609200 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1141609200 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1141609200 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1141609200 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 751203683 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 751203683 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 933372844 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 933372844 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1684576527 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1684576527 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808310 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808310 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953326 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953326 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.860173 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.860173 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16730.468083 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16730.468083 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22130.309729 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22130.309729 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75429.629782 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75429.629782 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 170479.058265 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170479.058265 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109147.112025 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109147.112025 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.num_reads 99085 # number of read accesses completed
system.cpu1.num_writes 54836 # number of write accesses completed
system.cpu1.l1c.tags.replacements 22258 # number of replacements
system.cpu1.l1c.tags.tagsinuse 391.296117 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22654 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.590536 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1 391.296117 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.764250 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.764250 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 336817 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 336817 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8647 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8647 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1131 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1131 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9778 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9778 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9778 # number of overall hits
system.cpu1.l1c.overall_hits::total 9778 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36589 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36589 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23685 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23685 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60274 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60274 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60274 # number of overall misses
system.cpu1.l1c.overall_misses::total 60274 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 652011208 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 652011208 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 548619495 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 548619495 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1200630703 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1200630703 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1200630703 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1200630703 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45236 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45236 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 24816 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 24816 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70052 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70052 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70052 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70052 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808847 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.808847 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954425 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.954425 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.860418 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.860418 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.860418 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.860418 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17819.869578 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 17819.869578 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23163.162128 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 23163.162128 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 19919.545791 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 19919.545791 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 19919.545791 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 19919.545791 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 748495 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs 59422 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.596261 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks
system.cpu1.l1c.writebacks::total 9809 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36589 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36589 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23685 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23685 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60274 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60274 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60274 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60274 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9902 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9902 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5511 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5511 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15413 # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15413 # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 615423208 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 615423208 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 524934495 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 524934495 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1140357703 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1140357703 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1140357703 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1140357703 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 747152224 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 747152224 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 944376752 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 944376752 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1691528976 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1691528976 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808847 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808847 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954425 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954425 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.860418 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.860418 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16819.896909 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16819.896909 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22163.162128 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22163.162128 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 75454.678247 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75454.678247 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 171362.139721 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171362.139721 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 109746.900409 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 109746.900409 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.num_reads 99705 # number of read accesses completed
system.cpu2.num_writes 55132 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22489 # number of replacements
system.cpu2.l1c.tags.tagsinuse 393.363987 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13472 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22889 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.588580 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2 393.363987 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.768289 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.768289 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 339330 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 339330 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8744 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8744 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1142 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1142 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9886 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9886 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9886 # number of overall hits
system.cpu2.l1c.overall_hits::total 9886 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36705 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36705 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23982 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23982 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60687 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60687 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60687 # number of overall misses
system.cpu2.l1c.overall_misses::total 60687 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 655863609 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 655863609 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 555301116 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 555301116 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1211164725 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1211164725 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1211164725 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1211164725 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70573 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70573 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70573 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70573 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807609 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.807609 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954545 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.954545 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.859918 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.859918 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.859918 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.859918 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17868.508623 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 17868.508623 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23154.912685 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 23154.912685 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 19957.564635 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 19957.564635 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 19957.564635 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 19957.564635 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 744784 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs 59741 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.466882 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks 9941 # number of writebacks
system.cpu2.l1c.writebacks::total 9941 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36705 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36705 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23982 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23982 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60687 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60687 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60687 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60687 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9745 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9745 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5541 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5541 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15286 # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 619160609 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 619160609 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 531319116 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 531319116 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1150479725 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1150479725 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1150479725 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1150479725 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 736103391 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 736103391 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 958643718 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 958643718 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1694747109 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1694747109 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807609 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807609 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954545 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954545 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.859918 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.859918 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16868.563111 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16868.563111 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22154.912685 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22154.912685 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75536.520369 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75536.520369 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 173009.153221 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173009.153221 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 110869.233874 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 110869.233874 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.num_reads 99493 # number of read accesses completed
system.cpu3.num_writes 55186 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22493 # number of replacements
system.cpu3.l1c.tags.tagsinuse 393.330553 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13483 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22894 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.588932 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3 393.330553 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.768224 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.768224 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 338296 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 338296 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8738 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8738 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1110 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1110 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9848 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9848 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9848 # number of overall hits
system.cpu3.l1c.overall_hits::total 9848 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36582 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36582 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23939 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23939 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60521 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60521 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60521 # number of overall misses
system.cpu3.l1c.overall_misses::total 60521 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 654319900 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 654319900 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 552232159 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 552232159 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1206552059 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1206552059 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1206552059 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1206552059 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45320 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45320 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 25049 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70369 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70369 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70369 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70369 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807193 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.807193 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955687 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.955687 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.860052 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.860052 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.860052 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.860052 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17886.389481 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 17886.389481 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23068.305234 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 23068.305234 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 19936.089275 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 19936.089275 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 19936.089275 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 19936.089275 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 748969 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs 59958 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.491561 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks 9953 # number of writebacks
system.cpu3.l1c.writebacks::total 9953 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36582 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36582 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23939 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60521 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60521 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60521 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60521 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9878 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9878 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5388 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15266 # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15266 # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 617737900 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 617737900 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 528295159 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 528295159 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1146033059 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1146033059 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1146033059 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1146033059 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 746486832 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 746486832 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 927844496 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 927844496 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1674331328 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1674331328 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807193 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807193 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955687 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955687 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.860052 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.860052 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16886.389481 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16886.389481 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22068.388780 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22068.388780 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75570.645070 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75570.645070 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 172205.734224 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172205.734224 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109677.147124 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109677.147124 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu4.num_reads 99921 # number of read accesses completed
system.cpu4.num_writes 55196 # number of write accesses completed
system.cpu4.l1c.tags.replacements 22380 # number of replacements
system.cpu4.l1c.tags.tagsinuse 392.777413 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13581 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22786 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.596024 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4 392.777413 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.767143 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.767143 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 339211 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 339211 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8862 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8862 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1132 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1132 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9994 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9994 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9994 # number of overall hits
system.cpu4.l1c.overall_hits::total 9994 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36800 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36800 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23778 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23778 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60578 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60578 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60578 # number of overall misses
system.cpu4.l1c.overall_misses::total 60578 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 655197570 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 655197570 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 548908934 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 548908934 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1204106504 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1204106504 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1204106504 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1204106504 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45662 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45662 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 24910 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 24910 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70572 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70572 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70572 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70572 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805922 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.805922 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954556 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.858386 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.858386 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.858386 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.858386 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17804.281793 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 17804.281793 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23084.739423 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 23084.739423 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 19876.960349 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 19876.960349 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 19876.960349 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 19876.960349 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 750268 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs 59848 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.536225 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks 9770 # number of writebacks
system.cpu4.l1c.writebacks::total 9770 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36800 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36800 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23778 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23778 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60578 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60578 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60578 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60578 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9925 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9925 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5406 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5406 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15331 # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15331 # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 618398570 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 618398570 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 525131934 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 525131934 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1143530504 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1143530504 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1143530504 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1143530504 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 750294225 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 750294225 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 944567825 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 944567825 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1694862050 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1694862050 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805922 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805922 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954556 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.858386 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.858386 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16804.308967 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16804.308967 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22084.781479 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22084.781479 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 75596.395466 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75596.395466 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174725.827784 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174725.827784 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 110551.304546 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 110551.304546 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu5.num_reads 99482 # number of read accesses completed
system.cpu5.num_writes 55607 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22456 # number of replacements
system.cpu5.l1c.tags.tagsinuse 392.242325 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13457 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22866 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.588516 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5 392.242325 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.766098 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.766098 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 338143 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 338143 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8578 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8578 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1205 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1205 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits
system.cpu5.l1c.overall_hits::total 9783 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36239 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36239 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 24308 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 24308 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60547 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60547 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60547 # number of overall misses
system.cpu5.l1c.overall_misses::total 60547 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 647043171 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 647043171 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 559180438 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 559180438 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1206223609 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1206223609 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1206223609 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1206223609 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 44817 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 44817 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25513 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25513 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70330 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70330 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808599 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.808599 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952769 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.952769 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.860899 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.860899 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.860899 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.860899 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17854.884820 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 17854.884820 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23003.967336 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 23003.967336 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 19922.103638 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 19922.103638 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 19922.103638 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 19922.103638 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 749399 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs 59952 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.499983 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks 10051 # number of writebacks
system.cpu5.l1c.writebacks::total 10051 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36239 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36239 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24308 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 24308 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60547 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60547 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60547 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60547 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9869 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5375 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5375 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15244 # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15244 # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 610804171 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 610804171 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 534872438 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 534872438 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1145676609 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1145676609 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1145676609 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1145676609 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 745114179 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 745114179 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 938602875 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 938602875 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1683717054 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1683717054 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808599 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808599 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952769 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952769 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.860899 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.860899 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16854.884820 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16854.884820 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22003.967336 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22003.967336 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 75500.474111 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75500.474111 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 174623.790698 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174623.790698 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 110451.131855 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 110451.131855 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu6.num_reads 99231 # number of read accesses completed
system.cpu6.num_writes 55266 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22476 # number of replacements
system.cpu6.l1c.tags.tagsinuse 393.210816 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13488 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22863 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.589949 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6 393.210816 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.767990 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.767990 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 339081 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 339081 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9910 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9910 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9910 # number of overall hits
system.cpu6.l1c.overall_hits::total 9910 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36605 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36605 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 24011 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 24011 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60616 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60616 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60616 # number of overall misses
system.cpu6.l1c.overall_misses::total 60616 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 653690176 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 653690176 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 554778070 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 554778070 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1208468246 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1208468246 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1208468246 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1208468246 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45308 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45308 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 25218 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 25218 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70526 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70526 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70526 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70526 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807915 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.807915 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952137 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.952137 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.859484 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.859484 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.859484 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.859484 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17857.947712 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 17857.947712 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23105.163050 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 23105.163050 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 19936.456480 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 19936.456480 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 19936.456480 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 19936.456480 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 748048 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs 59929 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.482237 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks 9811 # number of writebacks
system.cpu6.l1c.writebacks::total 9811 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36605 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36605 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24011 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 24011 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60616 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60616 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60616 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60616 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9828 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5436 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5436 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15264 # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15264 # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 617085176 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 617085176 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 530767070 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 530767070 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1147852246 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1147852246 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1147852246 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1147852246 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 743889866 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 743889866 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 938428736 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 938428736 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1682318602 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1682318602 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807915 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807915 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952137 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952137 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.859484 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.859484 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16857.947712 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16857.947712 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22105.163050 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22105.163050 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 75690.869556 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75690.869556 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 172632.217807 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172632.217807 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 110214.793108 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 110214.793108 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu7.num_reads 99956 # number of read accesses completed
system.cpu7.num_writes 55531 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22312 # number of replacements
system.cpu7.l1c.tags.tagsinuse 393.161929 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13691 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22714 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.602756 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7 393.161929 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.767894 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.767894 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 338939 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 338939 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8916 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8916 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 10081 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 10081 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 10081 # number of overall hits
system.cpu7.l1c.overall_hits::total 10081 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36493 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36493 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23963 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23963 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60456 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60456 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60456 # number of overall misses
system.cpu7.l1c.overall_misses::total 60456 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 649044669 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 649044669 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 555516702 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 555516702 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1204561371 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1204561371 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1204561371 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1204561371 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45409 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 25128 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70537 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70537 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70537 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70537 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803651 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.803651 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953637 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.953637 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.857082 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.857082 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.857082 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.857082 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17785.456636 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 17785.456636 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23182.268581 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 23182.268581 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 19924.595921 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 19924.595921 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 19924.595921 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 19924.595921 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 753584 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs 60106 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.537584 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks 9825 # number of writebacks
system.cpu7.l1c.writebacks::total 9825 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36493 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36493 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23963 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23963 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60456 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60456 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60456 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60456 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9946 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5477 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5477 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15423 # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15423 # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 612553669 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 612553669 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 531553702 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 531553702 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1144107371 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1144107371 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1144107371 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1144107371 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 750008205 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 750008205 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 931574803 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 931574803 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1681583008 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1681583008 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803651 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803651 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953637 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953637 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.857082 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.857082 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16785.511441 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16785.511441 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22182.268581 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22182.268581 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75408.023829 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75408.023829 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 170088.516158 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170088.516158 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 109030.863516 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 109030.863516 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 13679 # number of replacements
system.l2c.tags.tagsinuse 785.030982 # Cycle average of tags in use
system.l2c.tags.total_refs 164295 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 14481 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 11.345556 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 728.912576 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 7.109869 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 7.264593 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 7.067016 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 7.280147 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 6.468572 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 6.873708 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 6.969066 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 7.085434 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.711829 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.006943 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.007094 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.006901 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.006317 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.006713 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.006806 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.006919 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.766632 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 802 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 2100989 # Number of tag accesses
system.l2c.tags.data_accesses 2100989 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 77660 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 77660 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0 265 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 275 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 255 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 290 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 283 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 292 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 297 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 302 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2259 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1784 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1764 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1831 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1735 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1757 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1864 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1767 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1780 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 14282 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0 10784 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1 10837 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2 10882 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3 10814 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4 10969 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5 10782 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6 10825 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7 10836 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 86729 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0 12568 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12601 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12713 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12549 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12726 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12646 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12592 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12616 # number of demand (read+write) hits
system.l2c.demand_hits::total 101011 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12568 # number of overall hits
system.l2c.overall_hits::cpu1 12601 # number of overall hits
system.l2c.overall_hits::cpu2 12713 # number of overall hits
system.l2c.overall_hits::cpu3 12549 # number of overall hits
system.l2c.overall_hits::cpu4 12726 # number of overall hits
system.l2c.overall_hits::cpu5 12646 # number of overall hits
system.l2c.overall_hits::cpu6 12592 # number of overall hits
system.l2c.overall_hits::cpu7 12616 # number of overall hits
system.l2c.overall_hits::total 101011 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0 1935 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 2063 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 2062 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 2061 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 2025 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 2056 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 1973 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 2050 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 16225 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4717 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4573 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4643 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4618 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4604 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4681 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4664 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4698 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 37198 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0 701 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1 741 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2 707 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3 750 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4 700 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5 714 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6 696 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7 703 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 5712 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0 5418 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5314 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5350 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5368 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5304 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5395 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5360 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5401 # number of demand (read+write) misses
system.l2c.demand_misses::total 42910 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5418 # number of overall misses
system.l2c.overall_misses::cpu1 5314 # number of overall misses
system.l2c.overall_misses::cpu2 5350 # number of overall misses
system.l2c.overall_misses::cpu3 5368 # number of overall misses
system.l2c.overall_misses::cpu4 5304 # number of overall misses
system.l2c.overall_misses::cpu5 5395 # number of overall misses
system.l2c.overall_misses::cpu6 5360 # number of overall misses
system.l2c.overall_misses::cpu7 5401 # number of overall misses
system.l2c.overall_misses::total 42910 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0 33570299 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 36327486 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 35657979 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 35008978 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 34589470 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 34691475 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 32410475 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 35465977 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 277722139 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 161829189 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 155335873 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 157770030 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 156623200 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 158516385 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 158789879 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 159063367 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 159738542 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1267666465 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0 49231417 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1 51778912 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2 49960071 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3 52497915 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4 48409406 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5 49972406 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6 48755897 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7 49161911 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 399767935 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0 211060606 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 207114785 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 207730101 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 209121115 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 206925791 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 208762285 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 207819264 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 208900453 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 1667434400 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 211060606 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 207114785 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 207730101 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 209121115 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 206925791 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 208762285 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 207819264 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 208900453 # number of overall miss cycles
system.l2c.overall_miss_latency::total 1667434400 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 77660 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 77660 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2200 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2338 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2317 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2351 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2308 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2348 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2270 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2352 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18484 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6501 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6337 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6474 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6353 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6361 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6545 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6431 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6478 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 51480 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0 11485 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1 11578 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2 11589 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3 11564 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4 11669 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5 11496 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6 11521 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7 11539 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 92441 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17986 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17915 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 18063 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17917 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 18030 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 18041 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17952 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 18017 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 143921 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17986 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17915 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 18063 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17917 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 18030 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 18041 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17952 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 18017 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 143921 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.879545 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.882378 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.889944 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.876648 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.877383 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.875639 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.869163 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.871599 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.877786 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.725581 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.721635 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.717176 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.726901 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.723786 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.715202 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.725237 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.725224 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.722572 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0 0.061036 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1 0.064001 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2 0.061006 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3 0.064856 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4 0.059988 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5 0.062109 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6 0.060411 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7 0.060924 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.061791 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0 0.301234 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.296623 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.296186 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.299604 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.294176 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.299041 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.298574 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.299772 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.298150 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.301234 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.296623 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.296186 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.299604 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.294176 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.299041 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.298574 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.299772 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.298150 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 17348.991731 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 17609.057683 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 17292.909311 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 16986.403688 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 17081.219753 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 16873.285506 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 16427.002027 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 17300.476585 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 17116.926903 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 34307.650837 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 33968.045703 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 33980.191686 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 33915.807709 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 34430.144440 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 33922.212989 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 34104.495497 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 34001.392507 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 34078.887709 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70230.266762 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69877.074224 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 70664.881188 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69997.220000 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69156.294286 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69989.364146 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70051.576149 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69931.594595 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 69987.383578 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 38955.445921 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 38975.307678 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 38828.056262 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 38956.988636 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 39013.158183 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 38695.511585 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 38772.250746 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 38678.106462 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 38858.876719 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 38955.445921 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 38975.307678 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 38828.056262 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 38956.988636 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 39013.158183 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 38695.511585 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 38772.250746 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 38678.106462 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 38858.876719 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 15775 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 2328 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 6.776203 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 6347 # number of writebacks
system.l2c.writebacks::total 6347 # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 8 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 8 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 9 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 45 # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0 7 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1 13 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2 7 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3 10 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4 13 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6 9 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 71 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 15 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 18 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 15 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 18 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 116 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 1217 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 1217 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1934 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 2063 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 2062 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 2060 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 2025 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 2055 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 1973 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 2050 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 16222 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4714 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4566 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4635 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4615 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4599 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4673 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4662 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4689 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 37153 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0 694 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1 728 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2 700 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3 740 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4 687 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5 706 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6 687 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7 699 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 5641 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5408 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5294 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5335 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5355 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5286 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5379 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5349 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5388 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 42794 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5408 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5294 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5335 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5355 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5286 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5379 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5349 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5388 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 42794 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0 9958 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1 9902 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2 9745 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3 9878 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4 9925 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5 9869 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6 9828 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7 9946 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 79051 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0 5475 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1 5509 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2 5540 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3 5388 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4 5404 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5 5375 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6 5435 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7 5475 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 43601 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0 15433 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1 15411 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2 15285 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3 15266 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4 15329 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5 15244 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6 15263 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7 15421 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 122652 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 40213943 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 42852043 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 42722752 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 42718914 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 41954263 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 42662066 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 40886253 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 42452590 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 336462824 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 114483428 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 109319242 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 111132111 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 110326921 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 112301120 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 111711839 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 112344259 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 112421561 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 894040481 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 41942368 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 43799223 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42582401 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 44577742 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40998173 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 42436532 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41443209 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 41880731 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 339660379 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 156425796 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 153118465 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 153714512 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 154904663 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 153299293 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 154148371 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 153787468 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 154302292 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1233700860 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 156425796 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 153118465 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 153714512 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 154904663 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 153299293 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 154148371 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 153787468 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 154302292 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1233700860 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 532537334 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 530034961 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 522091524 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 528677272 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 531067932 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 528334987 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 526505398 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 532738235 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 4231987643 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302507401 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 304491446 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 306673088 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 296941482 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 299721877 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 297975047 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 302462757 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 303375300 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2414148398 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 835044735 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 834526407 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 828764612 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 825618754 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 830789809 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 826310034 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 828968155 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 836113535 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6646136041 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.879091 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.882378 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889944 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.876223 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877383 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875213 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.869163 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871599 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.877624 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725119 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.720530 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.715941 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.726428 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.723000 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.713980 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.724926 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.723835 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.721698 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060427 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062878 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060402 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063992 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.058874 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.061413 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.059630 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060577 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061023 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.297344 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.297344 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20793.145295 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20771.712555 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.084384 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20737.336893 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20718.154568 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20760.129440 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20722.885454 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20708.580488 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20741.143139 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24285.835384 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 23942.015331 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 23976.722977 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23906.158397 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24418.595347 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 23905.807618 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24097.867653 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 23975.594157 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 24063.749388 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 60435.688761 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 60163.767857 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 60832.001429 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 60240.191892 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59677.107715 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60108.402266 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 60324.903930 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59915.208870 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 60212.795426 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53478.342438 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53528.071198 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53575.323140 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53520.679490 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53508.103980 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53534.804641 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53571.977818 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53563.064046 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53534.903328 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 55252.493333 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 55271.636595 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 55356.153069 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 55111.633630 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 55462.967617 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 55437.218047 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 55650.921251 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 55411.013699 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 55369.106167 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 54107.738936 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 54151.346895 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 54220.779326 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 54082.192716 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 54197.260682 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 54205.591315 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 54312.268558 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 54219.151482 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 54186.935729 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.snoop_filter.tot_requests 125196 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 119242 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq 79046 # Transaction distribution
system.membus.trans_dist::ReadResp 84668 # Transaction distribution
system.membus.trans_dist::WriteReq 43599 # Transaction distribution
system.membus.trans_dist::WriteResp 43596 # Transaction distribution
system.membus.trans_dist::WritebackDirty 6347 # Transaction distribution
system.membus.trans_dist::CleanEvict 1243 # Transaction distribution
system.membus.trans_dist::UpgradeReq 60999 # Transaction distribution
system.membus.trans_dist::ReadExReq 49250 # Transaction distribution
system.membus.trans_dist::ReadExResp 3150 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 5631 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377529 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 377529 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1090828 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1090828 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 56847 # Total snoops (count)
system.membus.snoop_fanout::samples 245688 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 245688 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 245688 # Request fanout histogram
system.membus.reqLayer0.occupancy 290283631 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 54.2 # Layer utilization (%)
system.membus.respLayer0.occupancy 245575000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 45.9 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 665524 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 283935 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 335837 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 12315 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 5744 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 6571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 79051 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 371557 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43601 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43596 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 84007 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 105887 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29231 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29230 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 162413 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 162411 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 292528 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133251 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133734 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133419 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133559 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133487 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133484 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133586 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1068067 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1785416 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1780080 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1798067 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1787232 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784031 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801672 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1781660 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1785403 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14303561 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 335445 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 626448 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.148675 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.987271 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 174709 27.89% 27.89% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 258191 41.22% 69.10% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 133874 21.37% 90.47% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 46929 7.49% 97.97% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 11007 1.76% 99.72% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 1601 0.26% 99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 133 0.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 626448 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 498178453 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 102533331 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 102040683 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 19.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 102532818 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 102294677 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 19.1 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 102527849 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 102329742 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 19.1 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 102510939 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 19.2 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 102349372 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 19.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
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