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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000014 # Number of seconds simulated
sim_ticks 13821 # Number of ticks simulated
final_tick 13821 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 213268 # Simulator tick rate (ticks/s)
host_mem_usage 483832 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::dir_cntrl0 16384 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 16384 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::dir_cntrl0 896 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 896 # Number of bytes written to this memory
system.mem_ctrls.num_reads::dir_cntrl0 256 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 256 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::dir_cntrl0 14 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 14 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::dir_cntrl0 1185442443 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 1185442443 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::dir_cntrl0 64828884 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 64828884 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::dir_cntrl0 1250271326 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1250271326 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 256 # Number of read requests accepted
system.mem_ctrls.writeReqs 14 # Number of write requests accepted
system.mem_ctrls.readBursts 256 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 14 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 15488 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 896 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 16384 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 896 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 14 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 99 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 62 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 13710 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 256 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 14 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 199 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 36 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 6 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 15 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 913.066667 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 883.543279 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 210.139908 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 3 20.00% 20.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 1 6.67% 26.67% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 11 73.33% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 15 # Bytes accessed per row activation
system.mem_ctrls.totQLat 2184 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 6782 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 1210 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 9.02 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 28.02 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 1120.61 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 1185.44 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 64.83 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 8.75 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 8.75 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 3.35 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 223 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 92.15 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 50.78 # Average gap between requests
system.mem_ctrls.pageHitRate 87.11 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 135660 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 57960 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 2764608 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 2757888 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 44928 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.actPowerDownEnergy 3490680 # Energy for active power-down per rank (pJ)
system.mem_ctrls_0.prePowerDownEnergy 384 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.mem_ctrls_0.totalEnergy 9866748 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 713.895377 # Core power per rank (mW)
system.mem_ctrls_0.totalIdleTime 7568 # Total Idle time Per DRAM Rank
system.mem_ctrls_0.memoryStateTime::IDLE 89 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 260 # Time in different power states
system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 1 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 5816 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 7655 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 112176 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
system.mem_ctrls_1.prePowerDownEnergy 2217600 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.mem_ctrls_1.totalEnergy 5939616 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 429.752985 # Core power per rank (mW)
system.mem_ctrls_1.totalIdleTime 0 # Total Idle time Per DRAM Rank
system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 260 # Time in different power states
system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 5775 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 63
system.ruby.outstanding_req_hist_seqr::mean 12.873016
system.ruby.outstanding_req_hist_seqr::gmean 11.658152
system.ruby.outstanding_req_hist_seqr::stdev 4.202503
system.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 16 25.40% 60.32% | 25 39.68% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 63
system.ruby.outstanding_req_hist_coalsr::bucket_size 2
system.ruby.outstanding_req_hist_coalsr::max_bucket 19
system.ruby.outstanding_req_hist_coalsr::samples 872
system.ruby.outstanding_req_hist_coalsr::mean 2.547018
system.ruby.outstanding_req_hist_coalsr::gmean 2.158955
system.ruby.outstanding_req_hist_coalsr::stdev 1.537168
system.ruby.outstanding_req_hist_coalsr | 236 27.06% 27.06% | 460 52.75% 79.82% | 126 14.45% 94.27% | 40 4.59% 98.85% | 9 1.03% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_coalsr::total 872
system.ruby.latency_hist_seqr::bucket_size 1024
system.ruby.latency_hist_seqr::max_bucket 10239
system.ruby.latency_hist_seqr::samples 48
system.ruby.latency_hist_seqr::mean 3315.854167
system.ruby.latency_hist_seqr::gmean 1841.298781
system.ruby.latency_hist_seqr::stdev 1907.716848
system.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 20 41.67% 91.67% | 4 8.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 48
system.ruby.latency_hist_coalsr::bucket_size 128
system.ruby.latency_hist_coalsr::max_bucket 1279
system.ruby.latency_hist_coalsr::samples 858
system.ruby.latency_hist_coalsr::mean 215.358974
system.ruby.latency_hist_coalsr::gmean 107.894342
system.ruby.latency_hist_coalsr::stdev 237.470134
system.ruby.latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_coalsr::total 858
system.ruby.hit_latency_hist_seqr::bucket_size 1024
system.ruby.hit_latency_hist_seqr::max_bucket 10239
system.ruby.hit_latency_hist_seqr::samples 42
system.ruby.hit_latency_hist_seqr::mean 3644.142857
system.ruby.hit_latency_hist_seqr::gmean 2737.850881
system.ruby.hit_latency_hist_seqr::stdev 1757.652877
system.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 42
system.ruby.miss_latency_hist_seqr::bucket_size 512
system.ruby.miss_latency_hist_seqr::max_bucket 5119
system.ruby.miss_latency_hist_seqr::samples 6
system.ruby.miss_latency_hist_seqr::mean 1017.833333
system.ruby.miss_latency_hist_seqr::gmean 114.584426
system.ruby.miss_latency_hist_seqr::stdev 1278.753677
system.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 6
system.ruby.miss_latency_hist_coalsr::bucket_size 128
system.ruby.miss_latency_hist_coalsr::max_bucket 1279
system.ruby.miss_latency_hist_coalsr::samples 858
system.ruby.miss_latency_hist_coalsr::mean 215.358974
system.ruby.miss_latency_hist_coalsr::gmean 107.894342
system.ruby.miss_latency_hist_coalsr::stdev 237.470134
system.ruby.miss_latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_coalsr::total 858
system.ruby.L1Cache.incomplete_times_seqr 6
system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
system.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses
system.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses
system.cp_cntrl0.L1D0cache.num_data_array_writes 43 # number of data array writes
system.cp_cntrl0.L1D0cache.num_tag_array_reads 155 # number of tag array reads
system.cp_cntrl0.L1D0cache.num_tag_array_writes 41 # number of tag array writes
system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits
system.cp_cntrl0.L1D1cache.demand_misses 45 # Number of cache demand misses
system.cp_cntrl0.L1D1cache.demand_accesses 45 # Number of cache demand accesses
system.cp_cntrl0.L1D1cache.num_data_array_writes 42 # number of data array writes
system.cp_cntrl0.L1D1cache.num_tag_array_reads 74 # number of tag array reads
system.cp_cntrl0.L1D1cache.num_tag_array_writes 42 # number of tag array writes
system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.cp_cntrl0.L1Icache.demand_misses 3 # Number of cache demand misses
system.cp_cntrl0.L1Icache.demand_accesses 3 # Number of cache demand accesses
system.cp_cntrl0.L1Icache.num_tag_array_reads 3 # number of tag array reads
system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
system.cp_cntrl0.L2cache.demand_misses 93 # Number of cache demand misses
system.cp_cntrl0.L2cache.demand_accesses 93 # Number of cache demand accesses
system.cp_cntrl0.L2cache.num_data_array_reads 81 # number of data array reads
system.cp_cntrl0.L2cache.num_data_array_writes 85 # number of data array writes
system.cp_cntrl0.L2cache.num_tag_array_reads 372 # number of tag array reads
system.cp_cntrl0.L2cache.num_tag_array_writes 362 # number of tag array writes
system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.cp_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load
system.cp_cntrl0.sequencer.store_waiting_on_store 4 # Number of times a store aliased with a pending store
system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store
system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
system.dir_cntrl0.L3CacheMemory.num_data_array_writes 365 # number of data array writes
system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 372 # number of tag array reads
system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 369 # number of tag array writes
system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 9126 # number of stalls caused by tag array
system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 4922 # number of stalls caused by data array
system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199915
system.ruby.network.ext_links00.int_node.msg_count.Control::0 300
system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 372
system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 383
system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 217
system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 67
system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 71
system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 295
system.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2400
system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 2976
system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 27576
system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1736
system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4824
system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 568
system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2360
system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links01.int_node.percent_links_utilized 0.123680
system.ruby.network.ext_links01.int_node.msg_count.Control::0 216
system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 155
system.ruby.network.ext_links01.int_node.msg_count.Response_Data::2 95
system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 207
system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 67
system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 71
system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 81
system.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1728
system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1240
system.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2 6840
system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1656
system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4824
system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 568
system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 648
system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl0.L1cache.num_data_array_reads 16 # number of data array reads
system.tcp_cntrl0.L1cache.num_data_array_writes 112 # number of data array writes
system.tcp_cntrl0.L1cache.num_tag_array_reads 309 # number of tag array reads
system.tcp_cntrl0.L1cache.num_tag_array_writes 300 # number of tag array writes
system.tcp_cntrl0.L1cache.num_tag_array_stalls 28 # number of stalls caused by tag array
system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl0.coalescer.gpu_ld_misses 1 # loads that miss in the GPU
system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl0.coalescer.gpu_st_misses 19 # stores that miss in the GPU
system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links02.int_node.percent_links_utilized 0.172944
system.ruby.network.ext_links02.int_node.msg_count.Control::0 84
system.ruby.network.ext_links02.int_node.msg_count.Control::1 789
system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 217
system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 823
system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 288
system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1594
system.ruby.network.ext_links02.int_node.msg_count.Response_Control::2 10
system.ruby.network.ext_links02.int_node.msg_count.Response_Control::3 2
system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 214
system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 810
system.ruby.network.ext_links02.int_node.msg_bytes.Control::0 672
system.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6312
system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1736
system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6584
system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 20736
system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 114768
system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2 80
system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3 16
system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1712
system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6480
system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl1.L1cache.num_data_array_reads 11 # number of data array reads
system.tcp_cntrl1.L1cache.num_data_array_writes 108 # number of data array writes
system.tcp_cntrl1.L1cache.num_tag_array_reads 298 # number of tag array reads
system.tcp_cntrl1.L1cache.num_tag_array_writes 285 # number of tag array writes
system.tcp_cntrl1.L1cache.num_tag_array_stalls 43 # number of stalls caused by tag array
system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 11 # stores that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl1.coalescer.gpu_st_misses 20 # stores that miss in the GPU
system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl2.L1cache.num_data_array_reads 11 # number of data array reads
system.tcp_cntrl2.L1cache.num_data_array_writes 106 # number of data array writes
system.tcp_cntrl2.L1cache.num_tag_array_reads 286 # number of tag array reads
system.tcp_cntrl2.L1cache.num_tag_array_writes 275 # number of tag array writes
system.tcp_cntrl2.L1cache.num_tag_array_stalls 42 # number of stalls caused by tag array
system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers
system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl2.coalescer.gpu_ld_misses 1 # loads that miss in the GPU
system.tcp_cntrl2.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP
system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers
system.tcp_cntrl2.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl2.coalescer.gpu_st_misses 18 # stores that miss in the GPU
system.tcp_cntrl2.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl2.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl2.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl2.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl3.L1cache.num_data_array_reads 8 # number of data array reads
system.tcp_cntrl3.L1cache.num_data_array_writes 95 # number of data array writes
system.tcp_cntrl3.L1cache.num_tag_array_reads 260 # number of tag array reads
system.tcp_cntrl3.L1cache.num_tag_array_writes 253 # number of tag array writes
system.tcp_cntrl3.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array
system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array
system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 12 # TCP to TCP load transfers
system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl3.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl3.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP
system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 59 # TCP to TCP store transfers
system.tcp_cntrl3.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl3.coalescer.gpu_st_misses 17 # stores that miss in the GPU
system.tcp_cntrl3.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl3.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl3.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl3.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl4.L1cache.num_data_array_reads 16 # number of data array reads
system.tcp_cntrl4.L1cache.num_data_array_writes 117 # number of data array writes
system.tcp_cntrl4.L1cache.num_tag_array_reads 309 # number of tag array reads
system.tcp_cntrl4.L1cache.num_tag_array_writes 299 # number of tag array writes
system.tcp_cntrl4.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array
system.tcp_cntrl4.L1cache.num_data_array_stalls 4 # number of stalls caused by data array
system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers
system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl4.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl4.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP
system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers
system.tcp_cntrl4.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl4.coalescer.gpu_st_misses 26 # stores that miss in the GPU
system.tcp_cntrl4.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl4.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl4.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl4.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl5.L1cache.num_data_array_reads 9 # number of data array reads
system.tcp_cntrl5.L1cache.num_data_array_writes 101 # number of data array writes
system.tcp_cntrl5.L1cache.num_tag_array_reads 276 # number of tag array reads
system.tcp_cntrl5.L1cache.num_tag_array_writes 266 # number of tag array writes
system.tcp_cntrl5.L1cache.num_tag_array_stalls 22 # number of stalls caused by tag array
system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 3 # TCP to TCP load transfers
system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl5.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl5.coalescer.gpu_tcp_st_hits 8 # stores that hit in the TCP
system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 67 # TCP to TCP store transfers
system.tcp_cntrl5.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl5.coalescer.gpu_st_misses 22 # stores that miss in the GPU
system.tcp_cntrl5.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl5.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl5.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl5.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl6.L1cache.num_data_array_reads 15 # number of data array reads
system.tcp_cntrl6.L1cache.num_data_array_writes 120 # number of data array writes
system.tcp_cntrl6.L1cache.num_tag_array_reads 336 # number of tag array reads
system.tcp_cntrl6.L1cache.num_tag_array_writes 330 # number of tag array writes
system.tcp_cntrl6.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array
system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers
system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl6.coalescer.gpu_ld_misses 1 # loads that miss in the GPU
system.tcp_cntrl6.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
system.tcp_cntrl6.coalescer.gpu_tcp_st_transfers 86 # TCP to TCP store transfers
system.tcp_cntrl6.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl6.coalescer.gpu_st_misses 20 # stores that miss in the GPU
system.tcp_cntrl6.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl6.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl6.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl6.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl7.L1cache.num_data_array_reads 13 # number of data array reads
system.tcp_cntrl7.L1cache.num_data_array_writes 101 # number of data array writes
system.tcp_cntrl7.L1cache.num_tag_array_reads 275 # number of tag array reads
system.tcp_cntrl7.L1cache.num_tag_array_writes 266 # number of tag array writes
system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array
system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers
system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl7.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl7.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP
system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 66 # TCP to TCP store transfers
system.tcp_cntrl7.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl7.coalescer.gpu_st_misses 18 # stores that miss in the GPU
system.tcp_cntrl7.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl7.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl7.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl7.coalescer.cp_ld_misses 0 # loads that miss in the GPU
system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU
system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
system.sqc_cntrl0.L1cache.num_data_array_reads 12 # number of data array reads
system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes
system.sqc_cntrl0.L1cache.num_tag_array_reads 23 # number of tag array reads
system.sqc_cntrl0.L1cache.num_tag_array_writes 23 # number of tag array writes
system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
system.sqc_cntrl1.L1cache.num_data_array_reads 12 # number of data array reads
system.sqc_cntrl1.L1cache.num_data_array_writes 12 # number of data array writes
system.sqc_cntrl1.L1cache.num_tag_array_reads 23 # number of tag array reads
system.sqc_cntrl1.L1cache.num_tag_array_writes 23 # number of tag array writes
system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
system.tccdir_cntrl0.directory.num_tag_array_reads 896 # number of tag array reads
system.tccdir_cntrl0.directory.num_tag_array_writes 882 # number of tag array writes
system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 1389
system.ruby.network.msg_count.Request_Control 1567
system.ruby.network.msg_count.Response_Data 2360
system.ruby.network.msg_count.Response_Control 436
system.ruby.network.msg_count.Writeback_Data 134
system.ruby.network.msg_count.Writeback_Control 142
system.ruby.network.msg_count.Unblock_Control 1400
system.ruby.network.msg_byte.Control 11112
system.ruby.network.msg_byte.Request_Control 12536
system.ruby.network.msg_byte.Response_Data 169920
system.ruby.network.msg_byte.Response_Control 3488
system.ruby.network.msg_byte.Writeback_Data 9648
system.ruby.network.msg_byte.Writeback_Control 1136
system.ruby.network.msg_byte.Unblock_Control 11200
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.254594
system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 372
system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85
system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 217
system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 67
system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 295
system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 2976
system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2 6120
system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1736
system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4824
system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2360
system.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.115879
system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 216
system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 82
system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 71
system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1728
system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5904
system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 568
system.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.229271
system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 84
system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 216
system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 672
system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 15552
system.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.115879
system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 216
system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 82
system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 71
system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1728
system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5904
system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 568
system.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.131480
system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 155
system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 13
system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 207
system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 67
system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 81
system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1240
system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 936
system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1656
system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4824
system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 648
system.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.116105
system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 100
system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 103
system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 800
system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7416
system.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.109661
system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 97
system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 97
system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 776
system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 6984
system.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.108078
system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 92
system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 96
system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 736
system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 6912
system.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.099260
system.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1 86
system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 88
system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1 688
system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3 6336
system.ruby.network.ext_links02.int_node.throttle4.link_utilization 0.116557
system.ruby.network.ext_links02.int_node.throttle4.msg_count.Control::1 104
system.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3 103
system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Control::1 832
system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3 7416
system.ruby.network.ext_links02.int_node.throttle5.link_utilization 0.103556
system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1 88
system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3 92
system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1 704
system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3 6624
system.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.129558
system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 111
system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 115
system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 888
system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8280
system.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.104687
system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 89
system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 93
system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1 712
system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3 6696
system.ruby.network.ext_links02.int_node.throttle8.link_utilization 0
system.ruby.network.ext_links02.int_node.throttle9.link_utilization 1.210793
system.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0 84
system.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1 823
system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2 216
system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3 783
system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Control::3 2
system.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5 810
system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0 672
system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1 6584
system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2 15552
system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3 56376
system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3 16
system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6480
system.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013453
system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 11
system.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3 12
system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 88
system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3 864
system.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.013453
system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 11
system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 12
system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 88
system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 864
system.ruby.network.ext_links02.int_node.throttle12.link_utilization 0.123114
system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0 217
system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2 72
system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Control::2 10
system.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4 214
system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0 1736
system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2 5184
system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Control::2 80
system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4 1712
system.ruby.CorePair_Controller.C0_Load_L1miss 1 0.00% 0.00%
system.ruby.CorePair_Controller.C1_Load_L1miss 2 0.00% 0.00%
system.ruby.CorePair_Controller.Ifetch0_L1miss 2 0.00% 0.00%
system.ruby.CorePair_Controller.Ifetch1_L1miss 1 0.00% 0.00%
system.ruby.CorePair_Controller.C0_Store_L1miss 45 0.00% 0.00%
system.ruby.CorePair_Controller.C0_Store_L1hit 2 0.00% 0.00%
system.ruby.CorePair_Controller.C1_Store_L1miss 72 0.00% 0.00%
system.ruby.CorePair_Controller.NB_AckS 4 0.00% 0.00%
system.ruby.CorePair_Controller.NB_AckM 78 0.00% 0.00%
system.ruby.CorePair_Controller.NB_AckWB 71 0.00% 0.00%
system.ruby.CorePair_Controller.L1D0_Repl 11 0.00% 0.00%
system.ruby.CorePair_Controller.L2_Repl 35555 0.00% 0.00%
system.ruby.CorePair_Controller.PrbInvData 212 0.00% 0.00%
system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00%
system.ruby.CorePair_Controller.I.C0_Load_L1miss 1 0.00% 0.00%
system.ruby.CorePair_Controller.I.C1_Load_L1miss 2 0.00% 0.00%
system.ruby.CorePair_Controller.I.Ifetch0_L1miss 2 0.00% 0.00%
system.ruby.CorePair_Controller.I.Ifetch1_L1miss 1 0.00% 0.00%
system.ruby.CorePair_Controller.I.C0_Store_L1miss 41 0.00% 0.00%
system.ruby.CorePair_Controller.I.C1_Store_L1miss 38 0.00% 0.00%
system.ruby.CorePair_Controller.I.PrbInvData 198 0.00% 0.00%
system.ruby.CorePair_Controller.I.PrbShrData 4 0.00% 0.00%
system.ruby.CorePair_Controller.S.L2_Repl 3 0.00% 0.00%
system.ruby.CorePair_Controller.S.PrbInvData 1 0.00% 0.00%
system.ruby.CorePair_Controller.M0.C0_Store_L1hit 2 0.00% 0.00%
system.ruby.CorePair_Controller.M0.L2_Repl 33 0.00% 0.00%
system.ruby.CorePair_Controller.M0.PrbInvData 6 0.00% 0.00%
system.ruby.CorePair_Controller.M1.C0_Store_L1miss 1 0.00% 0.00%
system.ruby.CorePair_Controller.M1.L2_Repl 36 0.00% 0.00%
system.ruby.CorePair_Controller.M1.PrbInvData 3 0.00% 0.00%
system.ruby.CorePair_Controller.I_M0.C1_Store_L1miss 5 0.00% 0.00%
system.ruby.CorePair_Controller.I_M0.NB_AckM 35 0.00% 0.00%
system.ruby.CorePair_Controller.I_M0.L1D0_Repl 11 0.00% 0.00%
system.ruby.CorePair_Controller.I_M0.L2_Repl 15350 0.00% 0.00%
system.ruby.CorePair_Controller.I_M1.C0_Store_L1miss 3 0.00% 0.00%
system.ruby.CorePair_Controller.I_M1.NB_AckM 35 0.00% 0.00%
system.ruby.CorePair_Controller.I_M1.L2_Repl 14410 0.00% 0.00%
system.ruby.CorePair_Controller.I_M0M1.NB_AckM 5 0.00% 0.00%
system.ruby.CorePair_Controller.I_M0M1.L2_Repl 3283 0.00% 0.00%
system.ruby.CorePair_Controller.I_M1M0.NB_AckM 3 0.00% 0.00%
system.ruby.CorePair_Controller.I_M1M0.L2_Repl 1200 0.00% 0.00%
system.ruby.CorePair_Controller.I_E0S.NB_AckS 1 0.00% 0.00%
system.ruby.CorePair_Controller.I_E0S.L2_Repl 404 0.00% 0.00%
system.ruby.CorePair_Controller.I_E1S.NB_AckS 1 0.00% 0.00%
system.ruby.CorePair_Controller.I_E1S.L2_Repl 392 0.00% 0.00%
system.ruby.CorePair_Controller.ES_I.NB_AckWB 2 0.00% 0.00%
system.ruby.CorePair_Controller.MO_I.NB_AckWB 65 0.00% 0.00%
system.ruby.CorePair_Controller.MO_I.PrbInvData 4 0.00% 0.00%
system.ruby.CorePair_Controller.S0.C1_Store_L1miss 29 0.00% 0.00%
system.ruby.CorePair_Controller.S0.NB_AckS 1 0.00% 0.00%
system.ruby.CorePair_Controller.S0.L2_Repl 444 0.00% 0.00%
system.ruby.CorePair_Controller.S1.NB_AckS 1 0.00% 0.00%
system.ruby.CorePair_Controller.I_C.NB_AckWB 4 0.00% 0.00%
system.ruby.Directory_Controller.RdBlkS 4 0.00% 0.00%
system.ruby.Directory_Controller.RdBlkM 297 0.00% 0.00%
system.ruby.Directory_Controller.RdBlk 6 0.00% 0.00%
system.ruby.Directory_Controller.VicDirty 69 0.00% 0.00%
system.ruby.Directory_Controller.VicClean 2 0.00% 0.00%
system.ruby.Directory_Controller.CPUData 67 0.00% 0.00%
system.ruby.Directory_Controller.StaleWB 4 0.00% 0.00%
system.ruby.Directory_Controller.CPUPrbResp 298 0.00% 0.00%
system.ruby.Directory_Controller.ProbeAcksComplete 298 0.00% 0.00%
system.ruby.Directory_Controller.L3Hit 45 0.00% 0.00%
system.ruby.Directory_Controller.MemData 256 0.00% 0.00%
system.ruby.Directory_Controller.WBAck 14 0.00% 0.00%
system.ruby.Directory_Controller.CoreUnblock 295 0.00% 0.00%
system.ruby.Directory_Controller.U.RdBlkS 4 0.00% 0.00%
system.ruby.Directory_Controller.U.RdBlkM 291 0.00% 0.00%
system.ruby.Directory_Controller.U.RdBlk 6 0.00% 0.00%
system.ruby.Directory_Controller.U.VicDirty 69 0.00% 0.00%
system.ruby.Directory_Controller.U.VicClean 2 0.00% 0.00%
system.ruby.Directory_Controller.U.WBAck 14 0.00% 0.00%
system.ruby.Directory_Controller.BL.CPUData 67 0.00% 0.00%
system.ruby.Directory_Controller.BL.StaleWB 4 0.00% 0.00%
system.ruby.Directory_Controller.BM_M.MemData 9 0.00% 0.00%
system.ruby.Directory_Controller.BS_PM.L3Hit 1 0.00% 0.00%
system.ruby.Directory_Controller.BS_PM.MemData 3 0.00% 0.00%
system.ruby.Directory_Controller.BM_PM.RdBlkM 1 0.00% 0.00%
system.ruby.Directory_Controller.BM_PM.CPUPrbResp 13 0.00% 0.00%
system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 9 0.00% 0.00%
system.ruby.Directory_Controller.BM_PM.L3Hit 41 0.00% 0.00%
system.ruby.Directory_Controller.BM_PM.MemData 241 0.00% 0.00%
system.ruby.Directory_Controller.B_PM.L3Hit 3 0.00% 0.00%
system.ruby.Directory_Controller.B_PM.MemData 3 0.00% 0.00%
system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 3 0.00% 0.00%
system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 3 0.00% 0.00%
system.ruby.Directory_Controller.BM_Pm.RdBlkM 3 0.00% 0.00%
system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 277 0.00% 0.00%
system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 281 0.00% 0.00%
system.ruby.Directory_Controller.B_Pm.CPUPrbResp 5 0.00% 0.00%
system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% 0.00%
system.ruby.Directory_Controller.B.RdBlkM 2 0.00% 0.00%
system.ruby.Directory_Controller.B.CoreUnblock 295 0.00% 0.00%
system.ruby.LD.latency_hist_seqr::bucket_size 1024
system.ruby.LD.latency_hist_seqr::max_bucket 10239
system.ruby.LD.latency_hist_seqr::samples 1
system.ruby.LD.latency_hist_seqr::mean 5256
system.ruby.LD.latency_hist_seqr::gmean 5256.000000
system.ruby.LD.latency_hist_seqr::stdev nan
system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1
system.ruby.LD.latency_hist_coalsr::bucket_size 64
system.ruby.LD.latency_hist_coalsr::max_bucket 639
system.ruby.LD.latency_hist_coalsr::samples 72
system.ruby.LD.latency_hist_coalsr::mean 101.402778
system.ruby.LD.latency_hist_coalsr::gmean 68.071118
system.ruby.LD.latency_hist_coalsr::stdev 67.272969
system.ruby.LD.latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_coalsr::total 72
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1024
system.ruby.LD.hit_latency_hist_seqr::max_bucket 10239
system.ruby.LD.hit_latency_hist_seqr::samples 1
system.ruby.LD.hit_latency_hist_seqr::mean 5256
system.ruby.LD.hit_latency_hist_seqr::gmean 5256.000000
system.ruby.LD.hit_latency_hist_seqr::stdev nan
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 1
system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64
system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639
system.ruby.LD.miss_latency_hist_coalsr::samples 72
system.ruby.LD.miss_latency_hist_coalsr::mean 101.402778
system.ruby.LD.miss_latency_hist_coalsr::gmean 68.071118
system.ruby.LD.miss_latency_hist_coalsr::stdev 67.272969
system.ruby.LD.miss_latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_coalsr::total 72
system.ruby.ST.latency_hist_seqr::bucket_size 1024
system.ruby.ST.latency_hist_seqr::max_bucket 10239
system.ruby.ST.latency_hist_seqr::samples 46
system.ruby.ST.latency_hist_seqr::mean 3234.260870
system.ruby.ST.latency_hist_seqr::gmean 1760.149244
system.ruby.ST.latency_hist_seqr::stdev 1907.255858
system.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 20 43.48% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 46
system.ruby.ST.latency_hist_coalsr::bucket_size 128
system.ruby.ST.latency_hist_coalsr::max_bucket 1279
system.ruby.ST.latency_hist_coalsr::samples 786
system.ruby.ST.latency_hist_coalsr::mean 225.797710
system.ruby.ST.latency_hist_coalsr::gmean 112.544056
system.ruby.ST.latency_hist_coalsr::stdev 244.652456
system.ruby.ST.latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_coalsr::total 786
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1024
system.ruby.ST.hit_latency_hist_seqr::max_bucket 10239
system.ruby.ST.hit_latency_hist_seqr::samples 40
system.ruby.ST.hit_latency_hist_seqr::mean 3566.725000
system.ruby.ST.hit_latency_hist_seqr::gmean 2651.630943
system.ruby.ST.hit_latency_hist_seqr::stdev 1765.919997
system.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 40
system.ruby.ST.miss_latency_hist_seqr::bucket_size 512
system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119
system.ruby.ST.miss_latency_hist_seqr::samples 6
system.ruby.ST.miss_latency_hist_seqr::mean 1017.833333
system.ruby.ST.miss_latency_hist_seqr::gmean 114.584426
system.ruby.ST.miss_latency_hist_seqr::stdev 1278.753677
system.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 6
system.ruby.ST.miss_latency_hist_coalsr::bucket_size 128
system.ruby.ST.miss_latency_hist_coalsr::max_bucket 1279
system.ruby.ST.miss_latency_hist_coalsr::samples 786
system.ruby.ST.miss_latency_hist_coalsr::mean 225.797710
system.ruby.ST.miss_latency_hist_coalsr::gmean 112.544056
system.ruby.ST.miss_latency_hist_coalsr::stdev 244.652456
system.ruby.ST.miss_latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_coalsr::total 786
system.ruby.IFETCH.latency_hist_seqr::bucket_size 1024
system.ruby.IFETCH.latency_hist_seqr::max_bucket 10239
system.ruby.IFETCH.latency_hist_seqr::samples 1
system.ruby.IFETCH.latency_hist_seqr::mean 5129
system.ruby.IFETCH.latency_hist_seqr::gmean 5129
system.ruby.IFETCH.latency_hist_seqr::stdev nan
system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 1
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1024
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 10239
system.ruby.IFETCH.hit_latency_hist_seqr::samples 1
system.ruby.IFETCH.hit_latency_hist_seqr::mean 5129
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 5129
system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 1
system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512
system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119
system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 6
system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1017.833333
system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 114.584426
system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1278.753677
system.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 6
system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 1024
system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 10239
system.ruby.Directory.hit_mach_latency_hist_seqr::samples 42
system.ruby.Directory.hit_mach_latency_hist_seqr::mean 3644.142857
system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2737.850881
system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1757.652877
system.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.hit_mach_latency_hist_seqr::total 42
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 128
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 1279
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 624
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 148.483974
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 122.381501
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 128.958613
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 502 80.45% 80.45% | 36 5.77% 86.22% | 40 6.41% 92.63% | 24 3.85% 96.47% | 12 1.92% 98.40% | 6 0.96% 99.36% | 3 0.48% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 624
system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1
system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9
system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 71
system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.126761
system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.060325
system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.607796
system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 68 95.77% 95.77% | 0 0.00% 95.77% | 0 0.00% 95.77% | 3 4.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.TCP.miss_mach_latency_hist_coalsr::total 71
system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 128
system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 1279
system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 163
system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 564.687117
system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 498.870659
system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 272.472640
system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 71 43.56% 43.56% | 13 7.98% 51.53% | 12 7.36% 58.90% | 13 7.98% 66.87% | 29 17.79% 84.66% | 22 13.50% 98.16% | 3 1.84% 100.00% | 0 0.00% 100.00%
system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 163
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 1
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 5256
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5256.000000
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev nan
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 1
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 62
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 104.322581
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 100.218451
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 51.260433
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 60 96.77% 96.77% | 1 1.61% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 62
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 7
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 1.428571
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.219014
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.133893
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 6 85.71% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 7
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 3
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 274.333333
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273.844265
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 20.256686
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00%
system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 3
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 6
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1017.833333
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.584426
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1278.753677
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 6
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 40
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3566.725000
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2651.630943
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1765.919997
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 40
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 562
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 153.355872
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 125.108856
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 133.952348
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 442 78.65% 78.65% | 35 6.23% 84.88% | 40 7.12% 91.99% | 23 4.09% 96.09% | 12 2.14% 98.22% | 6 1.07% 99.29% | 3 0.53% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 562
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 64
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.093750
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.044274
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.526104
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 62 96.88% 96.88% | 0 0.00% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 64
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 128
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 1279
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 160
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 570.131250
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 504.512629
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 272.059675
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 42.50% 42.50% | 13 8.12% 50.62% | 12 7.50% 58.12% | 13 8.12% 66.25% | 29 18.12% 84.38% | 22 13.75% 98.12% | 3 1.88% 100.00% | 0 0.00% 100.00%
system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 160
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5129
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5129
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev nan
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1
system.ruby.SQC_Controller.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00%
system.ruby.SQC_Controller.Fetch::total 24
system.ruby.SQC_Controller.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00%
system.ruby.SQC_Controller.TCC_AckS::total 24
system.ruby.SQC_Controller.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00%
system.ruby.SQC_Controller.PrbInvData::total 22
system.ruby.SQC_Controller.I.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00%
system.ruby.SQC_Controller.I.Fetch::total 24
system.ruby.SQC_Controller.S.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00%
system.ruby.SQC_Controller.S.PrbInvData::total 22
system.ruby.SQC_Controller.I_S.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00%
system.ruby.SQC_Controller.I_S.TCC_AckS::total 24
system.ruby.TCCdir_Controller.RdBlk 115 0.00% 0.00%
system.ruby.TCCdir_Controller.RdBlkM 2448 0.00% 0.00%
system.ruby.TCCdir_Controller.RdBlkS 103 0.00% 0.00%
system.ruby.TCCdir_Controller.CPUPrbResp 785 0.00% 0.00%
system.ruby.TCCdir_Controller.ProbeAcksComplete 730 0.00% 0.00%
system.ruby.TCCdir_Controller.CoreUnblock 807 0.00% 0.00%
system.ruby.TCCdir_Controller.LastCoreUnblock 3 0.00% 0.00%
system.ruby.TCCdir_Controller.NB_AckS 1 0.00% 0.00%
system.ruby.TCCdir_Controller.NB_AckE 3 0.00% 0.00%
system.ruby.TCCdir_Controller.NB_AckM 212 0.00% 0.00%
system.ruby.TCCdir_Controller.PrbInvData 119 0.00% 0.00%
system.ruby.TCCdir_Controller.PrbShrData 6 0.00% 0.00%
system.ruby.TCCdir_Controller.I.RdBlk 3 0.00% 0.00%
system.ruby.TCCdir_Controller.I.RdBlkM 154 0.00% 0.00%
system.ruby.TCCdir_Controller.I.RdBlkS 1 0.00% 0.00%
system.ruby.TCCdir_Controller.I.PrbInvData 9 0.00% 0.00%
system.ruby.TCCdir_Controller.S.RdBlkM 1 0.00% 0.00%
system.ruby.TCCdir_Controller.E.RdBlkM 1 0.00% 0.00%
system.ruby.TCCdir_Controller.E.RdBlkS 1 0.00% 0.00%
system.ruby.TCCdir_Controller.O.RdBlk 2 0.00% 0.00%
system.ruby.TCCdir_Controller.O.RdBlkM 61 0.00% 0.00%
system.ruby.TCCdir_Controller.O.RdBlkS 1 0.00% 0.00%
system.ruby.TCCdir_Controller.O.PrbInvData 4 0.00% 0.00%
system.ruby.TCCdir_Controller.O.PrbShrData 1 0.00% 0.00%
system.ruby.TCCdir_Controller.M.RdBlk 61 0.00% 0.00%
system.ruby.TCCdir_Controller.M.RdBlkM 512 0.00% 0.00%
system.ruby.TCCdir_Controller.M.RdBlkS 20 0.00% 0.00%
system.ruby.TCCdir_Controller.M.PrbInvData 62 0.00% 0.00%
system.ruby.TCCdir_Controller.M.PrbShrData 4 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_I.RdBlkM 17 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 70 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 66 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_O.RdBlkM 4 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 6 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 5 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_OM.RdBlkM 14 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_OM.CPUPrbResp 1 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_OM.ProbeAcksComplete 1 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_IOM.RdBlkM 5 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp 2 0.00% 0.00%
system.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete 2 0.00% 0.00%
system.ruby.TCCdir_Controller.I_M.RdBlk 26 0.00% 0.00%
system.ruby.TCCdir_Controller.I_M.RdBlkM 960 0.00% 0.00%
system.ruby.TCCdir_Controller.I_M.RdBlkS 3 0.00% 0.00%
system.ruby.TCCdir_Controller.I_M.NB_AckM 154 0.00% 0.00%
system.ruby.TCCdir_Controller.I_M.PrbInvData 1 0.00% 0.00%
system.ruby.TCCdir_Controller.I_ES.NB_AckE 3 0.00% 0.00%
system.ruby.TCCdir_Controller.I_S.NB_AckS 1 0.00% 0.00%
system.ruby.TCCdir_Controller.BBO_O.RdBlkM 5 0.00% 0.00%
system.ruby.TCCdir_Controller.BBO_O.RdBlkS 1 0.00% 0.00%
system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp 3 0.00% 0.00%
system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete 3 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_M.RdBlk 6 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_M.RdBlkM 94 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_M.RdBlkS 5 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 510 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 510 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_M.PrbInvData 15 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_O.RdBlkM 6 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_O.RdBlkS 5 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp 81 0.00% 0.00%
system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete 81 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_M.RdBlk 13 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_M.RdBlkM 176 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_M.RdBlkS 5 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_M.CoreUnblock 509 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_M.PrbInvData 24 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_O.RdBlkM 26 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_O.RdBlkS 5 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_O.CoreUnblock 81 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_O.PrbInvData 2 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_OO.RdBlkM 14 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_OO.CoreUnblock 1 0.00% 0.00%
system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock 3 0.00% 0.00%
system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 2 0.00% 0.00%
system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 2 0.00% 0.00%
system.ruby.TCCdir_Controller.BBO_M.RdBlkM 4 0.00% 0.00%
system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 110 0.00% 0.00%
system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 60 0.00% 0.00%
system.ruby.TCCdir_Controller.S_M.NB_AckM 2 0.00% 0.00%
system.ruby.TCCdir_Controller.O_M.RdBlkM 198 0.00% 0.00%
system.ruby.TCCdir_Controller.O_M.RdBlkS 48 0.00% 0.00%
system.ruby.TCCdir_Controller.O_M.NB_AckM 56 0.00% 0.00%
system.ruby.TCCdir_Controller.O_M.PrbInvData 2 0.00% 0.00%
system.ruby.TCCdir_Controller.O_M.PrbShrData 1 0.00% 0.00%
system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 1 0.00% 0.00%
system.ruby.TCCdir_Controller.BBB_M.RdBlk 4 0.00% 0.00%
system.ruby.TCCdir_Controller.BBB_M.RdBlkM 196 0.00% 0.00%
system.ruby.TCCdir_Controller.BBB_M.RdBlkS 8 0.00% 0.00%
system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 212 0.00% 0.00%
system.ruby.TCCdir_Controller.BBB_E.CoreUnblock 3 0.00% 0.00%
system.ruby.TCP_Controller.Load | 10 13.70% 13.70% | 10 13.70% 27.40% | 11 15.07% 42.47% | 12 16.44% 58.90% | 6 8.22% 67.12% | 3 4.11% 71.23% | 10 13.70% 84.93% | 11 15.07% 100.00%
system.ruby.TCP_Controller.Load::total 73
system.ruby.TCP_Controller.Store | 106 13.27% 13.27% | 102 12.77% 26.03% | 97 12.14% 38.17% | 86 10.76% 48.94% | 107 13.39% 62.33% | 98 12.27% 74.59% | 111 13.89% 88.49% | 92 11.51% 100.00%
system.ruby.TCP_Controller.Store::total 799
system.ruby.TCP_Controller.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00%
system.ruby.TCP_Controller.TCC_AckS::total 62
system.ruby.TCP_Controller.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.TCC_AckE::total 3
system.ruby.TCP_Controller.TCC_AckM | 93 12.88% 12.88% | 89 12.33% 25.21% | 87 12.05% 37.26% | 76 10.53% 47.78% | 98 13.57% 61.36% | 89 12.33% 73.68% | 106 14.68% 88.37% | 84 11.63% 100.00%
system.ruby.TCP_Controller.TCC_AckM::total 722
system.ruby.TCP_Controller.PrbInvData | 84 12.44% 12.44% | 87 12.89% 25.33% | 83 12.30% 37.63% | 78 11.56% 49.19% | 89 13.19% 62.37% | 79 11.70% 74.07% | 97 14.37% 88.44% | 78 11.56% 100.00%
system.ruby.TCP_Controller.PrbInvData::total 675
system.ruby.TCP_Controller.PrbShrData | 16 17.39% 17.39% | 10 10.87% 28.26% | 9 9.78% 38.04% | 8 8.70% 46.74% | 15 16.30% 63.04% | 9 9.78% 72.83% | 14 15.22% 88.04% | 11 11.96% 100.00%
system.ruby.TCP_Controller.PrbShrData::total 92
system.ruby.TCP_Controller.I.Load | 10 15.15% 15.15% | 9 13.64% 28.79% | 9 13.64% 42.42% | 12 18.18% 60.61% | 5 7.58% 68.18% | 3 4.55% 72.73% | 9 13.64% 86.36% | 9 13.64% 100.00%
system.ruby.TCP_Controller.I.Load::total 66
system.ruby.TCP_Controller.I.Store | 97 13.42% 13.42% | 91 12.59% 26.00% | 87 12.03% 38.04% | 79 10.93% 48.96% | 92 12.72% 61.69% | 89 12.31% 74.00% | 104 14.38% 88.38% | 84 11.62% 100.00%
system.ruby.TCP_Controller.I.Store::total 723
system.ruby.TCP_Controller.I.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.I.PrbInvData::total 2
system.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.S.Store::total 3
system.ruby.TCP_Controller.S.PrbInvData | 6 14.29% 14.29% | 7 16.67% 30.95% | 7 16.67% 47.62% | 7 16.67% 64.29% | 2 4.76% 69.05% | 1 2.38% 71.43% | 5 11.90% 83.33% | 7 16.67% 100.00%
system.ruby.TCP_Controller.S.PrbInvData::total 42
system.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.S.PrbShrData::total 1
system.ruby.TCP_Controller.E.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.E.PrbInvData::total 1
system.ruby.TCP_Controller.E.PrbShrData | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.E.PrbShrData::total 1
system.ruby.TCP_Controller.O.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 11.11% 11.11% | 0 0.00% 11.11% | 5 55.56% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00%
system.ruby.TCP_Controller.O.Store::total 9
system.ruby.TCP_Controller.O.PrbInvData | 9 16.07% 16.07% | 7 12.50% 28.57% | 8 14.29% 42.86% | 8 14.29% 57.14% | 7 12.50% 69.64% | 3 5.36% 75.00% | 9 16.07% 91.07% | 5 8.93% 100.00%
system.ruby.TCP_Controller.O.PrbInvData::total 56
system.ruby.TCP_Controller.O.PrbShrData | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
system.ruby.TCP_Controller.O.PrbShrData::total 3
system.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 14.29% 14.29% | 2 28.57% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00%
system.ruby.TCP_Controller.M.Load::total 7
system.ruby.TCP_Controller.M.Store | 9 14.06% 14.06% | 11 17.19% 31.25% | 9 14.06% 45.31% | 7 10.94% 56.25% | 9 14.06% 70.31% | 8 12.50% 82.81% | 4 6.25% 89.06% | 7 10.94% 100.00%
system.ruby.TCP_Controller.M.Store::total 64
system.ruby.TCP_Controller.M.PrbInvData | 69 12.02% 12.02% | 73 12.72% 24.74% | 68 11.85% 36.59% | 62 10.80% 47.39% | 79 13.76% 61.15% | 75 13.07% 74.22% | 82 14.29% 88.50% | 66 11.50% 100.00%
system.ruby.TCP_Controller.M.PrbInvData::total 574
system.ruby.TCP_Controller.M.PrbShrData | 14 16.47% 16.47% | 10 11.76% 28.24% | 9 10.59% 38.82% | 8 9.41% 48.24% | 14 16.47% 64.71% | 6 7.06% 71.76% | 14 16.47% 88.24% | 10 11.76% 100.00%
system.ruby.TCP_Controller.M.PrbShrData::total 85
system.ruby.TCP_Controller.I_M.TCC_AckM | 93 13.06% 13.06% | 89 12.50% 25.56% | 86 12.08% 37.64% | 76 10.67% 48.31% | 92 12.92% 61.24% | 89 12.50% 73.74% | 104 14.61% 88.34% | 83 11.66% 100.00%
system.ruby.TCP_Controller.I_M.TCC_AckM::total 712
system.ruby.TCP_Controller.I_ES.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00%
system.ruby.TCP_Controller.I_ES.TCC_AckS::total 62
system.ruby.TCP_Controller.I_ES.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.I_ES.TCC_AckE::total 3
system.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.S_M.TCC_AckM::total 2
system.ruby.TCP_Controller.O_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 12.50% 12.50% | 0 0.00% 12.50% | 5 62.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00%
system.ruby.TCP_Controller.O_M.TCC_AckM::total 8
system.ruby.TCP_Controller.O_M.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.TCP_Controller.O_M.PrbShrData::total 2
---------- End Simulation Statistics ----------
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