New MMU reference manuals, and updates to other manuals

1. Added 5 new MMU reference manuals:

	dev_mmu_fault.ref.txt
	pri_mmu_both.ref.txt
	pri_mmu_gpc.ref.txt
	pri_mmu_hshub.ref.txt
	pri_mmu_hub.ref.txt

2. Renamed dev_display.ref.txt --> dev_display_withoffset.ref.txt .

3. Updates and a few documentation additions and clarifications to these
manuals:

	dev_bus.ref.txt
	dev_fifo.ref.txt
	dev_master.ref.txt
	dev_pbdma.ref.txt
	dev_ram.ref.txt
	dev_timer.ref.txt
	dev_usermode.ref.txt

Reviewed by:

14 files changed, 1913 insertions, 47 deletions

diff --git a/manuals/volta/gv100/dev_bus.ref.txt b/manuals/volta/gv100/dev_bus.ref.txt
index 488e265..48a82c2 100644
--- a/manuals/volta/gv100/dev_bus.ref.txt
+++ b/manuals/volta/gv100/dev_bus.ref.txt
@@ -19,6 +19,17 @@ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 DEALINGS IN THE SOFTWARE.
 --------------------------------------------------------------------------------
 
+#define NV_MEMORY                             0xFFFFFFFF:0x00000000 /* RW--D */
+#define NV_IO                                 0xFFFFFFFF:0x00000000 /* RW--D */
+#define NV_EXPROM                             0x0007FFFF:0x00000000 /* R---D */
+#define NV_SPACE                              0x01FFFFFF:0x00000000 /* RW--D */
+#define NV_RSPACE                             0x00FFFFFF:0x00000000 /* RW--D */
+#define NV_MSPACE                             0x1FFFFFFF:0x00000000 /* RW--D */
+#define NV_ISPACE                             0x01FFFFFF:0x00000000 /* RW--D */
+#define NV_IOBAR                              0x0000007F:0x00000000 /* RW--D */
+#define NV_IFB                                0x00060FFF:0x00060000 /* RW--D */
+#define NV_PRMIO                              0x00007FFF:0x00007000 /* RW--D */
+#define NV_PBUS                               0x00001FFF:0x00001000 /* RW--D */
 #define NV_PBUS_SW_SCRATCH(i)                     (0x00001580+(i)*4) /* RW-4A */
 #define NV_PBUS_SW_SCRATCH__SIZE_1                                32 /*       */
 #define NV_PBUS_SW_SCRATCH_FIELD                                31:0 /* RWIVF */
@@ -314,3 +325,79 @@ DEALINGS IN THE SOFTWARE.
 #define NV_PBUS_LVDS_USER                                 0x00001800 /* RW-4R */
 #define NV_PBUS_LVDS_USER_VALUE                                  3:0 /* RWIVF */
 #define NV_PBUS_LVDS_USER_VALUE_INIT                      0x0000000F /* RWI-V */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_display.ref.txt b/manuals/volta/gv100/dev_display_withoffset.ref.txt
index e287338..1fa8ad5 100644
--- a/manuals/volta/gv100/dev_display.ref.txt
+++ b/manuals/volta/gv100/dev_display_withoffset.ref.txt
@@ -1,18 +1,18 @@
-Copyright (c) 2018 NVIDIA Corporation
+Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
 
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to
-deal in the Software without restriction, including without limitation the
-rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-sell copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
 
-The above copyright notice and this permission notice shall be
-included in all copies or substantial portions of the Software.
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
 
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
@@ -3943,9 +3943,9 @@ DEALINGS IN THE SOFTWARE.
 #define NV_DMA_ADDRESS_BASE_HI                                         (2*32+6):(2*32+0) /* RWXUF */
 #define NV_DMA_ADDRESS_LIMIT_LO                                       (3*32+31):(3*32+0) /* RWXUF */
 #define NV_DMA_ADDRESS_LIMIT_HI                                        (4*32+6):(4*32+0) /* RWXUF */
-#define NV_DMA__SIZE                                                                  20 /*       */
-#define NV_DMA__ALIGN                                                                 32 /*       */
-#define NV_DMA__ADDRESS_BASE_SHIFT                                                     8 /*       */
+#define NV_DMA_SIZE                                                                   20 /*       */
+#define NV_DMA_ALIGN                                                                  32 /*       */
+#define NV_DMA_ADDRESS_BASE_SHIFT                                                      8 /*       */
 #define NV_PDISP_IHUB_COMMON_CAPA                                               0x0062E000 /* R--4R */
 #define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES                                     15:0 /* R--UF */
 #define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH                                17:16 /* R--VF */
@@ -6026,3 +6026,79 @@ DEALINGS IN THE SOFTWARE.
 #define NV_UDISP_DMA_DATA_NOP                                                 0x00000000 /* RW--V */
 #define NV_UDISP_DMA_JUMP_OFFSET                                                    11:2 /* RWXUF */
 #define NV_UDISP_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 /* RWXUF */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_fifo.ref.txt b/manuals/volta/gv100/dev_fifo.ref.txt
index dcb055e..8b590cb 100644
--- a/manuals/volta/gv100/dev_fifo.ref.txt
+++ b/manuals/volta/gv100/dev_fifo.ref.txt
@@ -19,6 +19,8 @@ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 DEALINGS IN THE SOFTWARE.
 --------------------------------------------------------------------------------
 
+#define NV_PFIFO                              0x00003FFF:0x00002000 /* RW--D */
+#define NV_PCCSR                              0x0080FFFF:0x00800000 /* RW--D */
 #define NV_PFIFO_CFG0                                 0x00002004 /* R--4R */
 #define NV_PFIFO_CFG0_NUM_PBDMA                              7:0 /* R-IUF */
 #define NV_PFIFO_CFG0_NUM_PBDMA_INIT                           14 /* R-I-V */
@@ -637,3 +639,79 @@ DEALINGS IN THE SOFTWARE.
 #define NV_PFIFO_PBDMA_STATUS_INST_VALID                           31:31 /* R-EVF */
 #define NV_PFIFO_PBDMA_STATUS_INST_VALID_FALSE                0x00000000 /* R-E-V */
 #define NV_PFIFO_PBDMA_STATUS_INST_VALID_TRUE                 0x00000001 /* R---V */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_master.ref.txt b/manuals/volta/gv100/dev_master.ref.txt
index 8ae6133..5a86398 100644
--- a/manuals/volta/gv100/dev_master.ref.txt
+++ b/manuals/volta/gv100/dev_master.ref.txt
@@ -19,6 +19,7 @@ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 DEALINGS IN THE SOFTWARE.
 --------------------------------------------------------------------------------
 
+#define NV_PMC                                0x00000FFF:0x00000000 /* RW--D */
 #define NV_PMC_BOOT_0                                    0x00000000 /* R--4R */
 #define NV_PMC_BOOT_0_ID                                       31:0 /*       */
 #define NV_PMC_BOOT_0_MINOR_REVISION                            3:0 /* R--VF */
@@ -361,3 +362,79 @@ DEALINGS IN THE SOFTWARE.
 #define NV_PMC_ENABLE_PB_13_ENABLED                      0x00000001 /* RWI-V */
 #define NV_PMC_ENABLE_PB_SEL(i)                             (i):(i) /*       */
 #define NV_PMC_ENABLE_PB_SEL__SIZE_1              14 /*       */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_mmu_fault.ref.txt b/manuals/volta/gv100/dev_mmu_fault.ref.txt
new file mode 100644
index 0000000..e4e62db
--- /dev/null
+++ b/manuals/volta/gv100/dev_mmu_fault.ref.txt
@@ -0,0 +1,269 @@
+Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+
+1  -  INTRODUCTION
+==================
+
+This manual contains information definition of replayable (UVM)
+and non-replayable fault buffer packet in memory. Both type of faults
+use same packet format in memory although separate fault buffers are
+used.
+
+The goal of the UVM feature is to have a single unified virtual memory space
+for both GPU and CPU memory accesses.  In addition to the unified address
+space, UVM allows the GPU driver to support demand paging, and seamlessly
+migrate pages from GPU RAM to the primary system memory.
+
+This is done by allowing page faults to be stalling and support replay, and by
+reporting page faults to the operating system or GPU driver in an efficient
+manner.
+
+Non-replayable faults are various mapping and permission related
+faults and are usually fatal.
+
+
+
+2  -  GPU FAULT BUFFER
+======================================
+This chapter describes the format of the GPU replayable and
+non-replayable fault reporting buffer used to report page faults.
+
+
+This fault buffer is written to by GMMU based on buffer location info
+set in GMMU registers (NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER_LO/HI and
+NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER_LO/HI). The replayable fault
+buffer is managed by the UVM driver. The non-replayable fault buffer
+is managed by RM.
+
+
+The size of the fault buffer is controlled by SIZE register in GMMU
+which can be programmed by SW. If SW does not want to program the SIZE
+(because SW does not know/have enough info) then SW can write a SIZE
+CTL bit (SET_DEFAULT) in GMMU register to set the size to a HW
+recommended value. On that SIZE CTL bit write, GMMU will calculate the
+recommended value based on chip size and so and write the recommended
+value.
+
+
+The buffer can overflow. There is status maintained in GMMU register
+for that. If the buffer has overflowed the GPU will stop writing out new fault
+entries and proceed to drop entries until SW resets the overflow
+status (normally after processing the existing fault packets and so
+GET PTR is changed). This is done to prevent the GPU from overwriting
+unprocessed entries.  When faults are dropped they are not lost for
+replayable faults as the requets are buffered in MMU replay buffer;
+however, non-replayable faults are lost as those requests are not
+buffered for further processing; when SW triggers a replay event the
+requests for the dropped replayable faults will be replayed, fault
+again, and then be reported in the fault buffer.
+
+Each entry is of size NV_MMU_FAULT_BUFFER_PACKET_SIZE (=32) bytes and
+contains the fault information necessary for (1) the UVM driver to
+perform necessary page migrations and house keeping in response to a
+replayable fault for replayable fault and (2) the RM to perform
+graceful exit for the non-replayable fault.
+
+The ENGINE_ID field specifies the faulting MMU engine id.
+
+The APERTURE field specifies the GPU physical APERTURE of the instance block
+used for the request.  VID_MEM indicates the instance block was stored in the
+GPU devices RAM.  SYS_MEM_COHERENT indicates the instance block was stored in
+coherent system memory. SYS_MEM_NONCOHERENT indicates the page table was stored
+in non-coherent system memory.
+
+
+INST_LO is used to specify bits 32:12 of the physical 4KB aligned instance
+block associated with the faulting request.  INST_LO is aligned to this 4KB
+boundary and so the bottom 12 bits are not reported in this data structure, and
+this space is used to specify other fields.  The instance block contains the
+pointers to the page table used for the memory request.
+
+
+
+
+INST_HI contains the high order bits of the instance block associated with the
+memory request.  Space is reserved to allow INST_HI to eventually expand up to
+64 bits.
+
+ADDR_LO and ADDR_HI specify the 4K-aligned address (virtual or
+physical based on ACCESS_TYPE) of the faulting request. Up to 64 bits
+4K-aligned address can be reported; however,the bit width of the
+addresses supported by a given GPU depends on the GPU's family.
+
+PHYS_APERTURE specifies the aperture of the faulting address.
+
+
+FAULT_TYPE indicates the type of fault which occurred.  For a list of different
+fault types please see the NV_PFAULT_FAULT_TYPE_* defines in dev_fault.ref.
+
+REPLAYABLE_FAULT(RF) indicates whether this fault is a replayable fault or
+not. This bit is set false when (1) the fault is non-replayable or (2)
+fault is replayable but has been cancelled.
+
+CLIENT indicates which MMU client generated the faulting request.
+
+The ACCESS_TYPE field indicates the type of the faulting request.
+
+MMU_CLIENT_TYPE indicates whether the faulting request originated in a GPC, or
+if it came from another type of HUB client.  This field determines how the
+CLIENT field should be interpreted.
+
+
+GPC_ID specifies the GPC which generated the faulting request if MMU_CLIENT_TYPE
+will be NV_PFAULT_MMU_CLIENT_TYPE_GPC, meaning the request came from a GPC
+client.  Otherwise the GPC_ID field should be ignored.
+
+
+REPLAYABLE_FAULT_EN (R) is set to true if replayable fault is enabled for
+any client in the instance block.  It does not indicate whether the fault is replayable.
+
+VALID (V) indicates that this current buffer entry is VALID.
+
+#define NV_MMU_FAULT_BUF                                                    /* ----G */
+#define NV_MMU_FAULT_BUF_ENTRY                              0x1F:0x00000000 /* RW--M */
+
+Size of a buffer entry in bytes
+#define NV_MMU_FAULT_BUF_SIZE              32 /*       */
+
+#define NV_MMU_FAULT_BUF_ENTRY_INST_APERTURE              (9+0*32):(0*32+8) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_INST_APERTURE_VID_MEM             0x00000000 /* RW--V */
+#define NV_MMU_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT    0x00000002 /* RW--V */
+#define NV_MMU_FAULT_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
+
+#define NV_MMU_FAULT_BUF_ENTRY_INST_LO                   (31+0*32):(0*32+12) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_INST_HI                   (31+1*32):(1*32+0) /* RWXVF */
+Dword-spanning field define alias
+#define NV_MMU_FAULT_BUF_ENTRY_INST                      (31+1*32):(0*32+12) /*       */
+
+#define NV_MMU_FAULT_BUF_ENTRY_ADDR_PHYS_APERTURE         (1+2*32):(2*32+0) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_ADDR_LO                   (31+2*32):(2*32+12) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_ADDR_HI                   (31+3*32):(3*32+0) /* RWXVF */
+Dword-spanning field define alias
+#define NV_MMU_FAULT_BUF_ENTRY_ADDR                      (31+3*32):(2*32+12) /*       */
+
+#define NV_MMU_FAULT_BUF_ENTRY_TIMESTAMP_LO              (31+4*32):(4*32+0) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_TIMESTAMP_HI              (31+5*32):(5*32+0) /* RWXVF */
+Dword-spanning field define alias
+#define NV_MMU_FAULT_BUF_ENTRY_TIMESTAMP                 (31+5*32):(4*32+0) /*       */
+
+#define NV_MMU_FAULT_BUF_ENTRY_ENGINE_ID                  (8+6*32):(6*32+0) /* RWXVF */
+
+#define NV_MMU_FAULT_BUF_ENTRY_FAULT_TYPE                 (4+7*32):(7*32+0) /* RWXVF */
+
+#define NV_MMU_FAULT_BUF_ENTRY_REPLAYABLE_FAULT           (7+7*32):(7*32+7) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_REPLAYABLE_FAULT_FALSE            0x00000000 /* RWX-V */
+#define NV_MMU_FAULT_BUF_ENTRY_REPLAYABLE_FAULT_TRUE             0x00000001 /* RWX-V */
+
+#define NV_MMU_FAULT_BUF_ENTRY_CLIENT                    (14+7*32):(7*32+8) /* RWXVF */
+
+#define NV_MMU_FAULT_BUF_ENTRY_ACCESS_TYPE              (19+7*32):(7*32+16) /* RWXVF */
+
+#define NV_MMU_FAULT_BUF_ENTRY_MMU_CLIENT_TYPE          (20+7*32):(7*32+20) /* RWXVF */
+
+#define NV_MMU_FAULT_BUF_ENTRY_GPC_ID                   (28+7*32):(7*32+24) /* RWXVF */
+
+
+#define NV_MMU_FAULT_BUF_ENTRY_REPLAYABLE_FAULT_EN      (30+7*32):(7*32+30) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_REPLAYABLE_FAULT_EN_FALSE         0x00000000 /* RWX-V */
+#define NV_MMU_FAULT_BUF_ENTRY_REPLAYABLE_FAULT_EN_TRUE          0x00000001 /* RWX-V */
+
+// NOTE: VALID must be in the last byte in the packet for proper write ordering
+#define NV_MMU_FAULT_BUF_ENTRY_VALID                    (31+7*32):(7*32+31) /* RWXVF */
+#define NV_MMU_FAULT_BUF_ENTRY_VALID_FALSE                       0x00000000 /* RWX-V */
+#define NV_MMU_FAULT_BUF_ENTRY_VALID_TRUE                        0x00000001 /* RWX-V */
+
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_pbdma.ref.txt b/manuals/volta/gv100/dev_pbdma.ref.txt
index bc5163a..b9eaf43 100644
--- a/manuals/volta/gv100/dev_pbdma.ref.txt
+++ b/manuals/volta/gv100/dev_pbdma.ref.txt
@@ -19,7 +19,17 @@ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 DEALINGS IN THE SOFTWARE.
 --------------------------------------------------------------------------------
 
-1  -  INTRODUCTION
+CONTENTS
+
+    INTRODUCTION
+
+    INTERRUPT REGISTERS
+
+    HOST METHODS (NV_UDMA)
+
+    KEY
+
+INTRODUCTION
 ==================
 
      A Host's PBDMA unit fetches pushbuffer data from memory, generates
@@ -33,6 +43,22 @@ registers.
 address doubleword and a data doubleword.  The address specifies the operation
 to be performed.  The data is an operand.  The NV_UDMA address space contains
 the addresses of the methods that are executed by a PBDMA unit.
+
+Mnemonic  Description             Size    Interface
+--------  -----------             ----    ---------
+UDMA      Host Methods            256B
+PPBDMA    Priv PBDMA Unit         128K    HOST
+
+
+#define NV_UDMA                               0x000000FF:0x00000000 /* RW--D */
+#define NV_PPBDMA                             0x0005FFFF:0x00040000 /* RW--D */
+
+Note: As most of these registers directly reflect the current state of the PBDMA
+this means that while a Host channel switch is in progress the registers may be
+in an inconsistent state until the channel switch is complete. See dev_fifo.ref
+NV_PFIFO_PBDMA_STATUS for more information on how to tell if a chsw is in progress.
+
+
 GP_ENTRY0 and GP_ENTRY1 - GP-Entry Memory Format
 
      A pushbuffer contains the specifications of the operations that a GPU
@@ -1776,18 +1802,40 @@ NV_PPBDMA_CHANNEL_VALID is FALSE, this register should be ignored.
 
 
 
-CHANNEL - Channel Identifier
+CHANNEL register:
+
+     This register contains the channel ID of the channel currently loaded on
+the PBDMA.  If the PBDMA has been preempted and no channel is loaded or loading,
+the register contains information about the previously loaded channel.
 
-     The NV_PPBDMA_CHANNEL register contains the channel number that is
-currently assigned to a PBDMA unit. If VALID_FALSE, then this PBDMA unit
-does not contain any valid state. After loading state from RAMFC, VALID
-is set to TRUE. After saving the state to RAMFC, or during the load of RAMFC,
-VALID is set to FALSE.
-     This information is maintained by Hardware.  This register is available for
-debug purposes.
-     One of these registers exists for each of Host's PBDMA units.  This
-register is not context switched.  This register runs on the internal-domain
-clock.
+
+CHID field:
+
+     CHID contains the system channel ID of the channel currently loaded on the
+PBDMA, or the channel last loaded on the PBDMA during a channel save.  The chid
+gets populated with the ID of the loading channel during a channel switch as
+soon as the RAMFC load completes.  Note Host does not wait for the channel's
+bind acks to return.
+
+     The update of the chid field corresponds with the NV_PFIFO_PBDMA_STATUS
+register's CHAN_STATUS field as follows:
+
+  * CHAN_STATUS==VALID: CHID contains the current channel loaded on PBDMA
+  * CHAN_STATUS==INVALID or CHSW_SAVE: CHID specifies the channel that was last
+    loaded on the PBDMA if any.  If no channel has been loaded on the PBDMA, the
+    value is unspecified.
+  * CHAN_STATUS==CHSW_LOAD or CHSW_SWITCH: prior to completing the RAMFC load,
+    CHID contains the prior channel loaded if any.  After the RAMFC load
+    completes, CHID transitions to the ID of the loading channel.
+
+     The CHID field identifies the RAMFC that is currently accessible via the
+NV_PPBDMA registers.  However, note that the RAMFC requires multiple cycles to
+read, so it is possible that the PBDMA register state is not consistent during
+channel load.
+
+     This register is maintained by Hardware and is available for debug
+purposes.  One of these registers exists for each of Host's PBDMA units.  This
+register is not context switched.
 
 
 #define NV_PPBDMA_CHANNEL(i)                  (0x00040120+(i)*8192) /* RW-4A */
@@ -1795,9 +1843,6 @@ clock.
 
 #define NV_PPBDMA_CHANNEL_CHID                                 11:0 /*       */
 #define NV_PPBDMA_CHANNEL_CHID_HW                11:0 /* RWXUF */
-#define NV_PPBDMA_CHANNEL_VALID                               13:13 /* RWIVF */
-#define NV_PPBDMA_CHANNEL_VALID_FALSE                    0x00000000 /* RWI-V */
-#define NV_PPBDMA_CHANNEL_VALID_TRUE                     0x00000001 /* RW--V */
 
 
 
@@ -2057,6 +2102,7 @@ register runs on Host's internal domain clock.
 #define NV_PPBDMA_SET_CHANNEL_INFO_VEID     ((6-1)+8):8 /*       */
 
 #define NV_PPBDMA_SET_CHANNEL_INFO_RESERVED                        31:16 /*       */
+
 HCI_CTRL - Misc Additional HCE State
 
      HCE_CTRL is used for misc. HCE state that needs to be channel swapped
@@ -2114,6 +2160,7 @@ is useful for debug while the channel is loaded.
 #define NV_PPBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD           20:20 /* RW-UF */
 #define NV_PPBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD_NO   0x00000000 /* RW--V */
 #define NV_PPBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD_YES  0x00000001 /* RW--V */
+
 TIMEOUT - Timeout Period Register
 
      The NV_PPBDMA_TIMEOUT register contains a value used for detecting
@@ -2139,7 +2186,7 @@ clock.
 #define NV_PPBDMA_TIMEOUT_PERIOD_INIT                    0x00010000 /* RWE-V */
 #define NV_PPBDMA_TIMEOUT_PERIOD_MAX                     0xffffffff /* RW--V */
 
-6  -  INTERRUPT REGISTERS
+INTERRUPT REGISTERS
 =========================
 
      The interrupt registers control the interrupts for the local devices.
@@ -2504,13 +2551,10 @@ the interrupt will be fired.  This is a potentially fatal condition for the
 channel which was loaded on the PBDMA while the engine was reset.  The PBDMA which
 encountered the interrupt will stall and prevent the channel which was loaded at
 the time the interrupt fired from being swapped out until the interrupt is cleared.
-To unblock the PBDMA, SW needs to do the following:
-
-     1. Disable all the channels in the TSG
-     2. Initiate a preempt (but do not poll for completion yet)
-     3. Clear the interrupt bit
-     4. Poll for preempt completion
-     5. Tear down the context
+To unblock the PBDMA, SW needs to enable the engine and then tear down the
+context using the procedure described in Chapter "Channel Teardown Sequence" of
+dev_fifo.ref. This interrupt needs to be cleared as part of step 4 of the
+"Channel Teardown Sequence".
 
 Note the TSG ID can be obtained by reading NV_PFIFO_PBDMA_STATUS_ID;
 see dev_fifo.ref.  The error is limited to the channel.
@@ -3097,7 +3141,7 @@ pending and the PBDMA_STALL_1 register is set for the corresponding interrupt.
 #define NV_PPBDMA_HCE_DBG1_MTHD_DATA_VAL0                 0x00000000 /* R-E-V */
 
 
-9  -  HOST METHODS (NV_UDMA)
+HOST METHODS (NV_UDMA)
 ============================
 
      This section describes the types of methods that are executed by Host.  In
@@ -4259,3 +4303,82 @@ the CLEAR_FAULTED method times out or succeeds.
      Addresses that are not defined in this device are reserved.  Those below
 0x100 are reserved for future Host methods.  Addresses 0x100 and beyond are
 reserved for the engines served by Host.
+
+KEY
+================================
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_ram.ref.txt b/manuals/volta/gv100/dev_ram.ref.txt
index e80d9c0..3713180 100644
--- a/manuals/volta/gv100/dev_ram.ref.txt
+++ b/manuals/volta/gv100/dev_ram.ref.txt
@@ -19,7 +19,39 @@ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 DEALINGS IN THE SOFTWARE.
 --------------------------------------------------------------------------------
 
-2  -  GPU INSTANCE RAM (RAMIN)
+CONTENTS
+
+    Introduction
+
+    GPU Instance RAM (RAMIN)
+
+    FIFO Context RAM (RAMFC)
+
+    User-Driver Accessible RAM (RAMUSERD)
+
+    Run-List RAM (RAMRL)
+
+    Host Pushbuffer Format (FIFO_DMA)
+
+    Key
+
+INTRODUCTION
+==================
+
+     This device describes the various memory formats used by Host and the
+engines on the GPU.  It also defines the PRAMIN bar0 space controlled by
+NV_PBUS_BAR0_WINDOW.
+
+Mnemonc Description             Size    Interface
+------- -----------             ----    ---------
+PRAMIN  Priv Ram BAR0 Window      1M    HOST
+
+#define NV_PRAMIN                             0x007FFFFF:0x00700000 /* RW--M */
+
+
+
+
+GPU INSTANCE RAM (RAMIN)
 ==============================
 
      A GPU contains a block called "XVE" that manages the interface with PCI, a
@@ -342,7 +374,7 @@ is a virtual address.
 
 
 
-3  -  FIFO CONTEXT RAM (RAMFC)
+FIFO CONTEXT RAM (RAMFC)
 ==============================
 
 
@@ -470,7 +502,7 @@ corresponding register in the associated PBDMA unit's PRI space.
     Size of the full range of RAMFC in bytes.
 #define NV_RAMFC_SIZE_VAL                                0x00000200 /* ----C */
 
-4 - USER-DRIVER ACCESSIBLE RAM (RAMUSERD)
+USER-DRIVER ACCESSIBLE RAM (RAMUSERD)
 =========================================
 
      A user-level driver is allowed to access only a small portion of a GPU
@@ -548,7 +580,7 @@ unit.
 
 
 
-5 - RUN-LIST RAM (RAMRL)
+RUN-LIST RAM (RAMRL)
 ========================
 
      Software specifies the GPU contexts that hardware should "run" by writing a
@@ -779,7 +811,7 @@ number of regular channel entry, correspond to the second TSG.
 
 
 
-6  -  Host Pushbuffer Format (FIFO_DMA)
+Host Pushbuffer Format (FIFO_DMA)
 =======================================
 
      "FIFO" refers to Host.  "FIFO_DMA" means data that Host reads from memory:
@@ -1267,3 +1299,81 @@ segment via NV_PPBDMA_GP_ENTRY1_OPCODE_PB_CRC will be indeterminate.
 #define NV_FIFO_DMA_ENDSEG_OPCODE_VALUE                  0x00000007 /* ----V */
 
 
+KEY
+==================
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_timer.ref.txt b/manuals/volta/gv100/dev_timer.ref.txt
index 3f56b3b..4e5f26f 100644
--- a/manuals/volta/gv100/dev_timer.ref.txt
+++ b/manuals/volta/gv100/dev_timer.ref.txt
@@ -19,6 +19,7 @@ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 DEALINGS IN THE SOFTWARE.
 --------------------------------------------------------------------------------
 
+#define NV_PTIMER                             0x00009FFF:0x00009000 /* RW--D */
 #define NV_PTIMER_PRI_TIMEOUT                            0x00009080 /* RW-4R */
 #define NV_PTIMER_PRI_TIMEOUT_PERIOD                           23:0 /* RWIVF */
 #define NV_PTIMER_PRI_TIMEOUT_PERIOD_MIN                 0x00000003 /* RW--V */
@@ -77,3 +78,79 @@ DEALINGS IN THE SOFTWARE.
 #define NV_PTIMER_TIMER_0_NSEC                                 31:0 /*       */
 #define NV_PTIMER_TIMER_0_USEC                                31:10 /* RWIUF */
 #define NV_PTIMER_TIMER_0_USEC_INIT                             0x0 /* RWI-V */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/dev_usermode.ref.txt b/manuals/volta/gv100/dev_usermode.ref.txt
index cb98f96..b0a00c9 100644
--- a/manuals/volta/gv100/dev_usermode.ref.txt
+++ b/manuals/volta/gv100/dev_usermode.ref.txt
@@ -19,6 +19,23 @@ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 DEALINGS IN THE SOFTWARE.
 --------------------------------------------------------------------------------
 
+CONTENTS
+
+    Introduction
+
+    Identification and Capabilities Registers
+
+    PTIMER Current Time Registers
+
+    Channel Work Submission Registers
+
+    Key
+
+INTRODUCTION
+===============================================================================
+
+
+
      This manual describes the USERMODE device.  USERMODE is a mappable range of
 registers for use by usermode drivers.  The range is 64KB aligned and 64KB in
 size to match the maximum page size of systems supported by NVIDIA hardware.
@@ -34,11 +51,10 @@ USERMODE Usermode region         64K    HOST
 
 #define NV_USERMODE                           0x0081FFFF:0x00810000 /* RW--D */
 
-                        Table 1-1  Local Devices
 
 
 
-2  -  IDENTIFICATION AND CAPABILITIES REGISTERS
+IDENTIFICATION AND CAPABILITIES REGISTERS
 ===============================================================================
 
      The first 128 bytes of the NV_USERMODE device are reserved for up to 32
@@ -59,7 +75,7 @@ volta_usermode_a.
 // Note: addresses up to 0x810080 are reserved for CGF and capabilities registers
 
 
-3  -  PTIMER CURRENT TIME REGISTERS
+PTIMER CURRENT TIME REGISTERS
 ===============================================================================
 
      The TIME registers contain the current time as kept by the PTIMER; see
@@ -98,7 +114,7 @@ TIME_1 Register - Timer High Bits
 
 
 
-4  -  CHANNEL WORK SUBMISSION REGISTERS
+CHANNEL WORK SUBMISSION REGISTERS
 ===============================================================================
 
 NOTIFY_CHANNEL_PENDING - Notify Host that a channel has new work available
@@ -132,3 +148,84 @@ next channel.
 
 #define  NV_USERMODE_NOTIFY_CHANNEL_PENDING               0x00810090 /* -W-4R */
 #define  NV_USERMODE_NOTIFY_CHANNEL_PENDING_ID                  31:0 /* -W-UF */
+
+
+
+KEY
+===============================================================================
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/index.html b/manuals/volta/gv100/index.html
index aece319..fcada35 100644
--- a/manuals/volta/gv100/index.html
+++ b/manuals/volta/gv100/index.html
@@ -3,12 +3,17 @@
     <body>
         <h1>gv100</h1>
         <a href="dev_bus.ref.txt">dev_bus.ref.txt</a><br/>
-        <a href="dev_display.ref.txt">dev_display.ref.txt</a><br/>
+        <a href="dev_display_withoffset.ref.txt">dev_display_withoffset.ref.txt</a><br/>
         <a href="dev_fifo.ref.txt">dev_fifo.ref.txt</a><br/>
         <a href="dev_master.ref.txt">dev_master.ref.txt</a><br/>
+        <a href="dev_mmu_fault.ref.txt">dev_mmu_fault.ref.txt</a><br/>
         <a href="dev_pbdma.ref.txt">dev_pbdma.ref.txt</a><br/>
         <a href="dev_ram.ref.txt">dev_ram.ref.txt</a><br/>
         <a href="dev_timer.ref.txt">dev_timer.ref.txt</a><br/>
         <a href="dev_usermode.ref.txt">dev_usermode.ref.txt</a><br/>
+        <a href="pri_mmu_both.ref.txt">pri_mmu_both.ref.txt</a><br/>
+        <a href="pri_mmu_gpc.ref.txt">pri_mmu_gpc.ref.txt</a><br/>
+        <a href="pri_mmu_hshub.ref.txt">pri_mmu_hshub.ref.txt</a><br/>
+        <a href="pri_mmu_hub.ref.txt">pri_mmu_hub.ref.txt</a><br/>
     </body>
 </html>
diff --git a/manuals/volta/gv100/pri_mmu_both.ref.txt b/manuals/volta/gv100/pri_mmu_both.ref.txt
new file mode 100644
index 0000000..9ae585a
--- /dev/null
+++ b/manuals/volta/gv100/pri_mmu_both.ref.txt
@@ -0,0 +1,161 @@
+Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+#define NV_PFB_PRI_MMU_CTRL                                         0x00100C80 /* RW-4R */
+#define NV_PFB_PRI_MMU_CTRL_VOL_FAULT                                      1:1 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_VOL_FAULT_ENABLED                       0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_VOL_FAULT_DISABLED                      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_COMP_FAULT                                     2:2 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_COMP_FAULT_ENABLED                      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_COMP_FAULT_DISABLED                     0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN                                      4:3 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_FULL                          0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_HALF                          0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_QUARTER                       0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP                   0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE                                     6:5 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_ON                           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS          0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS           0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_OFF                          0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE                                 8:7 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_ON                       0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS       0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_OFF                      0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE                                   9:9 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE                    0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL                   0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE                        10:10 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE_FALSE             0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE_TRUE              0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE                        11:11 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE             0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE              0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE                       12:12 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE_FALSE            0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE_TRUE             0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR                         13:13 /* -WEVF */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR_FALSE              0x00000000 /* -WE-V */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR_TRUE               0x00000001 /* -W--T */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR                               14:14 /* R-EVF */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_FALSE                    0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_TRUE                     0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY                               15:15 /* R-EVF */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY_FALSE                    0x00000000 /* R---V */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY_TRUE                     0x00000001 /* R-E-V */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE                               23:16 /* R-EVF */
+#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE_INIT     32 /* R-E-V */
+#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE                       25:24 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2               0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC           0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW              0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER            0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_OVERRIDE_ATOMIC_DISABLE           26:26 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_OVERRIDE_ATOMIC_DISABLE_OFF  0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_OVERRIDE_ATOMIC_DISABLE_ON   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_APERTURE                                 29:28 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_MMU_APERTURE_VID_MEM                    0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_APERTURE_PEER_MEM                   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_VOL                                      30:30 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_MMU_VOL_FALSE                           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_VOL_TRUE                            0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_DISABLE                                  31:31 /* RWEVF */
+#define NV_PFB_PRI_MMU_CTRL_MMU_DISABLE_FALSE                       0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_CTRL_MMU_DISABLE_TRUE                        0x00000001 /* RW--V */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/pri_mmu_gpc.ref.txt b/manuals/volta/gv100/pri_mmu_gpc.ref.txt
new file mode 100644
index 0000000..24e1165
--- /dev/null
+++ b/manuals/volta/gv100/pri_mmu_gpc.ref.txt
@@ -0,0 +1,125 @@
+Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS                             0x000008AC /* RW-4R */
+
+        The MMU_NUM_ACTIVE_LTCS_USE_NVLINK segment of
+        MMU_NUM_ACTIVE_LTCS register hold the status of peer
+        connection through NVLINK. This is used to decide whether a
+        peer is PCIe connected or NVLink connected. If NVLink
+        connected then NVLINK_PEER_THROUGH_L2 determines whether the
+        peer traffic will be sent to master L2 or not(directly sent to
+        HSHUB).
+
+
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK                        23:16 /* RWEVF */
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT              0x00000000 /* RWE-V */
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i)    ((i)+16):((i)+16) /*       */
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1               8 /*       */
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED      0x00000001 /*       */
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED     0x00000000 /*       */
+
+
+        NVLINK_PEER_THROUGH_L2 flag tells MMU/HUBs whether NVLINK
+        connected peer traffic to be sent through master L2 (for
+        caching opportunity) or not. Caching is determined by VOL (==0
+        is cached) bit.
+
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2            24:24 /* RWEVF */
+#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT  0x00000000 /* RWE-V */
+
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/pri_mmu_hshub.ref.txt b/manuals/volta/gv100/pri_mmu_hshub.ref.txt
new file mode 100644
index 0000000..0231a7d
--- /dev/null
+++ b/manuals/volta/gv100/pri_mmu_hshub.ref.txt
@@ -0,0 +1,158 @@
+Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+#define NV_PFB_HSMMU_PRI_MMU_CTRL                                         0x001FAC80 /* RW-4R */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_VOL_FAULT                                      1:1 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_VOL_FAULT_ENABLED                       0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_VOL_FAULT_DISABLED                      0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_COMP_FAULT                                     2:2 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_COMP_FAULT_ENABLED                      0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_COMP_FAULT_DISABLED                     0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN                                      4:3 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_FULL                          0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_HALF                          0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_QUARTER                       0x00000002 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP                   0x00000003 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE                                     6:5 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_ON                           0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS          0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS           0x00000002 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_OFF                          0x00000003 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_L2_SEND_MODE                                   9:9 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE                    0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL                   0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE                       12:12 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE_FALSE            0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE_TRUE             0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE                       25:24 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2               0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC           0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW              0x00000002 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER            0x00000003 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_STRONG_BIT_OVERRIDE_ATOMIC_DISABLE           26:26 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_STRONG_BIT_OVERRIDE_ATOMIC_DISABLE_OFF  0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_CTRL_STRONG_BIT_OVERRIDE_ATOMIC_DISABLE_ON   0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL                                   0x001FACC4 /* RW-4R */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_WR_KIND                                  7:0 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT                      0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_RD_KIND                                 15:8 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT                      0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_DEBUG                                  16:16 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED                    0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED                     0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR                                     0x001FACC8 /* RW-4R */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE                                   1:0 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM                    0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_VOL                                        2:2 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_VOL_FALSE                           0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_VOL_TRUE                            0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_ADDR                                      31:4 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_ADDR_INIT                           0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT                      0x0000000c /*       */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD                                     0x001FACCC /* RW-4R */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE                                   1:0 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM                    0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_VOL                                        2:2 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_VOL_FALSE                           0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_VOL_TRUE                            0x00000001 /* RW--V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_ADDR                                      31:4 /* RWEVF */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_ADDR_INIT                           0x00000000 /* RWE-V */
+#define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT                      0x0000000c /*       */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here:
diff --git a/manuals/volta/gv100/pri_mmu_hub.ref.txt b/manuals/volta/gv100/pri_mmu_hub.ref.txt
new file mode 100644
index 0000000..3c47294
--- /dev/null
+++ b/manuals/volta/gv100/pri_mmu_hub.ref.txt
@@ -0,0 +1,423 @@
+Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL                              0x00100CF8 /* RW-4R */
+#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER                          1:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL          0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE         0x00000003 /* RWE-V */
+#define NV_PFB_PRI_MMU_BIND_IMB                                     0x00100CAC /* RW-4R */
+#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE                                   1:0 /* RWXVF */
+#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_VID_MEM                    0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_BIND_IMB_VOL                                        2:2 /* RWXVF */
+#define NV_PFB_PRI_MMU_BIND_IMB_VOL_FALSE                           0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_BIND_IMB_VOL_TRUE                            0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_BIND_IMB_ADDR                                      31:4 /* RWXVF */
+#define NV_PFB_PRI_MMU_BIND_IMB_ADDR_ALIGNMENT                      0x0000000c /*       */
+#define NV_PFB_PRI_MMU_BIND                                         0x00100CB0 /* RW-4R */
+#define NV_PFB_PRI_MMU_BIND_ENGINE_ID                                      7:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_INIT                          0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_BIND_UPPER_IMB_ADDR                                25:8 /* RWEVF */
+#define NV_PFB_PRI_MMU_BIND_UPPER_IMB_ADDR_INIT                     0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_BIND_OP                                           30:29 /* RWEVF */
+#define NV_PFB_PRI_MMU_BIND_OP_NORMAL                               0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_BIND_OP_SAVE                                 0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_BIND_OP_RESTORE                              0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_BIND_TRIGGER                                      31:31 /* -WEVF */
+#define NV_PFB_PRI_MMU_BIND_TRIGGER_FALSE                           0x00000000 /* -WE-V */
+#define NV_PFB_PRI_MMU_BIND_TRIGGER_TRUE                            0x00000001 /* -W--T */
+#define NV_PFB_PRI_MMU_INVALIDATE_VADDR                             0x00100CB4 /* RW-4R */
+#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_BITS                              31:4 /* RWEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_BITS_INIT                   0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_ALIGNMENT                   0x0000000c /*       */
+#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR                       0x00100CE8 /* RW-4R */
+#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_BITS                        19:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_BITS_INIT             0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB                               0x00100CB8 /* RW-4R */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE                             1:1 /* RWEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_INIT                 0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM              0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM              0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR                                31:4 /* RWEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_INIT                     0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT                0x0000000c /*       */
+#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB                         0x00100CEC /* RW-4R */
+#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_ADDR                          19:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_ADDR_INIT               0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PASID                               0x00100E64 /* RW-4R */
+#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VAL                                 19:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VAL_INIT                      0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE_SIZE                                0x00100E68 /* RW-4R */
+#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VAL                                   5:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VAL_INIT                       0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE                                   0x00100CBC /* RW-4R */
+#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA                                   0:0 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE                      0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE                       0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB                                  1:1 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE                     0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE                      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY                              2:2 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE                 0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE                  0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY                                   5:3 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE                       0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START                      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL              0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED            0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL              0x00000004 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL           0x00000005 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR                              6:6 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE                 0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE                  0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_ACK                                     8:7 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED                0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE                    0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY                     0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID                       14:9 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID                         19:15 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE                    20:20 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC           0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB           0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID                             21:21 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID_FALSE                  0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID_TRUE                   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE                              22:22 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE_FALSE                   0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE_TRUE                    0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH                            23:23 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH_FALSE                 0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH_TRUE                  0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL                           26:24 /* RWXVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL                  0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY             0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0           0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1           0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2           0x00000004 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3           0x00000005 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4           0x00000006 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5           0x00000007 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ          0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE         0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG 0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD        0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK   0x00000004 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL    0x00000005 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC 0x00000006 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL           0x00000007 /* RW--V */
+#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER                                31:31 /* -WEVF */
+#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE                     0x00000000 /* -WE-V */
+#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE                      0x00000001 /* -W--T */
+#define NV_PFB_PRI_MMU_INVALIDATE_MAX_CACHELINE_SIZE                0x00000010 /*       */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL                                   0x00100CC4 /* RW-4R */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_WR_KIND                                  7:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT                      0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_RD_KIND                                 15:8 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT                      0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG                                  16:16 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED                    0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED                     0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE                              18:17 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB                     0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB                    0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_WR                                     0x00100CC8 /* RW-4R */
+#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE                                   1:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM                    0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_WR_VOL                                        2:2 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_WR_VOL_FALSE                           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_WR_VOL_TRUE                            0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR                                      31:4 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_INIT                           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT                      0x0000000c /*       */
+#define NV_PFB_PRI_MMU_DEBUG_RD                                     0x00100CCC /* RW-4R */
+#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE                                   1:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM                    0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_RD_VOL                                        2:2 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_RD_VOL_FALSE                           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_RD_VOL_TRUE                            0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR                                      31:4 /* RWEVF */
+#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_INIT                           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT                      0x0000000c /*       */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL                         0x00100E00 /* RW-4R */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_MASK                      15:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_MASK_INIT           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_ADDR                     31:16 /* RWEVF */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_ADDR_INIT           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER(i)                       (0x00100E04+(i)*4) /* RW-4A */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER__SIZE_1                          8 /*       */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_MASK                      15:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_MASK_INIT           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_ADDR                     31:16 /* RWEVF */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_ADDR_INIT           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_GRANULARITY  37 /*  */
+#define NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER               0
+#define NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER                   1
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO(i)                     (0x00100E24+(i)*20) /* RW-4A */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO__SIZE_1                          2 /*       */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE                      0:0 /* RW-VF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_VIRTUAL       0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_PHYSICAL      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE                  2:1 /* RW-VF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_LOCAL     0x00000000 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_COH   0x00000002 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_NCOH  0x00000003 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_VOL                       3:3 /* RW-VF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR                         31:12 /* RW-VF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI(i)                     (0x00100E28+(i)*20) /* RW-4A */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI__SIZE_1                          2 /*       */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_ADDR                          31:0 /* RW-VF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i)                         (0x00100E2C+(i)*20) /* RW-4A */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1                     2 /*       */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR                              19:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR_RESET                  0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED                30:30 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO        0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES       0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR     0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW                        31:31 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_NO                0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_YES               0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR             0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT(i)                         (0x00100E30+(i)*20) /* R--4A */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT__SIZE_1                    2 /*       */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR                               19:0 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR_RESET                   0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED                 30:30 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO         0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES        0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW                         31:31 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO                 0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES                0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE(i)                    (0x00100E34+(i)*20) /* RW-4A */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE__SIZE_1                         2 /*       */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL                          19:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET              0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR               29:29 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE  0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT                 30:30 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO         0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES        0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE                      31:31 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE           0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE            0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO                                      0x00100E4C /* R--4R */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE                               1:0 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_LOCAL                  0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_PEER                   0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_COH                0x00000002 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_NCOH               0x00000003 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR                                      31:12 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR_RESET                           0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_HI                                      0x00100E50 /* R--4R */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR                                       31:0 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR_RESET                           0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO                                      0x00100E54 /* R--4R */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID                                   8:0 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID_RESET                      0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE                                  11:10 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_VID_MEM                     0x00000000 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_COHERENT            0x00000002 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_NONCOHERENT         0x00000003 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_RESET                       0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR                                      31:12 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR_RESET                           0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INST_HI                                      0x00100E58 /* R--4R */
+#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR                                       31:0 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR_RESET                           0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO                                         0x00100E5C /* R--4R */
+#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE                                     4:0 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET                        0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT                               7:7 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET                  0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT                                        14:8 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_RESET                            0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE                                  19:16 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_READ                        0x00000000 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_WRITE                       0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC                      0x00000002 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH                    0x00000003 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ                   0x00000000 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE                  0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC                 0x00000002 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG          0x00000002 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH               0x00000003 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK            0x00000004 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ                   0x00000008 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE                  0x00000009 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC                 0x0000000a /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH               0x0000000b /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_RESET                       0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE                                  20:20 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE_RESET                       0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID                                       28:24 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID_RESET                            0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE                               29:29 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE_RESET                    0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN                          30:30 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET               0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_INFO_VALID                                        31:31 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_INFO_VALID_RESET                             0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS                                           0x00100E60 /* RW-4R */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS                                0:0 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET                   0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_CLEAR                   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_SET                     0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT                                1:1 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_RESET                   0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_CLEAR                   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_SET                     0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS                                2:2 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_RESET                   0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_CLEAR                   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_SET                     0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT                                3:3 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_RESET                   0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_CLEAR                   0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_SET                     0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS                                 4:4 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_RESET                    0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_CLEAR                    0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_SET                      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT                                 5:5 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_RESET                    0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_CLEAR                    0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_SET                      0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS                               6:6 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_RESET                  0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_CLEAR                  0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_SET                    0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT                               7:7 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_RESET                  0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_CLEAR                  0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_SET                    0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE                                       8:8 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_RESET                          0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_SET                            0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE                                   9:9 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_RESET                      0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_SET                        0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR                               10:10 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_RESET                    0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_SET                      0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR                           11:11 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_RESET                0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_SET                  0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW                            12:12 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_RESET                 0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_SET                   0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW                        13:13 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_RESET             0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_SET               0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED                    14:14 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_RESET         0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_SET           0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED                15:15 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET     0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_SET       0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY                                           30:30 /* R-EVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_FALSE                                0x00000000 /* R-E-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TRUE                                 0x00000001 /* R---V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID                                          31:31 /* RWEVF */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_RESET                               0x00000000 /* RWE-V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_CLEAR                               0x00000001 /* RW--V */
+#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_SET                                 0x00000001 /* RW--V */
+
+--------------------------------------------------------------------------------
+                         KEY LEGEND
+--------------------------------------------------------------------------------
+
+Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
+The following legend shows accepted values for each of the 5 fields:
+  Read, Write, Internal State, Declaration/Size, and Define Indicator.
+
+  Read
+    ' ' = Other Information
+    '-' = Field is part of a write-only register
+    'C' = Value read is always the same, constant value line follows (C)
+    'R' = Value is read
+
+
+  Write
+    ' ' = Other Information
+    '-' = Must not be written (D), value ignored when written (R,A,F)
+    'W' = Can be written
+
+
+  Internal State
+    ' ' = Other Information
+    '-' = No internal state
+    'X' = Internal state, initial value is unknown
+    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
+    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
+    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
+    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
+
+    'V' = (legacy) Internal state, initialize at volatile reset
+    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
+    'C' = (legacy) Internal state, initial value at object creation
+    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
+
+
+  Declaration/Size
+    ' ' = Other Information
+    '-' = Does Not Apply
+    'V' = Type is void
+    'U' = Type is unsigned integer
+    'S' = Type is signed integer
+    'F' = Type is IEEE floating point
+    '1' = Byte size (008)
+    '2' = Short size (016)
+    '3' = Three byte size (024)
+    '4' = Word size (032)
+    '8' = Double size (064)
+
+
+  Define Indicator
+    ' ' = Other Information
+    'C' = Clear value
+    'D' = Device
+    'L' = Logical device.
+    'M' = Memory
+    'R' = Register
+    'A' = Array of Registers
+    'F' = Field
+    'V' = Value
+    'T' = Task
+    'P' = Phantom Register
+
+    'B' = (legacy) Bundle address
+    'G' = (legacy) General purpose configuration register
+    'C' = (legacy) Class
+
+  Reset signal defaults for graphics engine registers.
+    All graphics engine registers use the following defaults for reset signals:
+     'E' = initialized with engine_reset_
+     'I' = initialized with context_reset_
+     'B' = initialized with reset_IB_dly_
+
+  Reset signal
+    For units that differ from the graphics engine defaults, the reset signals should be defined here: