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Diffstat (limited to 'manuals/volta/gv100/dev_master.ref.txt')
| -rw-r--r-- | manuals/volta/gv100/dev_master.ref.txt | 363 |
1 files changed, 363 insertions, 0 deletions
diff --git a/manuals/volta/gv100/dev_master.ref.txt b/manuals/volta/gv100/dev_master.ref.txt new file mode 100644 index 0000000..8ae6133 --- /dev/null +++ b/manuals/volta/gv100/dev_master.ref.txt @@ -0,0 +1,363 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ +#define NV_PMC_BOOT_0_ID 31:0 /* */ +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */ +#define NV_PMC_BOOT_0_MINOR_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_10 0x0000000A /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_11 0x0000000B /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_12 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_13 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_14 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_15 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_INIT 0x00000001 /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_INIT 0x00000000 /* R---V */ +#define NV_PMC_BOOT_0_RESERVED_0 11:8 /* */ +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_INIT 0x00000000 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GF100 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GF110 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GK100 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GK110 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GK200 0x00000010 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GM000 0x00000011 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GM100 0x00000011 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GM200 0x00000012 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GP100 0x00000013 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GV100 0x00000014 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 0x00000015 /* R---V */ +#define NV_PMC_BOOT_1 0x00000004 /* RW-4R */ +#define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */ +#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* R---V */ +#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* R---V */ +#define NV_PMC_BOOT_1_VGPU16 16:16 /* R--VF */ +#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* R---V */ +#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* R---V */ +#define NV_PMC_BOOT_2 0x00000008 /* R--4R */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION 3:0 /* R-XVF */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID 7:4 /* R-XVF */ +#define NV_PMC_BOOT_2_FAB_ID_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */ +#define NV_PMC_BOOT_42_MINOR_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_10 0x0000000A /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_11 0x0000000B /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_12 0x0000000C /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_13 0x0000000D /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_14 0x0000000E /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_15 0x0000000F /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_0 0x00000000 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_1 0x00000001 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_2 0x00000002 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_3 0x00000003 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_4 0x00000004 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_5 0x00000005 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_6 0x00000006 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_7 0x00000007 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_8 0x00000008 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_9 0x00000009 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_A 0x0000000A /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_B 0x0000000B /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_C 0x0000000C /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_D 0x0000000D /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_E 0x0000000E /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_F 0x0000000F /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GP100 0x00000013 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GV100 0x00000014 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GV110 0x00000015 /* */ +#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */ +#define NV_PMC_BOOT_42_CHIP_ID_GP000 0x00000131 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP100 0x00000130 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP102 0x00000132 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP104 0x00000134 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP104V 0x00000139 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP106 0x00000136 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP107 0x00000137 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP108 0x00000138 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP108V 0x0000013A /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GV100 0x00000140 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GV10B 0x0000014B /* R---V */ +#define NV_PMC_INTR(i) (0x00000100+(i)*4) /* R--4A */ +#define NV_PMC_INTR__SIZE_1 4 /* */ +#define NV_PMC_INTR_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_DEVICE_NOT_PENDING 0x00000000 /* */ +#define NV_PMC_INTR_DEVICE_PENDING 0x00000001 /* */ +#define NV_PMC_INTR_PFIFO 8:8 /* R--VF */ +#define NV_PMC_INTR_PFIFO_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PFIFO_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_HUB 9:9 /* R--VF */ +#define NV_PMC_INTR_HUB_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_HUB_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PFB 13:13 /* R--VF */ +#define NV_PMC_INTR_PFB_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PFB_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_THERMAL 18:18 /* R--VF */ +#define NV_PMC_INTR_THERMAL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_THERMAL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_HDACODEC 19:19 /* R--VF */ +#define NV_PMC_INTR_HDACODEC_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_HDACODEC_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PTIMER 20:20 /* R--VF */ +#define NV_PMC_INTR_PTIMER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PTIMER_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PMGR 21:21 /* R--VF */ +#define NV_PMC_INTR_PMGR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PMGR_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_DFD 23:23 /* R--VF */ +#define NV_PMC_INTR_DFD_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_DFD_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PMU 24:24 /* R--VF */ +#define NV_PMC_INTR_PMU_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PMU_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_LTC_ALL 25:25 /* R--VF */ +#define NV_PMC_INTR_LTC_ALL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_LTC_ALL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PDISP 26:26 /* R--VF */ +#define NV_PMC_INTR_PDISP_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PDISP_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PBUS 28:28 /* R--VF */ +#define NV_PMC_INTR_PBUS_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PBUS_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_XVE 29:29 /* R--VF */ +#define NV_PMC_INTR_XVE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_XVE_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PRIV_RING 30:30 /* R--VF */ +#define NV_PMC_INTR_PRIV_RING_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PRIV_RING_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_SOFTWARE 31:31 /* R--VF */ +#define NV_PMC_INTR_SOFTWARE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_SOFTWARE_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_MODE(i) (0x00000120+(i)*4) /* R--4A */ +#define NV_PMC_INTR_MODE__SIZE_1 4 /* */ +#define NV_PMC_INTR_MODE_BIT(i) (i):(i) /* */ +#define NV_PMC_INTR_MODE_BIT__SIZE_1 32 /* */ +#define NV_PMC_INTR_MODE_BIT_LEVEL 0x00000000 /* */ +#define NV_PMC_INTR_MODE_BIT_EDGE 0x00000001 /* */ +#define NV_PMC_INTR_MODE_VALUE 31:0 /* C--VF */ +#define NV_PMC_INTR_MODE_VALUE_INIT 0x00000000 /* C---V */ +#define NV_PMC_INTR_EN(i) (0x00000140+(i)*4) /* R--4A */ +#define NV_PMC_INTR_EN__SIZE_1 4 /* */ +#define NV_PMC_INTR_EN_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_EN_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_EN_DEVICE_DISABLED 0x00000000 /* */ +#define NV_PMC_INTR_EN_DEVICE_ENABLED 0x00000001 /* */ +#define NV_PMC_INTR_EN_VALUE 31:0 /* R-IVF */ +#define NV_PMC_INTR_EN_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_PMC_INTR_EN_SET(i) (0x00000160+(i)*4) /* -W-4A */ +#define NV_PMC_INTR_EN_SET__SIZE_1 4 /* */ +#define NV_PMC_INTR_EN_SET_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_EN_SET_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_EN_SET_DEVICE_SET 0x00000001 /* */ +#define NV_PMC_INTR_EN_SET_VALUE 31:0 /* -W-VF */ +#define NV_PMC_INTR_EN_CLEAR(i) (0x00000180+(i)*4) /* -W-4A */ +#define NV_PMC_INTR_EN_CLEAR__SIZE_1 4 /* */ +#define NV_PMC_INTR_EN_CLEAR_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */ +#define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */ +#define NV_PMC_INTR_SW(i) (0x000001A0+(i)*4) /* RW-4A */ +#define NV_PMC_INTR_SW__SIZE_1 4 /* */ +#define NV_PMC_INTR_SW_ASSERT 0:0 /* RWIVF */ +#define NV_PMC_INTR_SW_ASSERT_TRUE 0x00000001 /* RW--V */ +#define NV_PMC_INTR_SW_ASSERT_FALSE 0x00000000 /* RWI-V */ +#define NV_PMC_INTR_LTC 0x000001C0 /* R--4R */ +#define NV_PMC_INTR_LTC_PART_MASK 16:0 /* R--VF */ +#define NV_PMC_INTR_LTC_PART_MASK_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_LTC_PART_MASK_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_LTC_PART(i) (i):(i) /* */ +#define NV_PMC_INTR_LTC_PART__SIZE_1 16 /* */ +#define NV_PMC_INTR_LTC_PART_NOT_PENDING 0x00000000 /* */ +#define NV_PMC_INTR_LTC_PART_PENDING 0x00000001 /* */ +#define NV_PMC_INTR_FBPA 0x000001D0 /* R--4R */ +#define NV_PMC_INTR_FBPA_PART_MASK 16:0 /* R--VF */ +#define NV_PMC_INTR_FBPA_PART_MASK_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_FBPA_PART_MASK_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL 30:30 /* R--VF */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL 31:31 /* R--VF */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_FBPA_PART(i) (i):(i) /* */ +#define NV_PMC_INTR_FBPA_PART__SIZE_1 16 /* */ +#define NV_PMC_INTR_FBPA_PART_NOT_PENDING 0x00000000 /* */ +#define NV_PMC_INTR_FBPA_PART_PENDING 0x00000001 /* */ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */ +#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */ +#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */ +#define NV_PMC_ENABLE_PRIV_RING 5:5 /* RWIVF */ +#define NV_PMC_ENABLE_PRIV_RING_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PRIV_RING_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_HOST_SCHEDULER 8:8 /* */ +#define NV_PMC_ENABLE_HOST_SCHEDULER_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_HOST_SCHEDULER_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVLINK 25:25 /* RWIVF */ +#define NV_PMC_ENABLE_NVLINK_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_NVLINK_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_ZPW 26:26 /* RWIVF */ +#define NV_PMC_ENABLE_ZPW_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_ZPW_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_BLG 27:27 /* RWIVF */ +#define NV_PMC_ENABLE_BLG_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_BLG_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */ +#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB 0x00000204 /* RW-4R */ +#define NV_PMC_ENABLE_PB_0 0:0 /* RWIVF */ +#define NV_PMC_ENABLE_PB_0_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_0_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_1 1:1 /* RWIVF */ +#define NV_PMC_ENABLE_PB_1_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_1_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_2 2:2 /* RWIVF */ +#define NV_PMC_ENABLE_PB_2_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_2_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_3 3:3 /* RWIVF */ +#define NV_PMC_ENABLE_PB_3_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_3_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_4 4:4 /* RWIVF */ +#define NV_PMC_ENABLE_PB_4_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_4_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_5 5:5 /* RWIVF */ +#define NV_PMC_ENABLE_PB_5_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_5_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_6 6:6 /* RWIVF */ +#define NV_PMC_ENABLE_PB_6_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_6_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_7 7:7 /* RWIVF */ +#define NV_PMC_ENABLE_PB_7_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_7_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_8 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PB_8_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_8_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_9 9:9 /* RWIVF */ +#define NV_PMC_ENABLE_PB_9_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_9_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_10 10:10 /* RWIVF */ +#define NV_PMC_ENABLE_PB_10_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_10_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_11 11:11 /* RWIVF */ +#define NV_PMC_ENABLE_PB_11_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_11_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_12 12:12 /* RWIVF */ +#define NV_PMC_ENABLE_PB_12_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_12_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_13 13:13 /* RWIVF */ +#define NV_PMC_ENABLE_PB_13_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_13_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) /* */ +#define NV_PMC_ENABLE_PB_SEL__SIZE_1 14 /* */ |