From 09307cb4f9b0352b3045fde1d3f058197b01d018 Mon Sep 17 00:00:00 2001
From: John Hubbard <jhubbard@nvidia.com>
Date: Thu, 13 Jun 2019 21:04:49 -0700
Subject: New class files directory, delete old locations

As decided recently in an OpenSource-Approval discussion, we
want the directory structure for GPU classes to have the following
structure:

classes/<category>/<files>

This CL does that. It moves these directories:

    Compute-Class-Methods/*
    Display-Class-Methods/*

to:
    classes/compute/
    classes/display/

Regenerate index.html files to match (important for the
"github pages" site, at https://nvidia.github.io/open-gpu-doc/ .

Reviewed by: Maneet Singh
---
 Compute-Class-Methods/cl50c0.h   |  741 ------------------------
 Compute-Class-Methods/cl85c0.h   |  747 ------------------------
 Compute-Class-Methods/cl90c0.h   | 1033 ---------------------------------
 Compute-Class-Methods/cl91c0.h   | 1049 ---------------------------------
 Compute-Class-Methods/cla0c0.h   |  836 ---------------------------
 Compute-Class-Methods/cla1c0.h   |  866 ---------------------------
 Compute-Class-Methods/clb0c0.h   |  931 -----------------------------
 Compute-Class-Methods/clb1c0.h   |  968 -------------------------------
 Compute-Class-Methods/clc0c0.h   | 1006 --------------------------------
 Compute-Class-Methods/clc1c0.h   | 1026 --------------------------------
 Compute-Class-Methods/clc3c0.h   |  912 -----------------------------
 Compute-Class-Methods/clc5c0.h   |  942 ------------------------------
 Compute-Class-Methods/index.html |   18 -
 Display-Class-Methods/README.txt |  190 ------
 Display-Class-Methods/cl507a.h   |   56 --
 Display-Class-Methods/cl507b.h   |   59 --
 Display-Class-Methods/cl507c.h   |  194 -------
 Display-Class-Methods/cl507d.h   |  676 ----------------------
 Display-Class-Methods/cl507e.h   |  173 ------
 Display-Class-Methods/cl827a.h   |   56 --
 Display-Class-Methods/cl827b.h   |   59 --
 Display-Class-Methods/cl827c.h   |  181 ------
 Display-Class-Methods/cl827d.h   |  678 ----------------------
 Display-Class-Methods/cl827e.h   |  183 ------
 Display-Class-Methods/cl837c.h   |  181 ------
 Display-Class-Methods/cl837d.h   |  709 -----------------------
 Display-Class-Methods/cl837e.h   |  195 -------
 Display-Class-Methods/cl857a.h   |   56 --
 Display-Class-Methods/cl857b.h   |   59 --
 Display-Class-Methods/cl857c.h   |  188 ------
 Display-Class-Methods/cl857d.h   | 1121 -----------------------------------
 Display-Class-Methods/cl857e.h   |  195 -------
 Display-Class-Methods/cl887d.h   | 1078 ----------------------------------
 Display-Class-Methods/cl907a.h   |   56 --
 Display-Class-Methods/cl907b.h   |   59 --
 Display-Class-Methods/cl907c.h   |  254 --------
 Display-Class-Methods/cl907d.h   | 1140 ------------------------------------
 Display-Class-Methods/cl907e.h   |  255 --------
 Display-Class-Methods/cl917a.h   |   56 --
 Display-Class-Methods/cl917b.h   |   60 --
 Display-Class-Methods/cl917c.h   |  290 ----------
 Display-Class-Methods/cl917d.h   | 1176 -------------------------------------
 Display-Class-Methods/cl917e.h   |  257 --------
 Display-Class-Methods/cl927c.h   |  291 ----------
 Display-Class-Methods/cl927d.h   | 1181 -------------------------------------
 Display-Class-Methods/cl947d.h   | 1189 --------------------------------------
 Display-Class-Methods/cl957d.h   | 1185 -------------------------------------
 Display-Class-Methods/cl977d.h   | 1170 -------------------------------------
 Display-Class-Methods/cl987d.h   | 1173 -------------------------------------
 Display-Class-Methods/clc37a.h   |  180 ------
 Display-Class-Methods/clc37b.h   |   64 --
 Display-Class-Methods/clc37d.h   |  625 --------------------
 Display-Class-Methods/clc37e.h   |  446 --------------
 Display-Class-Methods/index.html |   46 --
 classes/compute/cl50c0.h         |  741 ++++++++++++++++++++++++
 classes/compute/cl85c0.h         |  747 ++++++++++++++++++++++++
 classes/compute/cl90c0.h         | 1033 +++++++++++++++++++++++++++++++++
 classes/compute/cl91c0.h         | 1049 +++++++++++++++++++++++++++++++++
 classes/compute/cla0c0.h         |  836 +++++++++++++++++++++++++++
 classes/compute/cla1c0.h         |  866 +++++++++++++++++++++++++++
 classes/compute/clb0c0.h         |  931 +++++++++++++++++++++++++++++
 classes/compute/clb1c0.h         |  968 +++++++++++++++++++++++++++++++
 classes/compute/clc0c0.h         | 1006 ++++++++++++++++++++++++++++++++
 classes/compute/clc1c0.h         | 1026 ++++++++++++++++++++++++++++++++
 classes/compute/clc3c0.h         |  912 +++++++++++++++++++++++++++++
 classes/compute/clc5c0.h         |  942 ++++++++++++++++++++++++++++++
 classes/compute/index.html       |   18 +
 classes/display/README.txt       |  190 ++++++
 classes/display/cl507a.h         |   56 ++
 classes/display/cl507b.h         |   59 ++
 classes/display/cl507c.h         |  194 +++++++
 classes/display/cl507d.h         |  676 ++++++++++++++++++++++
 classes/display/cl507e.h         |  173 ++++++
 classes/display/cl827a.h         |   56 ++
 classes/display/cl827b.h         |   59 ++
 classes/display/cl827c.h         |  181 ++++++
 classes/display/cl827d.h         |  678 ++++++++++++++++++++++
 classes/display/cl827e.h         |  183 ++++++
 classes/display/cl837c.h         |  181 ++++++
 classes/display/cl837d.h         |  709 +++++++++++++++++++++++
 classes/display/cl837e.h         |  195 +++++++
 classes/display/cl857a.h         |   56 ++
 classes/display/cl857b.h         |   59 ++
 classes/display/cl857c.h         |  188 ++++++
 classes/display/cl857d.h         | 1121 +++++++++++++++++++++++++++++++++++
 classes/display/cl857e.h         |  195 +++++++
 classes/display/cl887d.h         | 1078 ++++++++++++++++++++++++++++++++++
 classes/display/cl907a.h         |   56 ++
 classes/display/cl907b.h         |   59 ++
 classes/display/cl907c.h         |  254 ++++++++
 classes/display/cl907d.h         | 1140 ++++++++++++++++++++++++++++++++++++
 classes/display/cl907e.h         |  255 ++++++++
 classes/display/cl917a.h         |   56 ++
 classes/display/cl917b.h         |   60 ++
 classes/display/cl917c.h         |  290 ++++++++++
 classes/display/cl917d.h         | 1176 +++++++++++++++++++++++++++++++++++++
 classes/display/cl917e.h         |  257 ++++++++
 classes/display/cl927c.h         |  291 ++++++++++
 classes/display/cl927d.h         | 1181 +++++++++++++++++++++++++++++++++++++
 classes/display/cl947d.h         | 1189 ++++++++++++++++++++++++++++++++++++++
 classes/display/cl957d.h         | 1185 +++++++++++++++++++++++++++++++++++++
 classes/display/cl977d.h         | 1170 +++++++++++++++++++++++++++++++++++++
 classes/display/cl987d.h         | 1173 +++++++++++++++++++++++++++++++++++++
 classes/display/clc37a.h         |  180 ++++++
 classes/display/clc37b.h         |   64 ++
 classes/display/clc37d.h         |  625 ++++++++++++++++++++
 classes/display/clc37e.h         |  446 ++++++++++++++
 classes/display/index.html       |   46 ++
 classes/index.html               |    8 +
 index.html                       |    3 +-
 110 files changed, 28524 insertions(+), 28517 deletions(-)
 delete mode 100644 Compute-Class-Methods/cl50c0.h
 delete mode 100644 Compute-Class-Methods/cl85c0.h
 delete mode 100644 Compute-Class-Methods/cl90c0.h
 delete mode 100644 Compute-Class-Methods/cl91c0.h
 delete mode 100644 Compute-Class-Methods/cla0c0.h
 delete mode 100644 Compute-Class-Methods/cla1c0.h
 delete mode 100644 Compute-Class-Methods/clb0c0.h
 delete mode 100644 Compute-Class-Methods/clb1c0.h
 delete mode 100644 Compute-Class-Methods/clc0c0.h
 delete mode 100644 Compute-Class-Methods/clc1c0.h
 delete mode 100644 Compute-Class-Methods/clc3c0.h
 delete mode 100644 Compute-Class-Methods/clc5c0.h
 delete mode 100644 Compute-Class-Methods/index.html
 delete mode 100644 Display-Class-Methods/README.txt
 delete mode 100644 Display-Class-Methods/cl507a.h
 delete mode 100644 Display-Class-Methods/cl507b.h
 delete mode 100644 Display-Class-Methods/cl507c.h
 delete mode 100644 Display-Class-Methods/cl507d.h
 delete mode 100644 Display-Class-Methods/cl507e.h
 delete mode 100644 Display-Class-Methods/cl827a.h
 delete mode 100644 Display-Class-Methods/cl827b.h
 delete mode 100644 Display-Class-Methods/cl827c.h
 delete mode 100644 Display-Class-Methods/cl827d.h
 delete mode 100644 Display-Class-Methods/cl827e.h
 delete mode 100644 Display-Class-Methods/cl837c.h
 delete mode 100644 Display-Class-Methods/cl837d.h
 delete mode 100644 Display-Class-Methods/cl837e.h
 delete mode 100644 Display-Class-Methods/cl857a.h
 delete mode 100644 Display-Class-Methods/cl857b.h
 delete mode 100644 Display-Class-Methods/cl857c.h
 delete mode 100644 Display-Class-Methods/cl857d.h
 delete mode 100644 Display-Class-Methods/cl857e.h
 delete mode 100644 Display-Class-Methods/cl887d.h
 delete mode 100644 Display-Class-Methods/cl907a.h
 delete mode 100644 Display-Class-Methods/cl907b.h
 delete mode 100644 Display-Class-Methods/cl907c.h
 delete mode 100644 Display-Class-Methods/cl907d.h
 delete mode 100644 Display-Class-Methods/cl907e.h
 delete mode 100644 Display-Class-Methods/cl917a.h
 delete mode 100644 Display-Class-Methods/cl917b.h
 delete mode 100644 Display-Class-Methods/cl917c.h
 delete mode 100644 Display-Class-Methods/cl917d.h
 delete mode 100644 Display-Class-Methods/cl917e.h
 delete mode 100644 Display-Class-Methods/cl927c.h
 delete mode 100644 Display-Class-Methods/cl927d.h
 delete mode 100644 Display-Class-Methods/cl947d.h
 delete mode 100644 Display-Class-Methods/cl957d.h
 delete mode 100644 Display-Class-Methods/cl977d.h
 delete mode 100644 Display-Class-Methods/cl987d.h
 delete mode 100644 Display-Class-Methods/clc37a.h
 delete mode 100644 Display-Class-Methods/clc37b.h
 delete mode 100644 Display-Class-Methods/clc37d.h
 delete mode 100644 Display-Class-Methods/clc37e.h
 delete mode 100644 Display-Class-Methods/index.html
 create mode 100644 classes/compute/cl50c0.h
 create mode 100644 classes/compute/cl85c0.h
 create mode 100644 classes/compute/cl90c0.h
 create mode 100644 classes/compute/cl91c0.h
 create mode 100644 classes/compute/cla0c0.h
 create mode 100644 classes/compute/cla1c0.h
 create mode 100644 classes/compute/clb0c0.h
 create mode 100644 classes/compute/clb1c0.h
 create mode 100644 classes/compute/clc0c0.h
 create mode 100644 classes/compute/clc1c0.h
 create mode 100644 classes/compute/clc3c0.h
 create mode 100644 classes/compute/clc5c0.h
 create mode 100644 classes/compute/index.html
 create mode 100644 classes/display/README.txt
 create mode 100644 classes/display/cl507a.h
 create mode 100644 classes/display/cl507b.h
 create mode 100644 classes/display/cl507c.h
 create mode 100644 classes/display/cl507d.h
 create mode 100644 classes/display/cl507e.h
 create mode 100644 classes/display/cl827a.h
 create mode 100644 classes/display/cl827b.h
 create mode 100644 classes/display/cl827c.h
 create mode 100644 classes/display/cl827d.h
 create mode 100644 classes/display/cl827e.h
 create mode 100644 classes/display/cl837c.h
 create mode 100644 classes/display/cl837d.h
 create mode 100644 classes/display/cl837e.h
 create mode 100644 classes/display/cl857a.h
 create mode 100644 classes/display/cl857b.h
 create mode 100644 classes/display/cl857c.h
 create mode 100644 classes/display/cl857d.h
 create mode 100644 classes/display/cl857e.h
 create mode 100644 classes/display/cl887d.h
 create mode 100644 classes/display/cl907a.h
 create mode 100644 classes/display/cl907b.h
 create mode 100644 classes/display/cl907c.h
 create mode 100644 classes/display/cl907d.h
 create mode 100644 classes/display/cl907e.h
 create mode 100644 classes/display/cl917a.h
 create mode 100644 classes/display/cl917b.h
 create mode 100644 classes/display/cl917c.h
 create mode 100644 classes/display/cl917d.h
 create mode 100644 classes/display/cl917e.h
 create mode 100644 classes/display/cl927c.h
 create mode 100644 classes/display/cl927d.h
 create mode 100644 classes/display/cl947d.h
 create mode 100644 classes/display/cl957d.h
 create mode 100644 classes/display/cl977d.h
 create mode 100644 classes/display/cl987d.h
 create mode 100644 classes/display/clc37a.h
 create mode 100644 classes/display/clc37b.h
 create mode 100644 classes/display/clc37d.h
 create mode 100644 classes/display/clc37e.h
 create mode 100644 classes/display/index.html
 create mode 100644 classes/index.html

diff --git a/Compute-Class-Methods/cl50c0.h b/Compute-Class-Methods/cl50c0.h
deleted file mode 100644
index e22fed8..0000000
--- a/Compute-Class-Methods/cl50c0.h
+++ /dev/null
@@ -1,741 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_nv50_compute_h_
-#define _cl_nv50_compute_h_
-
-/* This file is generated - do not edit. */
-
-#include "nvtypes.h"
-
-#define NV50_COMPUTE    0x50C0
-
-typedef volatile struct _cl50c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 Notify;
-    NvU32 Reserved_0x108[0x2];
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0xB];
-    NvU32 PmTrigger;
-    NvU32 Reserved_0x144[0xF];
-    NvU32 SetContextDmaNotify;
-    NvU32 Reserved_0x184[0x7];
-    NvU32 SetCtxDmaGlobalMem;
-    NvU32 SetCtxDmaSemaphore;
-    NvU32 Reserved_0x1A8[0x4];
-    NvU32 SetCtxDmaShaderThreadMemory;
-    NvU32 SetCtxDmaShaderThreadStack;
-    NvU32 SetCtxDmaShaderProgram;
-    NvU32 SetCtxDmaTextureSampler;
-    NvU32 SetCtxDmaTextureHeaders;
-    NvU32 SetCtxDmaTexture;
-    NvU32 Reserved_0x1D0[0xC];
-    struct {
-        NvU32 Control;
-        NvU32 QuerySessionKey;
-        NvU32 GetSessionKey;
-        NvU32 SetEncryption;
-    } Decryption[0x1];
-    NvU32 SetCtaProgramA;
-    NvU32 SetCtaProgramB;
-    NvU32 SetShaderThreadStackA;
-    NvU32 SetShaderThreadStackB;
-    NvU32 SetShaderThreadStackC;
-    NvU32 SetApiCallLimit;
-    NvU32 SetShaderL1CacheControl;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 LoadConstantSelector;
-    NvU32 LoadConstant[0x10];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 Reserved_0x284[0x1];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 TestForCompute;
-    NvU32 SetShaderScheduling;
-    NvU32 SetShaderThreadMemoryA;
-    NvU32 SetShaderThreadMemoryB;
-    NvU32 SetShaderThreadMemoryC;
-    NvU32 SetWorkDistribution;
-    NvU32 LoadConstantBufferTableA;
-    NvU32 LoadConstantBufferTableB;
-    NvU32 LoadConstantBufferTableC;
-    NvU32 SetShaderErrorTrapControl;
-    NvU32 SetCtaResourceAllocation;
-    NvU32 SetCtaThreadControl;
-    NvU32 SetPhaseIdControl;
-    NvU32 SetCtaRegisterCount;
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 SetShaderPerformanceCounterValue[0x4];
-    NvU32 SetShaderPerformanceCounterControl[0x4];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 ResetCtaTrackingRam;
-    NvU32 Initialize;
-    NvU32 SetShaderThreadMemoryThrottle;
-    NvU32 SetShaderThreadMemoryThrottleControl;
-    NvU32 SetShaderThreadStackThrottle;
-    NvU32 SetShaderThreadStackThrottleControl;
-    NvU32 PrefetchShaderInstructions;
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 SetLaunchEnableA;
-    NvU32 SetLaunchEnableB;
-    NvU32 SetLaunchEnableC;
-    NvU32 SetCubemapAddressModeOverride;
-    NvU32 PipeNop;
-    NvU32 Reserved_0x334[0x3];
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x350[0x2];
-    NvU32 SetGlobalColorKey;
-    NvU32 ResetRefCount;
-    NvU32 WaitRefCount;
-    NvU32 SetRefCountValue;
-    NvU32 Launch;
-    NvU32 SetLaunchId;
-    NvU32 SetLaunchControl;
-    NvU32 SetParameterSize;
-    NvU32 SetSamplerBinding;
-    NvU32 SetShaderControl;
-    NvU32 InvalidateShaderCache;
-    NvU32 SetRasterControl;
-    NvU32 SetCtaFlags;
-    NvU32 Reserved_0x38C[0x6];
-    NvU32 SetCtaRasterSize;
-    NvU32 SetCtaGrfSize;
-    NvU32 SetCtaThreadDimensionA;
-    NvU32 SetCtaThreadDimensionB;
-    NvU32 SetCtaProgramStart;
-    NvU32 SetCtaRegisterAllocation;
-    NvU32 SetCtaTexture;
-    NvU32 BindCtaTextureSampler;
-    NvU32 BindCtaTextureHeader;
-    NvU32 BindConstantBuffer;
-    NvU32 PrefetchTextureSampler;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x3D4[0x6];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x3F0[0x4];
-    struct {
-        NvU32 A;
-        NvU32 B;
-        NvU32 Size;
-        NvU32 Limit;
-        NvU32 Format;
-        NvU32 Reserved_0x14[0x3];
-    } SetGlobalMem[0x10];
-    NvU32 Parameter[0x40];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-} nv50_compute_t;
-
-
-#define NV50C0_SET_OBJECT                                                                                  0x0000
-#define NV50C0_SET_OBJECT_POINTER                                                                            15:0
-
-#define NV50C0_NO_OPERATION                                                                                0x0100
-#define NV50C0_NO_OPERATION_V                                                                                31:0
-
-#define NV50C0_NOTIFY                                                                                      0x0104
-#define NV50C0_NOTIFY_TYPE                                                                                   31:0
-#define NV50C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NV50C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NV50C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NV50C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NV50C0_PM_TRIGGER                                                                                  0x0140
-#define NV50C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NV50C0_SET_CONTEXT_DMA_NOTIFY                                                                      0x0180
-#define NV50C0_SET_CONTEXT_DMA_NOTIFY_HANDLE                                                                 31:0
-
-#define NV50C0_SET_CTX_DMA_GLOBAL_MEM                                                                      0x01a0
-#define NV50C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE                                                                 31:0
-
-#define NV50C0_SET_CTX_DMA_SEMAPHORE                                                                       0x01a4
-#define NV50C0_SET_CTX_DMA_SEMAPHORE_HANDLE                                                                  31:0
-
-#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY                                                            0x01b8
-#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE                                                       31:0
-
-#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK                                                             0x01bc
-#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE                                                        31:0
-
-#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM                                                                  0x01c0
-#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE                                                             31:0
-
-#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER                                                                 0x01c4
-#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE                                                            31:0
-
-#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS                                                                 0x01c8
-#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE                                                            31:0
-
-#define NV50C0_SET_CTX_DMA_TEXTURE                                                                         0x01cc
-#define NV50C0_SET_CTX_DMA_TEXTURE_HANDLE                                                                    31:0
-
-#define NV50C0_DECRYPTION_CONTROL(j)                                                              (0x0200+(j)*16)
-#define NV50C0_DECRYPTION_CONTROL_ALGORITHM                                                                  15:0
-#define NV50C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE                                            0x00000000
-#define NV50C0_DECRYPTION_CONTROL_KEY_COUNT                                                                 23:16
-
-#define NV50C0_DECRYPTION_QUERY_SESSION_KEY(j)                                                    (0x0204+(j)*16)
-#define NV50C0_DECRYPTION_QUERY_SESSION_KEY_V                                                                31:0
-
-#define NV50C0_DECRYPTION_GET_SESSION_KEY(j)                                                      (0x0208+(j)*16)
-#define NV50C0_DECRYPTION_GET_SESSION_KEY_V                                                                  31:0
-
-#define NV50C0_DECRYPTION_SET_ENCRYPTION(j)                                                       (0x020c+(j)*16)
-#define NV50C0_DECRYPTION_SET_ENCRYPTION_V                                                                   31:0
-
-#define NV50C0_SET_CTA_PROGRAM_A                                                                           0x0210
-#define NV50C0_SET_CTA_PROGRAM_A_OFFSET_UPPER                                                                 7:0
-
-#define NV50C0_SET_CTA_PROGRAM_B                                                                           0x0214
-#define NV50C0_SET_CTA_PROGRAM_B_OFFSET_LOWER                                                                31:0
-
-#define NV50C0_SET_SHADER_THREAD_STACK_A                                                                   0x0218
-#define NV50C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER                                                         7:0
-
-#define NV50C0_SET_SHADER_THREAD_STACK_B                                                                   0x021c
-#define NV50C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER                                                        31:0
-
-#define NV50C0_SET_SHADER_THREAD_STACK_C                                                                   0x0220
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE                                                                 3:0
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__0                                                       0x00000000
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1                                                       0x00000001
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2                                                       0x00000002
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4                                                       0x00000003
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__8                                                       0x00000004
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__16                                                      0x00000005
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__32                                                      0x00000006
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__64                                                      0x00000007
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__128                                                     0x00000008
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__256                                                     0x00000009
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__512                                                     0x0000000A
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1024                                                    0x0000000B
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2048                                                    0x0000000C
-#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4096                                                    0x0000000D
-
-#define NV50C0_SET_API_CALL_LIMIT                                                                          0x0224
-#define NV50C0_SET_API_CALL_LIMIT_CTA                                                                         3:0
-#define NV50C0_SET_API_CALL_LIMIT_CTA__0                                                               0x00000000
-#define NV50C0_SET_API_CALL_LIMIT_CTA__1                                                               0x00000001
-#define NV50C0_SET_API_CALL_LIMIT_CTA__2                                                               0x00000002
-#define NV50C0_SET_API_CALL_LIMIT_CTA__4                                                               0x00000003
-#define NV50C0_SET_API_CALL_LIMIT_CTA__8                                                               0x00000004
-#define NV50C0_SET_API_CALL_LIMIT_CTA__16                                                              0x00000005
-#define NV50C0_SET_API_CALL_LIMIT_CTA__32                                                              0x00000006
-#define NV50C0_SET_API_CALL_LIMIT_CTA__64                                                              0x00000007
-#define NV50C0_SET_API_CALL_LIMIT_CTA__128                                                             0x00000008
-#define NV50C0_SET_API_CALL_LIMIT_CTA_NO_CHECK                                                         0x0000000F
-
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL                                                                 0x0228
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                             0:0
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                0x00000000
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                 0x00000001
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY                                         7:4
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY                                     11:8
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY                                       15:12
-#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY                                    19:16
-
-#define NV50C0_SET_TEX_SAMPLER_POOL_A                                                                      0x022c
-#define NV50C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NV50C0_SET_TEX_SAMPLER_POOL_B                                                                      0x0230
-#define NV50C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NV50C0_SET_TEX_SAMPLER_POOL_C                                                                      0x0234
-#define NV50C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NV50C0_LOAD_CONSTANT_SELECTOR                                                                      0x0238
-#define NV50C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX                                                             7:0
-#define NV50C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX                                                         23:8
-
-#define NV50C0_LOAD_CONSTANT(i)                                                                    (0x023c+(i)*4)
-#define NV50C0_LOAD_CONSTANT_V                                                                               31:0
-
-#define NV50C0_INVALIDATE_SAMPLER_CACHE                                                                    0x027c
-#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NV50C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x0280
-#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NV50C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0288
-#define NV50C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NV50C0_TEST_FOR_COMPUTE                                                                            0x028c
-#define NV50C0_TEST_FOR_COMPUTE_V                                                                            31:0
-
-#define NV50C0_SET_SHADER_SCHEDULING                                                                       0x0290
-#define NV50C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
-#define NV50C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
-#define NV50C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
-
-#define NV50C0_SET_SHADER_THREAD_MEMORY_A                                                                  0x0294
-#define NV50C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER                                                        7:0
-
-#define NV50C0_SET_SHADER_THREAD_MEMORY_B                                                                  0x0298
-#define NV50C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER                                                       31:0
-
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C                                                                  0x029c
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE                                                                3:0
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0                                                      0x00000000
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1                                                      0x00000001
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2                                                      0x00000002
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4                                                      0x00000003
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8                                                      0x00000004
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16                                                     0x00000005
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32                                                     0x00000006
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64                                                     0x00000007
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128                                                    0x00000008
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256                                                    0x00000009
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512                                                    0x0000000A
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024                                                   0x0000000B
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048                                                   0x0000000C
-#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096                                                   0x0000000D
-
-#define NV50C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
-#define NV50C0_SET_WORK_DISTRIBUTION_V                                                                        3:0
-#define NV50C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY                                                 0x00000000
-#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC                                                    0x00000001
-#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC                                                    0x00000002
-#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED                                                      0x00000003
-#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED                                                      0x00000004
-#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC                                               0x00000005
-#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC                                               0x00000006
-#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED                                                 0x00000007
-#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED                                                 0x00000008
-
-#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A                                                                0x02a4
-#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER                                                      7:0
-
-#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B                                                                0x02a8
-#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER                                                     31:0
-
-#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C                                                                0x02ac
-#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE                                                             15:0
-#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY                                                           23:16
-
-#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL                                                               0x02b0
-#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK                                                      0:0
-#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE                                         0x00000000
-#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE                                          0x00000001
-#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK                                                     31:1
-
-#define NV50C0_SET_CTA_RESOURCE_ALLOCATION                                                                 0x02b4
-#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT                                                      15:0
-#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT                                                    23:16
-
-#define NV50C0_SET_CTA_THREAD_CONTROL                                                                      0x02b8
-#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH                                                     0:0
-#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE                                        0x00000000
-#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE                                         0x00000001
-
-#define NV50C0_SET_PHASE_ID_CONTROL                                                                        0x02bc
-#define NV50C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE                                                               2:0
-#define NV50C0_SET_PHASE_ID_CONTROL_LOCK_PHASE                                                                6:4
-
-#define NV50C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
-#define NV50C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
-
-#define NV50C0_SET_TEX_HEADER_POOL_A                                                                       0x02c4
-#define NV50C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NV50C0_SET_TEX_HEADER_POOL_B                                                                       0x02c8
-#define NV50C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NV50C0_SET_TEX_HEADER_POOL_C                                                                       0x02cc
-#define NV50C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x02d0+(i)*4)
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i)                                           (0x02e0+(i)*4)
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE                                                    0:0
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK                                                   6:4
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE                                        0x00000000
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS                                        0x00000001
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM                                        0x00000002
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC                                        0x00000003
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP                                        0x00000004
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU                                        0x00000005
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC                                                   23:8
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT                                                 31:24
-
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x02f0
-#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               3:0
-
-#define NV50C0_RESET_CTA_TRACKING_RAM                                                                      0x02f4
-#define NV50C0_RESET_CTA_TRACKING_RAM_V                                                                      31:0
-
-#define NV50C0_INITIALIZE                                                                                  0x02f8
-#define NV50C0_INITIALIZE_INIT_CTA_SHAPE                                                                      0:0
-#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_FALSE                                                         0x00000000
-#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_TRUE                                                          0x00000001
-
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE                                                           0x02fc
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM                                              2:0
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1                                    0x00000000
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2                                    0x00000001
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4                                    0x00000002
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8                                    0x00000003
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16                                   0x00000004
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                0x00000007
-
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL                                                   0x0300
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V                                                    2:0
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                            0x00000000
-#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX                                  0x00000001
-
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE                                                            0x0304
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM                                               2:0
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1                                     0x00000000
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2                                     0x00000001
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4                                     0x00000002
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8                                     0x00000003
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16                                    0x00000004
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                 0x00000007
-
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL                                                    0x0308
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V                                                     2:0
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                             0x00000000
-#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX                                   0x00000001
-
-#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS                                                                0x030c
-#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA                                                               0:0
-#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE                                                  0x00000000
-#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE                                                   0x00000001
-
-#define NV50C0_SET_REPORT_SEMAPHORE_A                                                                      0x0310
-#define NV50C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NV50C0_SET_REPORT_SEMAPHORE_B                                                                      0x0314
-#define NV50C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NV50C0_SET_REPORT_SEMAPHORE_C                                                                      0x0318
-#define NV50C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NV50C0_SET_REPORT_SEMAPHORE_D                                                                      0x031c
-#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED                                                 0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE                                                                 2:2
-#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED                                                   0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE                                                                 3:3
-#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED                                                   0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION                                                       7:4
-#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED                                         0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON                                                              8:8
-#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED                                                0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                           9:9
-#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT                                                                14:10
-#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED                                                    0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        15:15
-#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-
-#define NV50C0_SET_LAUNCH_ENABLE_A                                                                         0x0320
-#define NV50C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NV50C0_SET_LAUNCH_ENABLE_B                                                                         0x0324
-#define NV50C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NV50C0_SET_LAUNCH_ENABLE_C                                                                         0x0328
-#define NV50C0_SET_LAUNCH_ENABLE_C_MODE                                                                       2:0
-#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE                                                           0x032c
-#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE                                                      31:0
-#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE                                          0x00000000
-#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE                                           0x00000001
-
-#define NV50C0_PIPE_NOP                                                                                    0x0330
-#define NV50C0_PIPE_NOP_V                                                                                    31:0
-
-#define NV50C0_SET_SPARE00                                                                                 0x0340
-#define NV50C0_SET_SPARE00_V                                                                                 31:0
-
-#define NV50C0_SET_SPARE01                                                                                 0x0344
-#define NV50C0_SET_SPARE01_V                                                                                 31:0
-
-#define NV50C0_SET_SPARE02                                                                                 0x0348
-#define NV50C0_SET_SPARE02_V                                                                                 31:0
-
-#define NV50C0_SET_SPARE03                                                                                 0x034c
-#define NV50C0_SET_SPARE03_V                                                                                 31:0
-
-#define NV50C0_SET_GLOBAL_COLOR_KEY                                                                        0x0358
-#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                   31:0
-#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
-#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
-
-#define NV50C0_RESET_REF_COUNT                                                                             0x035c
-#define NV50C0_RESET_REF_COUNT_REF_CNT                                                                        3:0
-
-#define NV50C0_WAIT_REF_COUNT                                                                              0x0360
-#define NV50C0_WAIT_REF_COUNT_COMPARE                                                                         7:4
-#define NV50C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT                                                   0x00000000
-#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL                                                      0x00000001
-#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND                                                  0x00000002
-#define NV50C0_WAIT_REF_COUNT_REF_CNT                                                                        11:8
-
-#define NV50C0_SET_REF_COUNT_VALUE                                                                         0x0364
-#define NV50C0_SET_REF_COUNT_VALUE_V                                                                         31:0
-
-#define NV50C0_LAUNCH                                                                                      0x0368
-#define NV50C0_LAUNCH_V                                                                                      31:0
-
-#define NV50C0_SET_LAUNCH_ID                                                                               0x036c
-#define NV50C0_SET_LAUNCH_ID_REF_CNT                                                                          3:0
-
-#define NV50C0_SET_LAUNCH_CONTROL                                                                          0x0370
-#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH                                                                      7:0
-#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH                                                 0x00000000
-#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH                                                   0x00000001
-
-#define NV50C0_SET_PARAMETER_SIZE                                                                          0x0374
-#define NV50C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX                                                           7:0
-#define NV50C0_SET_PARAMETER_SIZE_COUNT                                                                      15:8
-
-#define NV50C0_SET_SAMPLER_BINDING                                                                         0x0378
-#define NV50C0_SET_SAMPLER_BINDING_V                                                                          0:0
-#define NV50C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
-#define NV50C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
-
-#define NV50C0_SET_SHADER_CONTROL                                                                          0x037c
-#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
-#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
-#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
-#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
-#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
-#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
-
-#define NV50C0_INVALIDATE_SHADER_CACHE                                                                     0x0380
-#define NV50C0_INVALIDATE_SHADER_CACHE_V                                                                      1:0
-#define NV50C0_INVALIDATE_SHADER_CACHE_V_ALL                                                           0x00000000
-#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1                                                            0x00000001
-#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_DATA                                                       0x00000002
-#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION                                                0x00000003
-
-#define NV50C0_SET_RASTER_CONTROL                                                                          0x0384
-#define NV50C0_SET_RASTER_CONTROL_PROGRAM                                                                     7:0
-#define NV50C0_SET_RASTER_CONTROL_PROGRAM_DISABLE                                                      0x00000000
-#define NV50C0_SET_RASTER_CONTROL_FIXED                                                                      15:8
-#define NV50C0_SET_RASTER_CONTROL_FIXED_DISABLE                                                        0x00000000
-#define NV50C0_SET_RASTER_CONTROL_FIXED_SIMPLE                                                         0x00000001
-#define NV50C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED                                                 0x00000002
-#define NV50C0_SET_RASTER_CONTROL_DECRYPTION                                                                23:16
-#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE                                                   0x00000000
-#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE                                                    0x00000001
-
-#define NV50C0_SET_CTA_FLAGS                                                                               0x0388
-#define NV50C0_SET_CTA_FLAGS_V                                                                               15:0
-
-#define NV50C0_SET_CTA_RASTER_SIZE                                                                         0x03a4
-#define NV50C0_SET_CTA_RASTER_SIZE_WIDTH                                                                     15:0
-#define NV50C0_SET_CTA_RASTER_SIZE_HEIGHT                                                                   31:16
-
-#define NV50C0_SET_CTA_GRF_SIZE                                                                            0x03a8
-#define NV50C0_SET_CTA_GRF_SIZE_V                                                                            31:0
-
-#define NV50C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
-#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
-#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
-
-#define NV50C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
-#define NV50C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
-
-#define NV50C0_SET_CTA_PROGRAM_START                                                                       0x03b4
-#define NV50C0_SET_CTA_PROGRAM_START_OFFSET                                                                  23:0
-
-#define NV50C0_SET_CTA_REGISTER_ALLOCATION                                                                 0x03b8
-#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V                                                                 31:0
-#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THICK                                                     0x00000001
-#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THIN                                                      0x00000002
-
-#define NV50C0_SET_CTA_TEXTURE                                                                             0x03bc
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS                                                            3:0
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                                  0x00000000
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                                  0x00000001
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                                  0x00000002
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                                  0x00000003
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                                 0x00000004
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS                                                             7:4
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1                                                   0x00000000
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2                                                   0x00000001
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4                                                   0x00000002
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8                                                   0x00000003
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16                                                  0x00000004
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32                                                  0x00000005
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64                                                  0x00000006
-#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128                                                 0x00000007
-
-#define NV50C0_BIND_CTA_TEXTURE_SAMPLER                                                                    0x03c0
-#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID                                                                 0:0
-#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE                                                    0x00000000
-#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE                                                     0x00000001
-#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                         11:4
-#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_INDEX                                                               24:12
-
-#define NV50C0_BIND_CTA_TEXTURE_HEADER                                                                     0x03c4
-#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID                                                                  0:0
-#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE                                                     0x00000000
-#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE                                                      0x00000001
-#define NV50C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT                                                           8:1
-#define NV50C0_BIND_CTA_TEXTURE_HEADER_INDEX                                                                 30:9
-
-#define NV50C0_BIND_CONSTANT_BUFFER                                                                        0x03c8
-#define NV50C0_BIND_CONSTANT_BUFFER_VALID                                                                     3:0
-#define NV50C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
-#define NV50C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
-#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE                                                               7:4
-#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA                                                    0x00000000
-#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              11:8
-#define NV50C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY                                                             19:12
-
-#define NV50C0_PREFETCH_TEXTURE_SAMPLER                                                                    0x03cc
-#define NV50C0_PREFETCH_TEXTURE_SAMPLER_INDEX                                                                21:0
-
-#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x03d0
-#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           5:4
-#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
-#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY                                            0x00000001
-#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2                                          0x00000002
-
-#define NV50C0_SET_SHADER_EXCEPTIONS                                                                       0x03ec
-#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NV50C0_SET_GLOBAL_MEM_A(j)                                                                (0x0400+(j)*32)
-#define NV50C0_SET_GLOBAL_MEM_A_OFFSET_UPPER                                                                  7:0
-
-#define NV50C0_SET_GLOBAL_MEM_B(j)                                                                (0x0404+(j)*32)
-#define NV50C0_SET_GLOBAL_MEM_B_OFFSET_LOWER                                                                 31:0
-
-#define NV50C0_SET_GLOBAL_MEM_SIZE(j)                                                             (0x0408+(j)*32)
-#define NV50C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH                                                               31:0
-
-#define NV50C0_SET_GLOBAL_MEM_LIMIT(j)                                                            (0x040c+(j)*32)
-#define NV50C0_SET_GLOBAL_MEM_LIMIT_MAX                                                                      31:0
-
-#define NV50C0_SET_GLOBAL_MEM_FORMAT(j)                                                           (0x0410+(j)*32)
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT                                                               0:0
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR                                            0x00000000
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH                                                  0x00000001
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH                                                       7:4
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB                                        0x00000000
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT                                                     11:8
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB                                       0x00000000
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS                                      0x00000001
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS                                     0x00000002
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS                                    0x00000003
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS                                  0x00000004
-#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS                                0x00000005
-
-#define NV50C0_PARAMETER(i)                                                                        (0x0600+(i)*4)
-#define NV50C0_PARAMETER_V                                                                                   31:0
-
-#define NV50C0_SET_SPARE_NOOP00                                                                            0x0700
-#define NV50C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP01                                                                            0x0704
-#define NV50C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP02                                                                            0x0708
-#define NV50C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP03                                                                            0x070c
-#define NV50C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP04                                                                            0x0710
-#define NV50C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP05                                                                            0x0714
-#define NV50C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP06                                                                            0x0718
-#define NV50C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP07                                                                            0x071c
-#define NV50C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP08                                                                            0x0720
-#define NV50C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP09                                                                            0x0724
-#define NV50C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP10                                                                            0x0728
-#define NV50C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP11                                                                            0x072c
-#define NV50C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP12                                                                            0x0730
-#define NV50C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP13                                                                            0x0734
-#define NV50C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP14                                                                            0x0738
-#define NV50C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NV50C0_SET_SPARE_NOOP15                                                                            0x073c
-#define NV50C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#endif /* _cl_nv50_compute_h_ */
diff --git a/Compute-Class-Methods/cl85c0.h b/Compute-Class-Methods/cl85c0.h
deleted file mode 100644
index 4234fd0..0000000
--- a/Compute-Class-Methods/cl85c0.h
+++ /dev/null
@@ -1,747 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_gt214_compute_h_
-#define _cl_gt214_compute_h_
-
-/* This file is generated - do not edit. */
-
-#include "nvtypes.h"
-
-#define GT214_COMPUTE    0x85C0
-
-typedef volatile struct _cl85c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 Notify;
-    NvU32 Reserved_0x108[0x2];
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0xB];
-    NvU32 PmTrigger;
-    NvU32 Reserved_0x144[0xF];
-    NvU32 SetContextDmaNotify;
-    NvU32 Reserved_0x184[0x7];
-    NvU32 SetCtxDmaGlobalMem;
-    NvU32 SetCtxDmaSemaphore;
-    NvU32 Reserved_0x1A8[0x4];
-    NvU32 SetCtxDmaShaderThreadMemory;
-    NvU32 SetCtxDmaShaderThreadStack;
-    NvU32 SetCtxDmaShaderProgram;
-    NvU32 SetCtxDmaTextureSampler;
-    NvU32 SetCtxDmaTextureHeaders;
-    NvU32 SetCtxDmaTexture;
-    NvU32 Reserved_0x1D0[0xC];
-    struct {
-        NvU32 Control;
-        NvU32 QuerySessionKey;
-        NvU32 GetSessionKey;
-        NvU32 SetEncryption;
-    } Decryption[0x1];
-    NvU32 SetCtaProgramA;
-    NvU32 SetCtaProgramB;
-    NvU32 SetShaderThreadStackA;
-    NvU32 SetShaderThreadStackB;
-    NvU32 SetShaderThreadStackC;
-    NvU32 SetApiCallLimit;
-    NvU32 SetShaderL1CacheControl;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 LoadConstantSelector;
-    NvU32 LoadConstant[0x10];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 Reserved_0x284[0x1];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 TestForCompute;
-    NvU32 SetShaderScheduling;
-    NvU32 SetShaderThreadMemoryA;
-    NvU32 SetShaderThreadMemoryB;
-    NvU32 SetShaderThreadMemoryC;
-    NvU32 SetWorkDistribution;
-    NvU32 LoadConstantBufferTableA;
-    NvU32 LoadConstantBufferTableB;
-    NvU32 LoadConstantBufferTableC;
-    NvU32 SetShaderErrorTrapControl;
-    NvU32 SetCtaResourceAllocation;
-    NvU32 SetCtaThreadControl;
-    NvU32 SetPhaseIdControl;
-    NvU32 SetCtaRegisterCount;
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 SetShaderPerformanceCounterValue[0x4];
-    NvU32 SetShaderPerformanceCounterControl[0x4];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 ResetCtaTrackingRam;
-    NvU32 Initialize;
-    NvU32 SetShaderThreadMemoryThrottle;
-    NvU32 SetShaderThreadMemoryThrottleControl;
-    NvU32 SetShaderThreadStackThrottle;
-    NvU32 SetShaderThreadStackThrottleControl;
-    NvU32 PrefetchShaderInstructions;
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 SetLaunchEnableA;
-    NvU32 SetLaunchEnableB;
-    NvU32 SetLaunchEnableC;
-    NvU32 SetCubemapAddressModeOverride;
-    NvU32 PipeNop;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop10;
-    NvU32 SetGlobalColorKey;
-    NvU32 ResetRefCount;
-    NvU32 WaitRefCount;
-    NvU32 SetRefCountValue;
-    NvU32 Launch;
-    NvU32 SetLaunchId;
-    NvU32 SetLaunchControl;
-    NvU32 SetParameterSize;
-    NvU32 SetSamplerBinding;
-    NvU32 SetShaderControl;
-    NvU32 InvalidateShaderCache;
-    NvU32 SetRasterControl;
-    NvU32 SetCtaFlags;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop15;
-    NvU32 SetSpareNoop11;
-    NvU32 SetSpare02;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpare03;
-    NvU32 SetCtaRasterSize;
-    NvU32 SetCtaGrfSize;
-    NvU32 SetCtaThreadDimensionA;
-    NvU32 SetCtaThreadDimensionB;
-    NvU32 SetCtaProgramStart;
-    NvU32 SetCtaRegisterAllocation;
-    NvU32 SetCtaTexture;
-    NvU32 BindCtaTextureSampler;
-    NvU32 BindCtaTextureHeader;
-    NvU32 BindConstantBuffer;
-    NvU32 PrefetchTextureSampler;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop12;
-    NvU32 SetCubemapInterFaceFiltering;
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x3F0[0x4];
-    struct {
-        NvU32 A;
-        NvU32 B;
-        NvU32 Size;
-        NvU32 Limit;
-        NvU32 Format;
-        NvU32 Reserved_0x14[0x3];
-    } SetGlobalMem[0x10];
-    NvU32 Parameter[0x40];
-} gt214_compute_t;
-
-
-#define NV85C0_SET_OBJECT                                                                                  0x0000
-#define NV85C0_SET_OBJECT_POINTER                                                                            15:0
-
-#define NV85C0_NO_OPERATION                                                                                0x0100
-#define NV85C0_NO_OPERATION_V                                                                                31:0
-
-#define NV85C0_NOTIFY                                                                                      0x0104
-#define NV85C0_NOTIFY_TYPE                                                                                   31:0
-#define NV85C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NV85C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NV85C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NV85C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NV85C0_PM_TRIGGER                                                                                  0x0140
-#define NV85C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NV85C0_SET_CONTEXT_DMA_NOTIFY                                                                      0x0180
-#define NV85C0_SET_CONTEXT_DMA_NOTIFY_HANDLE                                                                 31:0
-
-#define NV85C0_SET_CTX_DMA_GLOBAL_MEM                                                                      0x01a0
-#define NV85C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE                                                                 31:0
-
-#define NV85C0_SET_CTX_DMA_SEMAPHORE                                                                       0x01a4
-#define NV85C0_SET_CTX_DMA_SEMAPHORE_HANDLE                                                                  31:0
-
-#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY                                                            0x01b8
-#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE                                                       31:0
-
-#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK                                                             0x01bc
-#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE                                                        31:0
-
-#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM                                                                  0x01c0
-#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE                                                             31:0
-
-#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER                                                                 0x01c4
-#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE                                                            31:0
-
-#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS                                                                 0x01c8
-#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE                                                            31:0
-
-#define NV85C0_SET_CTX_DMA_TEXTURE                                                                         0x01cc
-#define NV85C0_SET_CTX_DMA_TEXTURE_HANDLE                                                                    31:0
-
-#define NV85C0_DECRYPTION_CONTROL(j)                                                              (0x0200+(j)*16)
-#define NV85C0_DECRYPTION_CONTROL_ALGORITHM                                                                  15:0
-#define NV85C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE                                            0x00000000
-#define NV85C0_DECRYPTION_CONTROL_KEY_COUNT                                                                 23:16
-
-#define NV85C0_DECRYPTION_QUERY_SESSION_KEY(j)                                                    (0x0204+(j)*16)
-#define NV85C0_DECRYPTION_QUERY_SESSION_KEY_V                                                                31:0
-
-#define NV85C0_DECRYPTION_GET_SESSION_KEY(j)                                                      (0x0208+(j)*16)
-#define NV85C0_DECRYPTION_GET_SESSION_KEY_V                                                                  31:0
-
-#define NV85C0_DECRYPTION_SET_ENCRYPTION(j)                                                       (0x020c+(j)*16)
-#define NV85C0_DECRYPTION_SET_ENCRYPTION_V                                                                   31:0
-
-#define NV85C0_SET_CTA_PROGRAM_A                                                                           0x0210
-#define NV85C0_SET_CTA_PROGRAM_A_OFFSET_UPPER                                                                 7:0
-
-#define NV85C0_SET_CTA_PROGRAM_B                                                                           0x0214
-#define NV85C0_SET_CTA_PROGRAM_B_OFFSET_LOWER                                                                31:0
-
-#define NV85C0_SET_SHADER_THREAD_STACK_A                                                                   0x0218
-#define NV85C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER                                                         7:0
-
-#define NV85C0_SET_SHADER_THREAD_STACK_B                                                                   0x021c
-#define NV85C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER                                                        31:0
-
-#define NV85C0_SET_SHADER_THREAD_STACK_C                                                                   0x0220
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE                                                                 3:0
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__0                                                       0x00000000
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1                                                       0x00000001
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2                                                       0x00000002
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4                                                       0x00000003
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__8                                                       0x00000004
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__16                                                      0x00000005
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__32                                                      0x00000006
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__64                                                      0x00000007
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__128                                                     0x00000008
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__256                                                     0x00000009
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__512                                                     0x0000000A
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1024                                                    0x0000000B
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2048                                                    0x0000000C
-#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4096                                                    0x0000000D
-
-#define NV85C0_SET_API_CALL_LIMIT                                                                          0x0224
-#define NV85C0_SET_API_CALL_LIMIT_CTA                                                                         3:0
-#define NV85C0_SET_API_CALL_LIMIT_CTA__0                                                               0x00000000
-#define NV85C0_SET_API_CALL_LIMIT_CTA__1                                                               0x00000001
-#define NV85C0_SET_API_CALL_LIMIT_CTA__2                                                               0x00000002
-#define NV85C0_SET_API_CALL_LIMIT_CTA__4                                                               0x00000003
-#define NV85C0_SET_API_CALL_LIMIT_CTA__8                                                               0x00000004
-#define NV85C0_SET_API_CALL_LIMIT_CTA__16                                                              0x00000005
-#define NV85C0_SET_API_CALL_LIMIT_CTA__32                                                              0x00000006
-#define NV85C0_SET_API_CALL_LIMIT_CTA__64                                                              0x00000007
-#define NV85C0_SET_API_CALL_LIMIT_CTA__128                                                             0x00000008
-#define NV85C0_SET_API_CALL_LIMIT_CTA_NO_CHECK                                                         0x0000000F
-
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL                                                                 0x0228
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                             0:0
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                0x00000000
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                 0x00000001
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY                                         7:4
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY                                     11:8
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY                                       15:12
-#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY                                    19:16
-
-#define NV85C0_SET_TEX_SAMPLER_POOL_A                                                                      0x022c
-#define NV85C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NV85C0_SET_TEX_SAMPLER_POOL_B                                                                      0x0230
-#define NV85C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NV85C0_SET_TEX_SAMPLER_POOL_C                                                                      0x0234
-#define NV85C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NV85C0_LOAD_CONSTANT_SELECTOR                                                                      0x0238
-#define NV85C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX                                                             7:0
-#define NV85C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX                                                         23:8
-
-#define NV85C0_LOAD_CONSTANT(i)                                                                    (0x023c+(i)*4)
-#define NV85C0_LOAD_CONSTANT_V                                                                               31:0
-
-#define NV85C0_INVALIDATE_SAMPLER_CACHE                                                                    0x027c
-#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NV85C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x0280
-#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NV85C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0288
-#define NV85C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NV85C0_TEST_FOR_COMPUTE                                                                            0x028c
-#define NV85C0_TEST_FOR_COMPUTE_V                                                                            31:0
-
-#define NV85C0_SET_SHADER_SCHEDULING                                                                       0x0290
-#define NV85C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
-#define NV85C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
-#define NV85C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
-
-#define NV85C0_SET_SHADER_THREAD_MEMORY_A                                                                  0x0294
-#define NV85C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER                                                        7:0
-
-#define NV85C0_SET_SHADER_THREAD_MEMORY_B                                                                  0x0298
-#define NV85C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER                                                       31:0
-
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C                                                                  0x029c
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE                                                                3:0
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0                                                      0x00000000
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1                                                      0x00000001
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2                                                      0x00000002
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4                                                      0x00000003
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8                                                      0x00000004
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16                                                     0x00000005
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32                                                     0x00000006
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64                                                     0x00000007
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128                                                    0x00000008
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256                                                    0x00000009
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512                                                    0x0000000A
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024                                                   0x0000000B
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048                                                   0x0000000C
-#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096                                                   0x0000000D
-
-#define NV85C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
-#define NV85C0_SET_WORK_DISTRIBUTION_V                                                                        3:0
-#define NV85C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY                                                 0x00000000
-#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC                                                    0x00000001
-#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC                                                    0x00000002
-#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED                                                      0x00000003
-#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED                                                      0x00000004
-#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC                                               0x00000005
-#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC                                               0x00000006
-#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED                                                 0x00000007
-#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED                                                 0x00000008
-
-#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A                                                                0x02a4
-#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER                                                      7:0
-
-#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B                                                                0x02a8
-#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER                                                     31:0
-
-#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C                                                                0x02ac
-#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE                                                             15:0
-#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY                                                           23:16
-
-#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL                                                               0x02b0
-#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK                                                      0:0
-#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE                                         0x00000000
-#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE                                          0x00000001
-#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK                                                     31:1
-
-#define NV85C0_SET_CTA_RESOURCE_ALLOCATION                                                                 0x02b4
-#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT                                                      15:0
-#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT                                                    23:16
-
-#define NV85C0_SET_CTA_THREAD_CONTROL                                                                      0x02b8
-#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH                                                     0:0
-#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE                                        0x00000000
-#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE                                         0x00000001
-
-#define NV85C0_SET_PHASE_ID_CONTROL                                                                        0x02bc
-#define NV85C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE                                                               2:0
-#define NV85C0_SET_PHASE_ID_CONTROL_LOCK_PHASE                                                                6:4
-
-#define NV85C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
-#define NV85C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
-
-#define NV85C0_SET_TEX_HEADER_POOL_A                                                                       0x02c4
-#define NV85C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NV85C0_SET_TEX_HEADER_POOL_B                                                                       0x02c8
-#define NV85C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NV85C0_SET_TEX_HEADER_POOL_C                                                                       0x02cc
-#define NV85C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x02d0+(i)*4)
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i)                                           (0x02e0+(i)*4)
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE                                                    0:0
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK                                                   6:4
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE                                        0x00000000
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS                                        0x00000001
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM                                        0x00000002
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC                                        0x00000003
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP                                        0x00000004
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU                                        0x00000005
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC                                                   23:8
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT                                                 31:24
-
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x02f0
-#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               3:0
-
-#define NV85C0_RESET_CTA_TRACKING_RAM                                                                      0x02f4
-#define NV85C0_RESET_CTA_TRACKING_RAM_V                                                                      31:0
-
-#define NV85C0_INITIALIZE                                                                                  0x02f8
-#define NV85C0_INITIALIZE_INIT_CTA_SHAPE                                                                      0:0
-#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_FALSE                                                         0x00000000
-#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_TRUE                                                          0x00000001
-
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE                                                           0x02fc
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM                                              2:0
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1                                    0x00000000
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2                                    0x00000001
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4                                    0x00000002
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8                                    0x00000003
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16                                   0x00000004
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__24                                   0x00000005
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                0x00000007
-
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL                                                   0x0300
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V                                                    2:0
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                            0x00000000
-#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX                                  0x00000001
-
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE                                                            0x0304
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM                                               2:0
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1                                     0x00000000
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2                                     0x00000001
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4                                     0x00000002
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8                                     0x00000003
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16                                    0x00000004
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__24                                    0x00000005
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                 0x00000007
-
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL                                                    0x0308
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V                                                     2:0
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                             0x00000000
-#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX                                   0x00000001
-
-#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS                                                                0x030c
-#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA                                                               0:0
-#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE                                                  0x00000000
-#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE                                                   0x00000001
-
-#define NV85C0_SET_REPORT_SEMAPHORE_A                                                                      0x0310
-#define NV85C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NV85C0_SET_REPORT_SEMAPHORE_B                                                                      0x0314
-#define NV85C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NV85C0_SET_REPORT_SEMAPHORE_C                                                                      0x0318
-#define NV85C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NV85C0_SET_REPORT_SEMAPHORE_D                                                                      0x031c
-#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED                                                 0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE                                                                 2:2
-#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED                                                   0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE                                                                 3:3
-#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED                                                   0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION                                                       7:4
-#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED                                         0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON                                                              8:8
-#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED                                                0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                           9:9
-#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT                                                                14:10
-#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED                                                    0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        15:15
-#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-
-#define NV85C0_SET_LAUNCH_ENABLE_A                                                                         0x0320
-#define NV85C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NV85C0_SET_LAUNCH_ENABLE_B                                                                         0x0324
-#define NV85C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NV85C0_SET_LAUNCH_ENABLE_C                                                                         0x0328
-#define NV85C0_SET_LAUNCH_ENABLE_C_MODE                                                                       2:0
-#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE                                                           0x032c
-#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE                                                      31:0
-#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE                                          0x00000000
-#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE                                           0x00000001
-
-#define NV85C0_PIPE_NOP                                                                                    0x0330
-#define NV85C0_PIPE_NOP_V                                                                                    31:0
-
-#define NV85C0_SET_SPARE_NOOP13                                                                            0x0334
-#define NV85C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP09                                                                            0x0338
-#define NV85C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP14                                                                            0x033c
-#define NV85C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP00                                                                            0x0340
-#define NV85C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP01                                                                            0x0344
-#define NV85C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NV85C0_SET_SPARE00                                                                                 0x0348
-#define NV85C0_SET_SPARE00_V                                                                                 31:0
-
-#define NV85C0_SET_SPARE01                                                                                 0x034c
-#define NV85C0_SET_SPARE01_V                                                                                 31:0
-
-#define NV85C0_SET_SPARE_NOOP05                                                                            0x0350
-#define NV85C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP10                                                                            0x0354
-#define NV85C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NV85C0_SET_GLOBAL_COLOR_KEY                                                                        0x0358
-#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                   31:0
-#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
-#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
-
-#define NV85C0_RESET_REF_COUNT                                                                             0x035c
-#define NV85C0_RESET_REF_COUNT_REF_CNT                                                                        3:0
-
-#define NV85C0_WAIT_REF_COUNT                                                                              0x0360
-#define NV85C0_WAIT_REF_COUNT_COMPARE                                                                         7:4
-#define NV85C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT                                                   0x00000000
-#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL                                                      0x00000001
-#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND                                                  0x00000002
-#define NV85C0_WAIT_REF_COUNT_REF_CNT                                                                        11:8
-
-#define NV85C0_SET_REF_COUNT_VALUE                                                                         0x0364
-#define NV85C0_SET_REF_COUNT_VALUE_V                                                                         31:0
-
-#define NV85C0_LAUNCH                                                                                      0x0368
-#define NV85C0_LAUNCH_V                                                                                      31:0
-
-#define NV85C0_SET_LAUNCH_ID                                                                               0x036c
-#define NV85C0_SET_LAUNCH_ID_REF_CNT                                                                          3:0
-
-#define NV85C0_SET_LAUNCH_CONTROL                                                                          0x0370
-#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH                                                                      7:0
-#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH                                                 0x00000000
-#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH                                                   0x00000001
-
-#define NV85C0_SET_PARAMETER_SIZE                                                                          0x0374
-#define NV85C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX                                                           7:0
-#define NV85C0_SET_PARAMETER_SIZE_COUNT                                                                      15:8
-
-#define NV85C0_SET_SAMPLER_BINDING                                                                         0x0378
-#define NV85C0_SET_SAMPLER_BINDING_V                                                                          0:0
-#define NV85C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
-#define NV85C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
-
-#define NV85C0_SET_SHADER_CONTROL                                                                          0x037c
-#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
-#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
-#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
-#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
-#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
-#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
-
-#define NV85C0_INVALIDATE_SHADER_CACHE                                                                     0x0380
-#define NV85C0_INVALIDATE_SHADER_CACHE_V                                                                      1:0
-#define NV85C0_INVALIDATE_SHADER_CACHE_V_ALL                                                           0x00000000
-#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1                                                            0x00000001
-#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_DATA                                                       0x00000002
-#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION                                                0x00000003
-
-#define NV85C0_SET_RASTER_CONTROL                                                                          0x0384
-#define NV85C0_SET_RASTER_CONTROL_PROGRAM                                                                     7:0
-#define NV85C0_SET_RASTER_CONTROL_PROGRAM_DISABLE                                                      0x00000000
-#define NV85C0_SET_RASTER_CONTROL_FIXED                                                                      15:8
-#define NV85C0_SET_RASTER_CONTROL_FIXED_DISABLE                                                        0x00000000
-#define NV85C0_SET_RASTER_CONTROL_FIXED_SIMPLE                                                         0x00000001
-#define NV85C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED                                                 0x00000002
-#define NV85C0_SET_RASTER_CONTROL_DECRYPTION                                                                23:16
-#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE                                                   0x00000000
-#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE                                                    0x00000001
-
-#define NV85C0_SET_CTA_FLAGS                                                                               0x0388
-#define NV85C0_SET_CTA_FLAGS_V                                                                               15:0
-
-#define NV85C0_SET_SPARE_NOOP06                                                                            0x038c
-#define NV85C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP15                                                                            0x0390
-#define NV85C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP11                                                                            0x0394
-#define NV85C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NV85C0_SET_SPARE02                                                                                 0x0398
-#define NV85C0_SET_SPARE02_V                                                                                 31:0
-
-#define NV85C0_SET_SPARE_NOOP02                                                                            0x039c
-#define NV85C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NV85C0_SET_SPARE03                                                                                 0x03a0
-#define NV85C0_SET_SPARE03_V                                                                                 31:0
-
-#define NV85C0_SET_CTA_RASTER_SIZE                                                                         0x03a4
-#define NV85C0_SET_CTA_RASTER_SIZE_WIDTH                                                                     15:0
-#define NV85C0_SET_CTA_RASTER_SIZE_HEIGHT                                                                   31:16
-
-#define NV85C0_SET_CTA_GRF_SIZE                                                                            0x03a8
-#define NV85C0_SET_CTA_GRF_SIZE_V                                                                            31:0
-
-#define NV85C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
-#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
-#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
-
-#define NV85C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
-#define NV85C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
-
-#define NV85C0_SET_CTA_PROGRAM_START                                                                       0x03b4
-#define NV85C0_SET_CTA_PROGRAM_START_OFFSET                                                                  23:0
-
-#define NV85C0_SET_CTA_REGISTER_ALLOCATION                                                                 0x03b8
-#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V                                                                 31:0
-#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THICK                                                     0x00000001
-#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THIN                                                      0x00000002
-
-#define NV85C0_SET_CTA_TEXTURE                                                                             0x03bc
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS                                                            3:0
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                                  0x00000000
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                                  0x00000001
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                                  0x00000002
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                                  0x00000003
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                                 0x00000004
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS                                                             7:4
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1                                                   0x00000000
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2                                                   0x00000001
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4                                                   0x00000002
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8                                                   0x00000003
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16                                                  0x00000004
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32                                                  0x00000005
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64                                                  0x00000006
-#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128                                                 0x00000007
-
-#define NV85C0_BIND_CTA_TEXTURE_SAMPLER                                                                    0x03c0
-#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID                                                                 0:0
-#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE                                                    0x00000000
-#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE                                                     0x00000001
-#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                         11:4
-#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_INDEX                                                               24:12
-
-#define NV85C0_BIND_CTA_TEXTURE_HEADER                                                                     0x03c4
-#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID                                                                  0:0
-#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE                                                     0x00000000
-#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE                                                      0x00000001
-#define NV85C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT                                                           8:1
-#define NV85C0_BIND_CTA_TEXTURE_HEADER_INDEX                                                                 30:9
-
-#define NV85C0_BIND_CONSTANT_BUFFER                                                                        0x03c8
-#define NV85C0_BIND_CONSTANT_BUFFER_VALID                                                                     3:0
-#define NV85C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
-#define NV85C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
-#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE                                                               7:4
-#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA                                                    0x00000000
-#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              11:8
-#define NV85C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY                                                             19:12
-
-#define NV85C0_PREFETCH_TEXTURE_SAMPLER                                                                    0x03cc
-#define NV85C0_PREFETCH_TEXTURE_SAMPLER_INDEX                                                                21:0
-
-#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x03d0
-#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           5:4
-#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
-#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY                                            0x00000001
-#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2                                          0x00000002
-
-#define NV85C0_SET_SPARE_NOOP03                                                                            0x03d4
-#define NV85C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP07                                                                            0x03d8
-#define NV85C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP04                                                                            0x03dc
-#define NV85C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP08                                                                            0x03e0
-#define NV85C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NV85C0_SET_SPARE_NOOP12                                                                            0x03e4
-#define NV85C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING                                                            0x03e8
-#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE                                                          1:0
-#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP                                          0x00000000
-#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP                                     0x00000001
-#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM                                    0x00000002
-#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM                                   0x00000003
-
-#define NV85C0_SET_SHADER_EXCEPTIONS                                                                       0x03ec
-#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NV85C0_SET_GLOBAL_MEM_A(j)                                                                (0x0400+(j)*32)
-#define NV85C0_SET_GLOBAL_MEM_A_OFFSET_UPPER                                                                  7:0
-
-#define NV85C0_SET_GLOBAL_MEM_B(j)                                                                (0x0404+(j)*32)
-#define NV85C0_SET_GLOBAL_MEM_B_OFFSET_LOWER                                                                 31:0
-
-#define NV85C0_SET_GLOBAL_MEM_SIZE(j)                                                             (0x0408+(j)*32)
-#define NV85C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH                                                               31:0
-
-#define NV85C0_SET_GLOBAL_MEM_LIMIT(j)                                                            (0x040c+(j)*32)
-#define NV85C0_SET_GLOBAL_MEM_LIMIT_MAX                                                                      31:0
-
-#define NV85C0_SET_GLOBAL_MEM_FORMAT(j)                                                           (0x0410+(j)*32)
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT                                                               0:0
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR                                            0x00000000
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH                                                  0x00000001
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH                                                       7:4
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB                                        0x00000000
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT                                                     11:8
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB                                       0x00000000
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS                                      0x00000001
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS                                     0x00000002
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS                                    0x00000003
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS                                  0x00000004
-#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS                                0x00000005
-
-#define NV85C0_PARAMETER(i)                                                                        (0x0600+(i)*4)
-#define NV85C0_PARAMETER_V                                                                                   31:0
-
-#endif /* _cl_gt214_compute_h_ */
diff --git a/Compute-Class-Methods/cl90c0.h b/Compute-Class-Methods/cl90c0.h
deleted file mode 100644
index d49ab75..0000000
--- a/Compute-Class-Methods/cl90c0.h
+++ /dev/null
@@ -1,1033 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_fermi_compute_a_h_
-#define _cl_fermi_compute_a_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../class/bin/sw_header.pl fermi_compute_a */
-
-#include "nvtypes.h"
-
-#define FERMI_COMPUTE_A    0x90C0
-
-typedef volatile struct _cl90c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 LoadMmeInstructionRamPointer;
-    NvU32 LoadMmeInstructionRam;
-    NvU32 LoadMmeStartAddressRamPointer;
-    NvU32 LoadMmeStartAddressRam;
-    NvU32 SetMmeShadowRamControl;
-    NvU32 Reserved_0x128[0x2];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 Reserved_0x144[0x3];
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0x2B];
-    NvU32 SetShaderLocalMemoryLowSize;
-    NvU32 SetShaderLocalMemoryHighSize;
-    NvU32 SetShaderLocalMemoryCrsSize;
-    NvU32 SetBindingControlTexture;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 Reserved_0x218[0x1];
-    NvU32 InvalidateShaderCaches;
-    NvU32 Reserved_0x220[0x2];
-    NvU32 BindTextureSampler;
-    NvU32 BindTextureHeader;
-    NvU32 BindExtraTextureSampler;
-    NvU32 BindExtraTextureHeader;
-    NvU32 SetCtaRasterSizeA;
-    NvU32 SetCtaRasterSizeB;
-    NvU32 Reserved_0x240[0x1];
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 Reserved_0x248[0x1];
-    NvU32 SetShaderSharedMemorySize;
-    NvU32 SetCtaThreadCount;
-    NvU32 SetCtaBarrierCount;
-    NvU32 Reserved_0x258[0xD];
-    NvU32 TestForCompute;
-    NvU32 Reserved_0x290[0x3];
-    NvU32 BeginGrid;
-    NvU32 SetWorkDistribution;
-    NvU32 Reserved_0x2A4[0x7];
-    NvU32 SetCtaRegisterCount;
-    NvU32 SetGaToVaMappingMode;
-    NvU32 LoadGaToVaMappingEntry;
-    NvU32 Reserved_0x2CC[0xF];
-    NvU32 SetL1Configuration;
-    NvU32 SetRenderEnableControl;
-    NvU32 Reserved_0x310[0x14];
-    NvU32 WaitRefCount;
-    NvU32 Reserved_0x364[0x1];
-    NvU32 Launch;
-    NvU32 SetLaunchId;
-    NvU32 Reserved_0x370[0xF];
-    NvU32 SetCtaThreadDimensionA;
-    NvU32 SetCtaThreadDimensionB;
-    NvU32 SetCtaProgramStart;
-    NvU32 Reserved_0x3B8[0x52];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x76];
-    NvU32 SetMaxSmCount;
-    NvU32 Reserved_0x75C[0x8];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 SetGridParam;
-    NvU32 Reserved_0x784[0x3];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 SetShaderLocalMemoryC;
-    NvU32 SetShaderLocalMemoryD;
-    NvU32 SetShaderLocalMemoryE;
-    NvU32 Reserved_0x7A4[0x98];
-    NvU32 EndGrid;
-    NvU32 SetLaunchSize;
-    NvU32 Reserved_0xA0C[0xD6];
-    NvU32 SetApiVisibleCallLimit;
-    NvU32 Reserved_0xD68[0xB];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x2C];
-    NvU32 SetForceOneTextureUnit;
-    NvU32 Reserved_0x1008[0xE];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x21];
-    NvU32 UnbindAll;
-    NvU32 Reserved_0x10F8[0x4F];
-    NvU32 SetSamplerBinding;
-    NvU32 Reserved_0x1238[0x14];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x8];
-    NvU32 SetShaderScheduling;
-    NvU32 Reserved_0x12B0[0x20];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x6];
-    NvU32 SetGlobalColorKey;
-    NvU32 Reserved_0x1358[0x33];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x3F];
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x15];
-    NvU32 SetCubemapInterFaceFiltering;
-    NvU32 Reserved_0x1668[0xA];
-    NvU32 SetShaderControl;
-    NvU32 BindConstantBuffer;
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xA5];
-    NvU32 InvalidateConstantBufferCache;
-    NvU32 Reserved_0x1934[0x4];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x21C];
-    NvU32 SetConstantBufferSelectorA;
-    NvU32 SetConstantBufferSelectorB;
-    NvU32 SetConstantBufferSelectorC;
-    NvU32 LoadConstantBufferOffset;
-    NvU32 LoadConstantBuffer[0x10];
-    NvU32 Reserved_0x23D0[0xCC];
-    struct {
-        NvU32 A;
-        NvU32 B;
-        NvU32 C;
-        NvU32 D;
-        NvU32 Format;
-        NvU32 BlockSize;
-        NvU32 Reserved_0x18[0x2];
-    } SetSuLdStTarget[0x8];
-    NvU32 Reserved_0x2800[0x2D7];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 Reserved_0x33E0[0x8];
-    NvU32 SetMmeShadowScratch[0x80];
-    NvU32 Reserved_0x3600[0x80];
-    struct {
-        NvU32 Macro;
-        NvU32 Data;
-    } CallMme[0x80];
-} fermi_compute_a_t;
-
-
-#define NV90C0_SET_OBJECT                                                                                  0x0000
-#define NV90C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NV90C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NV90C0_NO_OPERATION                                                                                0x0100
-#define NV90C0_NO_OPERATION_V                                                                                31:0
-
-#define NV90C0_SET_NOTIFY_A                                                                                0x0104
-#define NV90C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NV90C0_SET_NOTIFY_B                                                                                0x0108
-#define NV90C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NV90C0_NOTIFY                                                                                      0x010c
-#define NV90C0_NOTIFY_TYPE                                                                                   31:0
-#define NV90C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NV90C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NV90C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NV90C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER                                                            0x0114
-#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V                                                            31:0
-
-#define NV90C0_LOAD_MME_INSTRUCTION_RAM                                                                    0x0118
-#define NV90C0_LOAD_MME_INSTRUCTION_RAM_V                                                                    31:0
-
-#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER                                                          0x011c
-#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V                                                          31:0
-
-#define NV90C0_LOAD_MME_START_ADDRESS_RAM                                                                  0x0120
-#define NV90C0_LOAD_MME_START_ADDRESS_RAM_V                                                                  31:0
-
-#define NV90C0_SET_MME_SHADOW_RAM_CONTROL                                                                  0x0124
-#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE                                                                1:0
-#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK                                            0x00000000
-#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER                                0x00000001
-#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH                                      0x00000002
-#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY                                           0x00000003
-
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NV90C0_SEND_GO_IDLE                                                                                0x013c
-#define NV90C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NV90C0_PM_TRIGGER                                                                                  0x0140
-#define NV90C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE                                                            0x0204
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V                                                            23:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE                                                           0x0208
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V                                                           23:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE                                                            0x020c
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V                                                            20:0
-
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE                                                                 0x0210
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS                                                3:0
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                      0x00000000
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                      0x00000001
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                      0x00000002
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                      0x00000003
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                     0x00000004
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS                                                 7:4
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1                                       0x00000000
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2                                       0x00000001
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4                                       0x00000002
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8                                       0x00000003
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16                                      0x00000004
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32                                      0x00000005
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64                                      0x00000006
-#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128                                     0x00000007
-
-#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NV90C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM                                                               8:8
-#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE                                                  0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE                                                   0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NV90C0_BIND_TEXTURE_SAMPLER                                                                        0x0228
-#define NV90C0_BIND_TEXTURE_SAMPLER_VALID                                                                     0:0
-#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_FALSE                                                        0x00000000
-#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_TRUE                                                         0x00000001
-#define NV90C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT                                                             11:4
-#define NV90C0_BIND_TEXTURE_SAMPLER_INDEX                                                                   24:12
-
-#define NV90C0_BIND_TEXTURE_HEADER                                                                         0x022c
-#define NV90C0_BIND_TEXTURE_HEADER_VALID                                                                      0:0
-#define NV90C0_BIND_TEXTURE_HEADER_VALID_FALSE                                                         0x00000000
-#define NV90C0_BIND_TEXTURE_HEADER_VALID_TRUE                                                          0x00000001
-#define NV90C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT                                                               8:1
-#define NV90C0_BIND_TEXTURE_HEADER_INDEX                                                                     30:9
-
-#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER                                                                  0x0230
-#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID                                                               0:0
-#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE                                                  0x00000000
-#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE                                                   0x00000001
-#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                       11:4
-#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX                                                             24:12
-
-#define NV90C0_BIND_EXTRA_TEXTURE_HEADER                                                                   0x0234
-#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID                                                                0:0
-#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE                                                   0x00000000
-#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE                                                    0x00000001
-#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT                                                         8:1
-#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_INDEX                                                               30:9
-
-#define NV90C0_SET_CTA_RASTER_SIZE_A                                                                       0x0238
-#define NV90C0_SET_CTA_RASTER_SIZE_A_WIDTH                                                                   15:0
-#define NV90C0_SET_CTA_RASTER_SIZE_A_HEIGHT                                                                 31:16
-
-#define NV90C0_SET_CTA_RASTER_SIZE_B                                                                       0x023c
-#define NV90C0_SET_CTA_RASTER_SIZE_B_DEPTH                                                                   15:0
-
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE                                                               0x024c
-#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE_V                                                               17:0
-
-#define NV90C0_SET_CTA_THREAD_COUNT                                                                        0x0250
-#define NV90C0_SET_CTA_THREAD_COUNT_V                                                                        15:0
-
-#define NV90C0_SET_CTA_BARRIER_COUNT                                                                       0x0254
-#define NV90C0_SET_CTA_BARRIER_COUNT_V                                                                        7:0
-
-#define NV90C0_TEST_FOR_COMPUTE                                                                            0x028c
-#define NV90C0_TEST_FOR_COMPUTE_V                                                                            31:0
-
-#define NV90C0_BEGIN_GRID                                                                                  0x029c
-#define NV90C0_BEGIN_GRID_V                                                                                   0:0
-
-#define NV90C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
-#define NV90C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE                                                         16:13
-#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE                                                               4:4
-#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE                                                  0x00000000
-#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE                                                   0x00000001
-#define NV90C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS                                                        12:5
-
-#define NV90C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
-#define NV90C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
-
-#define NV90C0_SET_GA_TO_VA_MAPPING_MODE                                                                   0x02c4
-#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V                                                                    0:0
-#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE                                                     0x00000000
-#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE                                                      0x00000001
-
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY                                                                 0x02c8
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER                                              7:0
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER                                            23:16
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE                                                      30:30
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE                                           0x00000000
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE                                            0x00000001
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE                                                     31:31
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE                                          0x00000000
-#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE                                           0x00000001
-
-#define NV90C0_SET_L1_CONFIGURATION                                                                        0x0308
-#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY                                               2:0
-#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB                              0x00000001
-#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB                              0x00000003
-
-#define NV90C0_SET_RENDER_ENABLE_CONTROL                                                                   0x030c
-#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER                                     0:0
-#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE                        0x00000000
-#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE                         0x00000001
-
-#define NV90C0_WAIT_REF_COUNT                                                                              0x0360
-#define NV90C0_WAIT_REF_COUNT_REF_CNT                                                                         9:8
-#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM                                                                   0:0
-#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE                                                      0x00000000
-#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE                                                       0x00000001
-
-#define NV90C0_LAUNCH                                                                                      0x0368
-#define NV90C0_LAUNCHCTA_PARAM                                                                               31:0
-
-#define NV90C0_SET_LAUNCH_ID                                                                               0x036c
-#define NV90C0_SET_LAUNCH_ID_REF_CNT                                                                          1:0
-
-#define NV90C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
-#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
-#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
-
-#define NV90C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
-#define NV90C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
-
-#define NV90C0_SET_CTA_PROGRAM_START                                                                       0x03b4
-#define NV90C0_SET_CTA_PROGRAM_START_OFFSET                                                                  31:0
-
-#define NV90C0_SET_FALCON00                                                                                0x0500
-#define NV90C0_SET_FALCON00_V                                                                                31:0
-
-#define NV90C0_SET_FALCON01                                                                                0x0504
-#define NV90C0_SET_FALCON01_V                                                                                31:0
-
-#define NV90C0_SET_FALCON02                                                                                0x0508
-#define NV90C0_SET_FALCON02_V                                                                                31:0
-
-#define NV90C0_SET_FALCON03                                                                                0x050c
-#define NV90C0_SET_FALCON03_V                                                                                31:0
-
-#define NV90C0_SET_FALCON04                                                                                0x0510
-#define NV90C0_SET_FALCON04_V                                                                                31:0
-
-#define NV90C0_SET_FALCON05                                                                                0x0514
-#define NV90C0_SET_FALCON05_V                                                                                31:0
-
-#define NV90C0_SET_FALCON06                                                                                0x0518
-#define NV90C0_SET_FALCON06_V                                                                                31:0
-
-#define NV90C0_SET_FALCON07                                                                                0x051c
-#define NV90C0_SET_FALCON07_V                                                                                31:0
-
-#define NV90C0_SET_FALCON08                                                                                0x0520
-#define NV90C0_SET_FALCON08_V                                                                                31:0
-
-#define NV90C0_SET_FALCON09                                                                                0x0524
-#define NV90C0_SET_FALCON09_V                                                                                31:0
-
-#define NV90C0_SET_FALCON10                                                                                0x0528
-#define NV90C0_SET_FALCON10_V                                                                                31:0
-
-#define NV90C0_SET_FALCON11                                                                                0x052c
-#define NV90C0_SET_FALCON11_V                                                                                31:0
-
-#define NV90C0_SET_FALCON12                                                                                0x0530
-#define NV90C0_SET_FALCON12_V                                                                                31:0
-
-#define NV90C0_SET_FALCON13                                                                                0x0534
-#define NV90C0_SET_FALCON13_V                                                                                31:0
-
-#define NV90C0_SET_FALCON14                                                                                0x0538
-#define NV90C0_SET_FALCON14_V                                                                                31:0
-
-#define NV90C0_SET_FALCON15                                                                                0x053c
-#define NV90C0_SET_FALCON15_V                                                                                31:0
-
-#define NV90C0_SET_FALCON16                                                                                0x0540
-#define NV90C0_SET_FALCON16_V                                                                                31:0
-
-#define NV90C0_SET_FALCON17                                                                                0x0544
-#define NV90C0_SET_FALCON17_V                                                                                31:0
-
-#define NV90C0_SET_FALCON18                                                                                0x0548
-#define NV90C0_SET_FALCON18_V                                                                                31:0
-
-#define NV90C0_SET_FALCON19                                                                                0x054c
-#define NV90C0_SET_FALCON19_V                                                                                31:0
-
-#define NV90C0_SET_FALCON20                                                                                0x0550
-#define NV90C0_SET_FALCON20_V                                                                                31:0
-
-#define NV90C0_SET_FALCON21                                                                                0x0554
-#define NV90C0_SET_FALCON21_V                                                                                31:0
-
-#define NV90C0_SET_FALCON22                                                                                0x0558
-#define NV90C0_SET_FALCON22_V                                                                                31:0
-
-#define NV90C0_SET_FALCON23                                                                                0x055c
-#define NV90C0_SET_FALCON23_V                                                                                31:0
-
-#define NV90C0_SET_FALCON24                                                                                0x0560
-#define NV90C0_SET_FALCON24_V                                                                                31:0
-
-#define NV90C0_SET_FALCON25                                                                                0x0564
-#define NV90C0_SET_FALCON25_V                                                                                31:0
-
-#define NV90C0_SET_FALCON26                                                                                0x0568
-#define NV90C0_SET_FALCON26_V                                                                                31:0
-
-#define NV90C0_SET_FALCON27                                                                                0x056c
-#define NV90C0_SET_FALCON27_V                                                                                31:0
-
-#define NV90C0_SET_FALCON28                                                                                0x0570
-#define NV90C0_SET_FALCON28_V                                                                                31:0
-
-#define NV90C0_SET_FALCON29                                                                                0x0574
-#define NV90C0_SET_FALCON29_V                                                                                31:0
-
-#define NV90C0_SET_FALCON30                                                                                0x0578
-#define NV90C0_SET_FALCON30_V                                                                                31:0
-
-#define NV90C0_SET_FALCON31                                                                                0x057c
-#define NV90C0_SET_FALCON31_V                                                                                31:0
-
-#define NV90C0_SET_MAX_SM_COUNT                                                                            0x0758
-#define NV90C0_SET_MAX_SM_COUNT_V                                                                             8:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NV90C0_SET_GRID_PARAM                                                                              0x0780
-#define NV90C0_SET_GRID_PARAM_V                                                                              31:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_C                                                                   0x0798
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER                                                           5:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_D                                                                   0x079c
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER                                                          31:0
-
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_E                                                                   0x07a0
-#define NV90C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP                                               25:0
-
-#define NV90C0_END_GRID                                                                                    0x0a04
-#define NV90C0_END_GRID_V                                                                                     0:0
-
-#define NV90C0_SET_LAUNCH_SIZE                                                                             0x0a08
-#define NV90C0_SET_LAUNCH_SIZE_V                                                                             31:0
-
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT                                                                  0x0d64
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA                                                                 3:0
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0                                                       0x00000000
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1                                                       0x00000001
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2                                                       0x00000002
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4                                                       0x00000003
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8                                                       0x00000004
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16                                                      0x00000005
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32                                                      0x00000006
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64                                                      0x00000007
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128                                                     0x00000008
-#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK                                                 0x0000000F
-
-#define NV90C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NV90C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NV90C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NV90C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NV90C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NV90C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NV90C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NV90C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT                                                                  0x1004
-#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE                                                              0:0
-#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE                                                 0x00000000
-#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE                                                  0x00000001
-
-#define NV90C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NV90C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NV90C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NV90C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NV90C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NV90C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NV90C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NV90C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NV90C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NV90C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NV90C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NV90C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NV90C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NV90C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NV90C0_UNBIND_ALL                                                                                  0x10f4
-#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS                                                                     0:0
-#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE                                                        0x00000000
-#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE                                                         0x00000001
-#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS                                                                    4:4
-#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE                                                       0x00000000
-#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE                                                        0x00000001
-#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS                                                                    8:8
-#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE                                                       0x00000000
-#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE                                                        0x00000001
-
-#define NV90C0_SET_SAMPLER_BINDING                                                                         0x1234
-#define NV90C0_SET_SAMPLER_BINDING_V                                                                          0:0
-#define NV90C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
-#define NV90C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
-
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NV90C0_SET_SHADER_SCHEDULING                                                                       0x12ac
-#define NV90C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
-#define NV90C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
-#define NV90C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
-
-#define NV90C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           2:1
-#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
-
-#define NV90C0_SET_GLOBAL_COLOR_KEY                                                                        0x1354
-#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                    0:0
-#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
-#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
-
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NV90C0_PERFMON_TRANSFER                                                                            0x1524
-#define NV90C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NV90C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NV90C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NV90C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NV90C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NV90C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NV90C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NV90C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NV90C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NV90C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NV90C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NV90C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NV90C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NV90C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NV90C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NV90C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NV90C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NV90C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NV90C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NV90C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NV90C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NV90C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NV90C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NV90C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NV90C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
-
-#define NV90C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NV90C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING                                                            0x1664
-#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE                                                          1:0
-#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP                                          0x00000000
-#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP                                     0x00000001
-#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM                                    0x00000002
-#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM                                   0x00000003
-
-#define NV90C0_SET_SHADER_CONTROL                                                                          0x1690
-#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
-#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
-#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
-#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
-#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
-#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
-
-#define NV90C0_BIND_CONSTANT_BUFFER                                                                        0x1694
-#define NV90C0_BIND_CONSTANT_BUFFER_VALID                                                                     0:0
-#define NV90C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
-#define NV90C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
-#define NV90C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              12:8
-
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM                                                        8:8
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE                                           0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE                                            0x00000001
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE                                                            0x1930
-#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2                                                       0:0
-#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE                                          0x00000000
-#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE                                           0x00000001
-
-#define NV90C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NV90C0_PIPE_NOP                                                                                    0x1a2c
-#define NV90C0_PIPE_NOP_V                                                                                    31:0
-
-#define NV90C0_SET_SPARE00                                                                                 0x1a30
-#define NV90C0_SET_SPARE00_V                                                                                 31:0
-
-#define NV90C0_SET_SPARE01                                                                                 0x1a34
-#define NV90C0_SET_SPARE01_V                                                                                 31:0
-
-#define NV90C0_SET_SPARE02                                                                                 0x1a38
-#define NV90C0_SET_SPARE02_V                                                                                 31:0
-
-#define NV90C0_SET_SPARE03                                                                                 0x1a3c
-#define NV90C0_SET_SPARE03_V                                                                                 31:0
-
-#define NV90C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NV90C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NV90C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NV90C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NV90C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NV90C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NV90C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-
-#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A                                                              0x2380
-#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE                                                           16:0
-
-#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B                                                              0x2384
-#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER                                                   7:0
-
-#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C                                                              0x2388
-#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER                                                  31:0
-
-#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET                                                                 0x238c
-#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET_V                                                                 15:0
-
-#define NV90C0_LOAD_CONSTANT_BUFFER(i)                                                             (0x2390+(i)*4)
-#define NV90C0_LOAD_CONSTANT_BUFFER_V                                                                        31:0
-
-#define NV90C0_SET_SU_LD_ST_TARGET_A(j)                                                           (0x2700+(j)*32)
-#define NV90C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER                                                             7:0
-
-#define NV90C0_SET_SU_LD_ST_TARGET_B(j)                                                           (0x2704+(j)*32)
-#define NV90C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER                                                            31:0
-
-#define NV90C0_SET_SU_LD_ST_TARGET_C(j)                                                           (0x2708+(j)*32)
-#define NV90C0_SET_SU_LD_ST_TARGET_C_WIDTH                                                                   31:0
-
-#define NV90C0_SET_SU_LD_ST_TARGET_D(j)                                                           (0x270c+(j)*32)
-#define NV90C0_SET_SU_LD_ST_TARGET_D_HEIGHT                                                                  16:0
-#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY                                                       20:20
-#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR                                      0x00000000
-#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH                                            0x00000001
-
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT(j)                                                      (0x2710+(j)*32)
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE                                                                0:0
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR                                                   0x00000000
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA                                                    0x00000001
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR                                                              11:4
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED                                               0x00000000
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32                                    0x000000C0
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32                                    0x000000C1
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32                                    0x000000C2
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32                                     0x000000C3
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32                                     0x000000C4
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32                                     0x000000C5
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16                                        0x000000C6
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16                                    0x000000C7
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16                                    0x000000C8
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16                                    0x000000C9
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16                                    0x000000CA
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32                                              0x000000CB
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32                                              0x000000CC
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32                                              0x000000CD
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16                                     0x000000CE
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8                                               0x000000CF
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8                                            0x000000D0
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10                                            0x000000D1
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10                                        0x000000D2
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8                                               0x000000D5
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8                                            0x000000D6
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8                                           0x000000D7
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8                                           0x000000D8
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8                                           0x000000D9
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16                                                0x000000DA
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16                                              0x000000DB
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16                                              0x000000DC
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16                                              0x000000DD
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16                                              0x000000DE
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10                                            0x000000DF
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11                                           0x000000E0
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32                                                   0x000000E3
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32                                                   0x000000E4
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32                                                   0x000000E5
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8                                               0x000000E6
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8                                            0x000000E7
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5                                                 0x000000E8
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5                                               0x000000E9
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8                                                   0x000000EA
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8                                                 0x000000EB
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8                                                 0x000000EC
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8                                                 0x000000ED
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16                                                    0x000000EE
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16                                                   0x000000EF
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16                                                   0x000000F0
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16                                                   0x000000F1
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16                                                   0x000000F2
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8                                                     0x000000F3
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8                                                    0x000000F4
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8                                                    0x000000F5
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8                                                    0x000000F6
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8                                                     0x000000F7
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5                                               0x000000F8
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8                                               0x000000F9
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8                                            0x000000FA
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5                                               0x000000FB
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5                                               0x000000FC
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8                                               0x000000FD
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8                                               0x000000FE
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32                                                    0x000000FF
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16                                                    0x00000040
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16                                                   0x00000041
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32                                                   0x00000042
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8                                                   0x00000043
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16                                                0x00000044
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16                                              0x00000045
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32                                              0x00000046
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA                                                              16:12
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16                                                     0x00000013
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8                                                   0x00000014
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24                                                   0x00000015
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24                                                   0x00000016
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24                                                   0x00000018
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32                                                    0x0000000A
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8                                              0x00000019
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8                                           0x0000001D
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8                                            0x0000001E
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8                                            0x0000001F
-#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT                                                        25:17
-
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j)                                                  (0x2714+(j)*32)
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH                                                           3:0
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB                                            0x00000000
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT                                                          7:4
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB                                           0x00000000
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS                                          0x00000001
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                         0x00000002
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                        0x00000003
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                      0x00000004
-#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                    0x00000005
-
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                2:0
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           6:4
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                               10:8
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                         14:12
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              18:16
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         22:20
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              26:24
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         30:28
-
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NV90C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NV90C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#define NV90C0_CALL_MME_MACRO(j)                                                                   (0x3800+(j)*8)
-#define NV90C0_CALL_MME_MACRO_V                                                                              31:0
-
-#define NV90C0_CALL_MME_DATA(j)                                                                    (0x3804+(j)*8)
-#define NV90C0_CALL_MME_DATA_V                                                                               31:0
-
-#endif /* _cl_fermi_compute_a_h_ */
diff --git a/Compute-Class-Methods/cl91c0.h b/Compute-Class-Methods/cl91c0.h
deleted file mode 100644
index b83f4aa..0000000
--- a/Compute-Class-Methods/cl91c0.h
+++ /dev/null
@@ -1,1049 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_fermi_compute_b_h_
-#define _cl_fermi_compute_b_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../class/bin/sw_header.pl fermi_compute_b */
-
-#include "nvtypes.h"
-
-#define FERMI_COMPUTE_B    0x91C0
-
-typedef volatile struct _cl91c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 LoadMmeInstructionRamPointer;
-    NvU32 LoadMmeInstructionRam;
-    NvU32 LoadMmeStartAddressRamPointer;
-    NvU32 LoadMmeStartAddressRam;
-    NvU32 SetMmeShadowRamControl;
-    NvU32 Reserved_0x128[0x2];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 Reserved_0x144[0x3];
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0x2B];
-    NvU32 SetShaderLocalMemoryLowSize;
-    NvU32 SetShaderLocalMemoryHighSize;
-    NvU32 SetShaderLocalMemoryCrsSize;
-    NvU32 SetBindingControlTexture;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 Reserved_0x218[0x1];
-    NvU32 InvalidateShaderCaches;
-    NvU32 Reserved_0x220[0x2];
-    NvU32 BindTextureSampler;
-    NvU32 BindTextureHeader;
-    NvU32 BindExtraTextureSampler;
-    NvU32 BindExtraTextureHeader;
-    NvU32 SetCtaRasterSizeA;
-    NvU32 SetCtaRasterSizeB;
-    NvU32 Reserved_0x240[0x1];
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 Reserved_0x248[0x1];
-    NvU32 SetShaderSharedMemorySize;
-    NvU32 SetCtaThreadCount;
-    NvU32 SetCtaBarrierCount;
-    NvU32 Reserved_0x258[0xD];
-    NvU32 TestForCompute;
-    NvU32 Reserved_0x290[0x3];
-    NvU32 BeginGrid;
-    NvU32 SetWorkDistribution;
-    NvU32 Reserved_0x2A4[0x7];
-    NvU32 SetCtaRegisterCount;
-    NvU32 SetGaToVaMappingMode;
-    NvU32 LoadGaToVaMappingEntry;
-    NvU32 Reserved_0x2CC[0x5];
-    NvU32 SetTexHeaderExtendedDimensions;
-    NvU32 Reserved_0x2E4[0x9];
-    NvU32 SetL1Configuration;
-    NvU32 SetRenderEnableControl;
-    NvU32 Reserved_0x310[0x14];
-    NvU32 WaitRefCount;
-    NvU32 Reserved_0x364[0x1];
-    NvU32 Launch;
-    NvU32 SetLaunchId;
-    NvU32 Reserved_0x370[0xF];
-    NvU32 SetCtaThreadDimensionA;
-    NvU32 SetCtaThreadDimensionB;
-    NvU32 SetCtaProgramStart;
-    NvU32 Reserved_0x3B8[0x52];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x76];
-    NvU32 SetMaxSmCount;
-    NvU32 Reserved_0x75C[0x8];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 SetGridParam;
-    NvU32 Reserved_0x784[0x3];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 SetShaderLocalMemoryC;
-    NvU32 SetShaderLocalMemoryD;
-    NvU32 SetShaderLocalMemoryE;
-    NvU32 Reserved_0x7A4[0x98];
-    NvU32 EndGrid;
-    NvU32 SetLaunchSize;
-    NvU32 Reserved_0xA0C[0xD6];
-    NvU32 SetApiVisibleCallLimit;
-    NvU32 Reserved_0xD68[0xB];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x2C];
-    NvU32 SetForceOneTextureUnit;
-    NvU32 Reserved_0x1008[0xE];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x21];
-    NvU32 UnbindAll;
-    NvU32 Reserved_0x10F8[0x4F];
-    NvU32 SetSamplerBinding;
-    NvU32 Reserved_0x1238[0x14];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x8];
-    NvU32 SetShaderScheduling;
-    NvU32 Reserved_0x12B0[0x20];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x6];
-    NvU32 SetGlobalColorKey;
-    NvU32 Reserved_0x1358[0x33];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x3F];
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x15];
-    NvU32 SetCubemapInterFaceFiltering;
-    NvU32 Reserved_0x1668[0xA];
-    NvU32 SetShaderControl;
-    NvU32 BindConstantBuffer;
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xA5];
-    NvU32 InvalidateConstantBufferCache;
-    NvU32 Reserved_0x1934[0x4];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x21C];
-    NvU32 SetConstantBufferSelectorA;
-    NvU32 SetConstantBufferSelectorB;
-    NvU32 SetConstantBufferSelectorC;
-    NvU32 LoadConstantBufferOffset;
-    NvU32 LoadConstantBuffer[0x10];
-    NvU32 Reserved_0x23D0[0xCC];
-    struct {
-        NvU32 A;
-        NvU32 B;
-        NvU32 C;
-        NvU32 D;
-        NvU32 Format;
-        NvU32 BlockSize;
-        NvU32 Reserved_0x18[0x2];
-    } SetSuLdStTarget[0x8];
-    NvU32 Reserved_0x2800[0x2D7];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 Reserved_0x33E0[0x8];
-    NvU32 SetMmeShadowScratch[0x80];
-    NvU32 Reserved_0x3600[0x80];
-    struct {
-        NvU32 Macro;
-        NvU32 Data;
-    } CallMme[0x80];
-} fermi_compute_b_t;
-
-
-#define NV91C0_SET_OBJECT                                                                                  0x0000
-#define NV91C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NV91C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NV91C0_NO_OPERATION                                                                                0x0100
-#define NV91C0_NO_OPERATION_V                                                                                31:0
-
-#define NV91C0_SET_NOTIFY_A                                                                                0x0104
-#define NV91C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NV91C0_SET_NOTIFY_B                                                                                0x0108
-#define NV91C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NV91C0_NOTIFY                                                                                      0x010c
-#define NV91C0_NOTIFY_TYPE                                                                                   31:0
-#define NV91C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NV91C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NV91C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NV91C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER                                                            0x0114
-#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V                                                            31:0
-
-#define NV91C0_LOAD_MME_INSTRUCTION_RAM                                                                    0x0118
-#define NV91C0_LOAD_MME_INSTRUCTION_RAM_V                                                                    31:0
-
-#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER                                                          0x011c
-#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V                                                          31:0
-
-#define NV91C0_LOAD_MME_START_ADDRESS_RAM                                                                  0x0120
-#define NV91C0_LOAD_MME_START_ADDRESS_RAM_V                                                                  31:0
-
-#define NV91C0_SET_MME_SHADOW_RAM_CONTROL                                                                  0x0124
-#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE                                                                1:0
-#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK                                            0x00000000
-#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER                                0x00000001
-#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH                                      0x00000002
-#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY                                           0x00000003
-
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NV91C0_SEND_GO_IDLE                                                                                0x013c
-#define NV91C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NV91C0_PM_TRIGGER                                                                                  0x0140
-#define NV91C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE                                                            0x0204
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V                                                            23:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE                                                           0x0208
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V                                                           23:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE                                                            0x020c
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V                                                            20:0
-
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE                                                                 0x0210
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS                                                3:0
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                      0x00000000
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                      0x00000001
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                      0x00000002
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                      0x00000003
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                     0x00000004
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS                                                 7:4
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1                                       0x00000000
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2                                       0x00000001
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4                                       0x00000002
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8                                       0x00000003
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16                                      0x00000004
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32                                      0x00000005
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64                                      0x00000006
-#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128                                     0x00000007
-
-#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NV91C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM                                                               8:8
-#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE                                                  0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE                                                   0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NV91C0_BIND_TEXTURE_SAMPLER                                                                        0x0228
-#define NV91C0_BIND_TEXTURE_SAMPLER_VALID                                                                     0:0
-#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_FALSE                                                        0x00000000
-#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_TRUE                                                         0x00000001
-#define NV91C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT                                                             11:4
-#define NV91C0_BIND_TEXTURE_SAMPLER_INDEX                                                                   24:12
-
-#define NV91C0_BIND_TEXTURE_HEADER                                                                         0x022c
-#define NV91C0_BIND_TEXTURE_HEADER_VALID                                                                      0:0
-#define NV91C0_BIND_TEXTURE_HEADER_VALID_FALSE                                                         0x00000000
-#define NV91C0_BIND_TEXTURE_HEADER_VALID_TRUE                                                          0x00000001
-#define NV91C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT                                                               8:1
-#define NV91C0_BIND_TEXTURE_HEADER_INDEX                                                                     30:9
-
-#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER                                                                  0x0230
-#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID                                                               0:0
-#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE                                                  0x00000000
-#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE                                                   0x00000001
-#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                       11:4
-#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX                                                             24:12
-
-#define NV91C0_BIND_EXTRA_TEXTURE_HEADER                                                                   0x0234
-#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID                                                                0:0
-#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE                                                   0x00000000
-#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE                                                    0x00000001
-#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT                                                         8:1
-#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_INDEX                                                               30:9
-
-#define NV91C0_SET_CTA_RASTER_SIZE_A                                                                       0x0238
-#define NV91C0_SET_CTA_RASTER_SIZE_A_WIDTH                                                                   15:0
-#define NV91C0_SET_CTA_RASTER_SIZE_A_HEIGHT                                                                 31:16
-
-#define NV91C0_SET_CTA_RASTER_SIZE_B                                                                       0x023c
-#define NV91C0_SET_CTA_RASTER_SIZE_B_DEPTH                                                                   15:0
-#define NV91C0_SET_CTA_RASTER_SIZE_B_WIDTH_UPPER                                                            31:16
-
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE                                                               0x024c
-#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE_V                                                               17:0
-
-#define NV91C0_SET_CTA_THREAD_COUNT                                                                        0x0250
-#define NV91C0_SET_CTA_THREAD_COUNT_V                                                                        15:0
-
-#define NV91C0_SET_CTA_BARRIER_COUNT                                                                       0x0254
-#define NV91C0_SET_CTA_BARRIER_COUNT_V                                                                        7:0
-
-#define NV91C0_TEST_FOR_COMPUTE                                                                            0x028c
-#define NV91C0_TEST_FOR_COMPUTE_V                                                                            31:0
-
-#define NV91C0_BEGIN_GRID                                                                                  0x029c
-#define NV91C0_BEGIN_GRID_V                                                                                   0:0
-
-#define NV91C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
-#define NV91C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE                                                         16:13
-#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE                                                               4:4
-#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE                                                  0x00000000
-#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE                                                   0x00000001
-#define NV91C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS                                                        12:5
-
-#define NV91C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
-#define NV91C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
-
-#define NV91C0_SET_GA_TO_VA_MAPPING_MODE                                                                   0x02c4
-#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V                                                                    0:0
-#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE                                                     0x00000000
-#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE                                                      0x00000001
-
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY                                                                 0x02c8
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER                                              7:0
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER                                            23:16
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE                                                      30:30
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE                                           0x00000000
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE                                            0x00000001
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE                                                     31:31
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE                                          0x00000000
-#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE                                           0x00000001
-
-#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS                                                          0x02e0
-#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE                                                      0:0
-#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_FALSE                                         0x00000000
-#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_TRUE                                          0x00000001
-
-#define NV91C0_SET_L1_CONFIGURATION                                                                        0x0308
-#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY                                               2:0
-#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB                              0x00000001
-#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB                              0x00000002
-#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB                              0x00000003
-
-#define NV91C0_SET_RENDER_ENABLE_CONTROL                                                                   0x030c
-#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER                                     0:0
-#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE                        0x00000000
-#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE                         0x00000001
-
-#define NV91C0_WAIT_REF_COUNT                                                                              0x0360
-#define NV91C0_WAIT_REF_COUNT_REF_CNT                                                                        11:8
-#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM                                                                   0:0
-#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE                                                      0x00000000
-#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE                                                       0x00000001
-
-#define NV91C0_LAUNCH                                                                                      0x0368
-#define NV91C0_LAUNCHCTA_PARAM                                                                               31:0
-
-#define NV91C0_SET_LAUNCH_ID                                                                               0x036c
-#define NV91C0_SET_LAUNCH_ID_REF_CNT                                                                          3:0
-
-#define NV91C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
-#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
-#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
-
-#define NV91C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
-#define NV91C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
-
-#define NV91C0_SET_CTA_PROGRAM_START                                                                       0x03b4
-#define NV91C0_SET_CTA_PROGRAM_START_OFFSET                                                                  31:0
-
-#define NV91C0_SET_FALCON00                                                                                0x0500
-#define NV91C0_SET_FALCON00_V                                                                                31:0
-
-#define NV91C0_SET_FALCON01                                                                                0x0504
-#define NV91C0_SET_FALCON01_V                                                                                31:0
-
-#define NV91C0_SET_FALCON02                                                                                0x0508
-#define NV91C0_SET_FALCON02_V                                                                                31:0
-
-#define NV91C0_SET_FALCON03                                                                                0x050c
-#define NV91C0_SET_FALCON03_V                                                                                31:0
-
-#define NV91C0_SET_FALCON04                                                                                0x0510
-#define NV91C0_SET_FALCON04_V                                                                                31:0
-
-#define NV91C0_SET_FALCON05                                                                                0x0514
-#define NV91C0_SET_FALCON05_V                                                                                31:0
-
-#define NV91C0_SET_FALCON06                                                                                0x0518
-#define NV91C0_SET_FALCON06_V                                                                                31:0
-
-#define NV91C0_SET_FALCON07                                                                                0x051c
-#define NV91C0_SET_FALCON07_V                                                                                31:0
-
-#define NV91C0_SET_FALCON08                                                                                0x0520
-#define NV91C0_SET_FALCON08_V                                                                                31:0
-
-#define NV91C0_SET_FALCON09                                                                                0x0524
-#define NV91C0_SET_FALCON09_V                                                                                31:0
-
-#define NV91C0_SET_FALCON10                                                                                0x0528
-#define NV91C0_SET_FALCON10_V                                                                                31:0
-
-#define NV91C0_SET_FALCON11                                                                                0x052c
-#define NV91C0_SET_FALCON11_V                                                                                31:0
-
-#define NV91C0_SET_FALCON12                                                                                0x0530
-#define NV91C0_SET_FALCON12_V                                                                                31:0
-
-#define NV91C0_SET_FALCON13                                                                                0x0534
-#define NV91C0_SET_FALCON13_V                                                                                31:0
-
-#define NV91C0_SET_FALCON14                                                                                0x0538
-#define NV91C0_SET_FALCON14_V                                                                                31:0
-
-#define NV91C0_SET_FALCON15                                                                                0x053c
-#define NV91C0_SET_FALCON15_V                                                                                31:0
-
-#define NV91C0_SET_FALCON16                                                                                0x0540
-#define NV91C0_SET_FALCON16_V                                                                                31:0
-
-#define NV91C0_SET_FALCON17                                                                                0x0544
-#define NV91C0_SET_FALCON17_V                                                                                31:0
-
-#define NV91C0_SET_FALCON18                                                                                0x0548
-#define NV91C0_SET_FALCON18_V                                                                                31:0
-
-#define NV91C0_SET_FALCON19                                                                                0x054c
-#define NV91C0_SET_FALCON19_V                                                                                31:0
-
-#define NV91C0_SET_FALCON20                                                                                0x0550
-#define NV91C0_SET_FALCON20_V                                                                                31:0
-
-#define NV91C0_SET_FALCON21                                                                                0x0554
-#define NV91C0_SET_FALCON21_V                                                                                31:0
-
-#define NV91C0_SET_FALCON22                                                                                0x0558
-#define NV91C0_SET_FALCON22_V                                                                                31:0
-
-#define NV91C0_SET_FALCON23                                                                                0x055c
-#define NV91C0_SET_FALCON23_V                                                                                31:0
-
-#define NV91C0_SET_FALCON24                                                                                0x0560
-#define NV91C0_SET_FALCON24_V                                                                                31:0
-
-#define NV91C0_SET_FALCON25                                                                                0x0564
-#define NV91C0_SET_FALCON25_V                                                                                31:0
-
-#define NV91C0_SET_FALCON26                                                                                0x0568
-#define NV91C0_SET_FALCON26_V                                                                                31:0
-
-#define NV91C0_SET_FALCON27                                                                                0x056c
-#define NV91C0_SET_FALCON27_V                                                                                31:0
-
-#define NV91C0_SET_FALCON28                                                                                0x0570
-#define NV91C0_SET_FALCON28_V                                                                                31:0
-
-#define NV91C0_SET_FALCON29                                                                                0x0574
-#define NV91C0_SET_FALCON29_V                                                                                31:0
-
-#define NV91C0_SET_FALCON30                                                                                0x0578
-#define NV91C0_SET_FALCON30_V                                                                                31:0
-
-#define NV91C0_SET_FALCON31                                                                                0x057c
-#define NV91C0_SET_FALCON31_V                                                                                31:0
-
-#define NV91C0_SET_MAX_SM_COUNT                                                                            0x0758
-#define NV91C0_SET_MAX_SM_COUNT_V                                                                             8:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NV91C0_SET_GRID_PARAM                                                                              0x0780
-#define NV91C0_SET_GRID_PARAM_V                                                                              31:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_C                                                                   0x0798
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER                                                           5:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_D                                                                   0x079c
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER                                                          31:0
-
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_E                                                                   0x07a0
-#define NV91C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP                                               25:0
-
-#define NV91C0_END_GRID                                                                                    0x0a04
-#define NV91C0_END_GRID_V                                                                                     0:0
-
-#define NV91C0_SET_LAUNCH_SIZE                                                                             0x0a08
-#define NV91C0_SET_LAUNCH_SIZE_V                                                                             31:0
-
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT                                                                  0x0d64
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA                                                                 3:0
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0                                                       0x00000000
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1                                                       0x00000001
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2                                                       0x00000002
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4                                                       0x00000003
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8                                                       0x00000004
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16                                                      0x00000005
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32                                                      0x00000006
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64                                                      0x00000007
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128                                                     0x00000008
-#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK                                                 0x0000000F
-
-#define NV91C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NV91C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NV91C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NV91C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NV91C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NV91C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NV91C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NV91C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT                                                                  0x1004
-#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE                                                              0:0
-#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE                                                 0x00000000
-#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE                                                  0x00000001
-
-#define NV91C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NV91C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NV91C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NV91C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NV91C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NV91C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NV91C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NV91C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NV91C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NV91C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NV91C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NV91C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NV91C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NV91C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NV91C0_UNBIND_ALL                                                                                  0x10f4
-#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS                                                                     0:0
-#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE                                                        0x00000000
-#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE                                                         0x00000001
-#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS                                                                    4:4
-#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE                                                       0x00000000
-#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE                                                        0x00000001
-#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS                                                                    8:8
-#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE                                                       0x00000000
-#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE                                                        0x00000001
-
-#define NV91C0_SET_SAMPLER_BINDING                                                                         0x1234
-#define NV91C0_SET_SAMPLER_BINDING_V                                                                          0:0
-#define NV91C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
-#define NV91C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
-
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NV91C0_SET_SHADER_SCHEDULING                                                                       0x12ac
-#define NV91C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
-#define NV91C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
-#define NV91C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
-
-#define NV91C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           2:1
-#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
-
-#define NV91C0_SET_GLOBAL_COLOR_KEY                                                                        0x1354
-#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                    0:0
-#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
-#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
-
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NV91C0_PERFMON_TRANSFER                                                                            0x1524
-#define NV91C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NV91C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NV91C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NV91C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NV91C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NV91C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NV91C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NV91C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NV91C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NV91C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NV91C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NV91C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NV91C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NV91C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NV91C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NV91C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NV91C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NV91C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NV91C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NV91C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NV91C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NV91C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NV91C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NV91C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NV91C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
-
-#define NV91C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NV91C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING                                                            0x1664
-#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE                                                          1:0
-#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP                                          0x00000000
-#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP                                     0x00000001
-#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM                                    0x00000002
-#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM                                   0x00000003
-
-#define NV91C0_SET_SHADER_CONTROL                                                                          0x1690
-#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
-#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
-#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
-#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
-#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
-#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
-#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR                                                           1:1
-#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY                                             0x00000000
-#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE                                    0x00000001
-#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR                                                       2:2
-#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO                                      0x00000000
-#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE                                0x00000001
-
-#define NV91C0_BIND_CONSTANT_BUFFER                                                                        0x1694
-#define NV91C0_BIND_CONSTANT_BUFFER_VALID                                                                     0:0
-#define NV91C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
-#define NV91C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
-#define NV91C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              12:8
-
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM                                                        8:8
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE                                           0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE                                            0x00000001
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE                                                            0x1930
-#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2                                                       0:0
-#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE                                          0x00000000
-#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE                                           0x00000001
-
-#define NV91C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NV91C0_PIPE_NOP                                                                                    0x1a2c
-#define NV91C0_PIPE_NOP_V                                                                                    31:0
-
-#define NV91C0_SET_SPARE00                                                                                 0x1a30
-#define NV91C0_SET_SPARE00_V                                                                                 31:0
-
-#define NV91C0_SET_SPARE01                                                                                 0x1a34
-#define NV91C0_SET_SPARE01_V                                                                                 31:0
-
-#define NV91C0_SET_SPARE02                                                                                 0x1a38
-#define NV91C0_SET_SPARE02_V                                                                                 31:0
-
-#define NV91C0_SET_SPARE03                                                                                 0x1a3c
-#define NV91C0_SET_SPARE03_V                                                                                 31:0
-
-#define NV91C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NV91C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NV91C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NV91C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NV91C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NV91C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NV91C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-
-#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A                                                              0x2380
-#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE                                                           16:0
-
-#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B                                                              0x2384
-#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER                                                   7:0
-
-#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C                                                              0x2388
-#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER                                                  31:0
-
-#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET                                                                 0x238c
-#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET_V                                                                 15:0
-
-#define NV91C0_LOAD_CONSTANT_BUFFER(i)                                                             (0x2390+(i)*4)
-#define NV91C0_LOAD_CONSTANT_BUFFER_V                                                                        31:0
-
-#define NV91C0_SET_SU_LD_ST_TARGET_A(j)                                                           (0x2700+(j)*32)
-#define NV91C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER                                                             7:0
-
-#define NV91C0_SET_SU_LD_ST_TARGET_B(j)                                                           (0x2704+(j)*32)
-#define NV91C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER                                                            31:0
-
-#define NV91C0_SET_SU_LD_ST_TARGET_C(j)                                                           (0x2708+(j)*32)
-#define NV91C0_SET_SU_LD_ST_TARGET_C_WIDTH                                                                   31:0
-
-#define NV91C0_SET_SU_LD_ST_TARGET_D(j)                                                           (0x270c+(j)*32)
-#define NV91C0_SET_SU_LD_ST_TARGET_D_HEIGHT                                                                  16:0
-#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY                                                       20:20
-#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR                                      0x00000000
-#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH                                            0x00000001
-
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT(j)                                                      (0x2710+(j)*32)
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE                                                                0:0
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR                                                   0x00000000
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA                                                    0x00000001
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR                                                              11:4
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED                                               0x00000000
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32                                    0x000000C0
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32                                    0x000000C1
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32                                    0x000000C2
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32                                     0x000000C3
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32                                     0x000000C4
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32                                     0x000000C5
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16                                        0x000000C6
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16                                    0x000000C7
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16                                    0x000000C8
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16                                    0x000000C9
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16                                    0x000000CA
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32                                              0x000000CB
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32                                              0x000000CC
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32                                              0x000000CD
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16                                     0x000000CE
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8                                               0x000000CF
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8                                            0x000000D0
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10                                            0x000000D1
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10                                        0x000000D2
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8                                               0x000000D5
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8                                            0x000000D6
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8                                           0x000000D7
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8                                           0x000000D8
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8                                           0x000000D9
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16                                                0x000000DA
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16                                              0x000000DB
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16                                              0x000000DC
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16                                              0x000000DD
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16                                              0x000000DE
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10                                            0x000000DF
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11                                           0x000000E0
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32                                                   0x000000E3
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32                                                   0x000000E4
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32                                                   0x000000E5
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8                                               0x000000E6
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8                                            0x000000E7
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5                                                 0x000000E8
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5                                               0x000000E9
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8                                                   0x000000EA
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8                                                 0x000000EB
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8                                                 0x000000EC
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8                                                 0x000000ED
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16                                                    0x000000EE
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16                                                   0x000000EF
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16                                                   0x000000F0
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16                                                   0x000000F1
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16                                                   0x000000F2
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8                                                     0x000000F3
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8                                                    0x000000F4
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8                                                    0x000000F5
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8                                                    0x000000F6
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8                                                     0x000000F7
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5                                               0x000000F8
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8                                               0x000000F9
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8                                            0x000000FA
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5                                               0x000000FB
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5                                               0x000000FC
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8                                               0x000000FD
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8                                               0x000000FE
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32                                                    0x000000FF
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16                                                    0x00000040
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16                                                   0x00000041
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32                                                   0x00000042
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8                                                   0x00000043
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16                                                0x00000044
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16                                              0x00000045
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32                                              0x00000046
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_B8G8R8A8                                               0x00000047
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA                                                              16:12
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16                                                     0x00000013
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8                                                   0x00000014
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24                                                   0x00000015
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24                                                   0x00000016
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24                                                   0x00000018
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32                                                    0x0000000A
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8                                              0x00000019
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8                                           0x0000001D
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8                                            0x0000001E
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8                                            0x0000001F
-#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT                                                        25:17
-
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j)                                                  (0x2714+(j)*32)
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH                                                           3:0
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB                                            0x00000000
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT                                                          7:4
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB                                           0x00000000
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS                                          0x00000001
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                         0x00000002
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                        0x00000003
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                      0x00000004
-#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                    0x00000005
-
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                2:0
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           6:4
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                               10:8
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                         14:12
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              18:16
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         22:20
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              26:24
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         30:28
-
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NV91C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NV91C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#define NV91C0_CALL_MME_MACRO(j)                                                                   (0x3800+(j)*8)
-#define NV91C0_CALL_MME_MACRO_V                                                                              31:0
-
-#define NV91C0_CALL_MME_DATA(j)                                                                    (0x3804+(j)*8)
-#define NV91C0_CALL_MME_DATA_V                                                                               31:0
-
-#endif /* _cl_fermi_compute_b_h_ */
diff --git a/Compute-Class-Methods/cla0c0.h b/Compute-Class-Methods/cla0c0.h
deleted file mode 100644
index e8677ad..0000000
--- a/Compute-Class-Methods/cla0c0.h
+++ /dev/null
@@ -1,836 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_kepler_compute_a_h_
-#define _cl_kepler_compute_a_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../class/bin/sw_header.pl kepler_compute_a */
-
-#include "nvtypes.h"
-
-#define KEPLER_COMPUTE_A    0xA0C0
-
-typedef volatile struct _cla0c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 Reserved_0x148[0x2];
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 Reserved_0x1E8[0x2];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 Reserved_0x200[0x4];
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 Reserved_0x218[0x1];
-    NvU32 InvalidateShaderCaches;
-    NvU32 Reserved_0x220[0x8];
-    NvU32 SetCwdControl;
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 Reserved_0x24C[0xA];
-    NvU32 InvalidateConstantBufferCacheA;
-    NvU32 InvalidateConstantBufferCacheB;
-    NvU32 InvalidateConstantBufferCacheC;
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 Reserved_0x28C[0x1];
-    NvU32 CheckQmdVersion;
-    NvU32 Reserved_0x294[0x7];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x9];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 SetShaderLocalMemoryThrottledA;
-    NvU32 SetShaderLocalMemoryThrottledB;
-    NvU32 SetShaderLocalMemoryThrottledC;
-    NvU32 Reserved_0x2FC[0x5];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x7B];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x7F];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 Reserved_0x780[0x4];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x17F];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x3B];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x86];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x29];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x20];
-    NvU32 SetShaderControl;
-    NvU32 Reserved_0x1694[0x1];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BE];
-    NvU32 SetBindlessTexture;
-    NvU32 SetTrapHandler;
-    NvU32 Reserved_0x2610[0x353];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 Reserved_0x33E0[0x8];
-    NvU32 SetMmeShadowScratch[0x8];
-} kepler_compute_a_t;
-
-
-#define NVA0C0_SET_OBJECT                                                                                  0x0000
-#define NVA0C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVA0C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVA0C0_NO_OPERATION                                                                                0x0100
-#define NVA0C0_NO_OPERATION_V                                                                                31:0
-
-#define NVA0C0_SET_NOTIFY_A                                                                                0x0104
-#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVA0C0_SET_NOTIFY_B                                                                                0x0108
-#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVA0C0_NOTIFY                                                                                      0x010c
-#define NVA0C0_NOTIFY_TYPE                                                                                   31:0
-#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVA0C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVA0C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVA0C0_SEND_GO_IDLE                                                                                0x013c
-#define NVA0C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVA0C0_PM_TRIGGER                                                                                  0x0140
-#define NVA0C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVA0C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVA0C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVA0C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVA0C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVA0C0_LINE_COUNT                                                                                  0x0184
-#define NVA0C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVA0C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVA0C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
-
-#define NVA0C0_OFFSET_OUT                                                                                  0x018c
-#define NVA0C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVA0C0_PITCH_OUT                                                                                   0x0190
-#define NVA0C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVA0C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVA0C0_SET_DST_WIDTH                                                                               0x0198
-#define NVA0C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVA0C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVA0C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVA0C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVA0C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVA0C0_SET_DST_LAYER                                                                               0x01a4
-#define NVA0C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVA0C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
-
-#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
-
-#define NVA0C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVA0C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVA0C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVA0C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVA0C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVA0C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVA0C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVA0C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVA0C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVA0C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVA0C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVA0C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVA0C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVA0C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVA0C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVA0C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NVA0C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVA0C0_SET_CWD_CONTROL                                                                             0x0240
-#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
-#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
-#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
-
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVA0C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVA0C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVA0C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
-
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
-
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
-#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
-
-#define NVA0C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVA0C0_SET_QMD_VERSION                                                                             0x0288
-#define NVA0C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVA0C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVA0C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVA0C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVA0C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVA0C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVA0C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVA0C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVA0C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVA0C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
-
-#define NVA0C0_SET_SPA_VERSION                                                                             0x0310
-#define NVA0C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVA0C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVA0C0_SET_FALCON00                                                                                0x0500
-#define NVA0C0_SET_FALCON00_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON01                                                                                0x0504
-#define NVA0C0_SET_FALCON01_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON02                                                                                0x0508
-#define NVA0C0_SET_FALCON02_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON03                                                                                0x050c
-#define NVA0C0_SET_FALCON03_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON04                                                                                0x0510
-#define NVA0C0_SET_FALCON04_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON05                                                                                0x0514
-#define NVA0C0_SET_FALCON05_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON06                                                                                0x0518
-#define NVA0C0_SET_FALCON06_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON07                                                                                0x051c
-#define NVA0C0_SET_FALCON07_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON08                                                                                0x0520
-#define NVA0C0_SET_FALCON08_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON09                                                                                0x0524
-#define NVA0C0_SET_FALCON09_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON10                                                                                0x0528
-#define NVA0C0_SET_FALCON10_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON11                                                                                0x052c
-#define NVA0C0_SET_FALCON11_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON12                                                                                0x0530
-#define NVA0C0_SET_FALCON12_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON13                                                                                0x0534
-#define NVA0C0_SET_FALCON13_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON14                                                                                0x0538
-#define NVA0C0_SET_FALCON14_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON15                                                                                0x053c
-#define NVA0C0_SET_FALCON15_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON16                                                                                0x0540
-#define NVA0C0_SET_FALCON16_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON17                                                                                0x0544
-#define NVA0C0_SET_FALCON17_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON18                                                                                0x0548
-#define NVA0C0_SET_FALCON18_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON19                                                                                0x054c
-#define NVA0C0_SET_FALCON19_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON20                                                                                0x0550
-#define NVA0C0_SET_FALCON20_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON21                                                                                0x0554
-#define NVA0C0_SET_FALCON21_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON22                                                                                0x0558
-#define NVA0C0_SET_FALCON22_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON23                                                                                0x055c
-#define NVA0C0_SET_FALCON23_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON24                                                                                0x0560
-#define NVA0C0_SET_FALCON24_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON25                                                                                0x0564
-#define NVA0C0_SET_FALCON25_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON26                                                                                0x0568
-#define NVA0C0_SET_FALCON26_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON27                                                                                0x056c
-#define NVA0C0_SET_FALCON27_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON28                                                                                0x0570
-#define NVA0C0_SET_FALCON28_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON29                                                                                0x0574
-#define NVA0C0_SET_FALCON29_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON30                                                                                0x0578
-#define NVA0C0_SET_FALCON30_V                                                                                31:0
-
-#define NVA0C0_SET_FALCON31                                                                                0x057c
-#define NVA0C0_SET_FALCON31_V                                                                                31:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
-
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVA0C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVA0C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVA0C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NVA0C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NVA0C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NVA0C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NVA0C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NVA0C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NVA0C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NVA0C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NVA0C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NVA0C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NVA0C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NVA0C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NVA0C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NVA0C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NVA0C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NVA0C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NVA0C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NVA0C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVA0C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVA0C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVA0C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVA0C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVA0C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVA0C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NVA0C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVA0C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVA0C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NVA0C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVA0C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVA0C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
-
-#define NVA0C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NVA0C0_SET_SHADER_CONTROL                                                                          0x1690
-#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
-#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
-#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
-
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVA0C0_PIPE_NOP                                                                                    0x1a2c
-#define NVA0C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVA0C0_SET_SPARE00                                                                                 0x1a30
-#define NVA0C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVA0C0_SET_SPARE01                                                                                 0x1a34
-#define NVA0C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVA0C0_SET_SPARE02                                                                                 0x1a38
-#define NVA0C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVA0C0_SET_SPARE03                                                                                 0x1a3c
-#define NVA0C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVA0C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVA0C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVA0C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVA0C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-
-#define NVA0C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVA0C0_SET_TRAP_HANDLER                                                                            0x260c
-#define NVA0C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
-
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVA0C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVA0C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_kepler_compute_a_h_ */
diff --git a/Compute-Class-Methods/cla1c0.h b/Compute-Class-Methods/cla1c0.h
deleted file mode 100644
index 37462b1..0000000
--- a/Compute-Class-Methods/cla1c0.h
+++ /dev/null
@@ -1,866 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_kepler_compute_b_h_
-#define _cl_kepler_compute_b_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../class/bin/sw_header.pl kepler_compute_b */
-
-#include "nvtypes.h"
-
-#define KEPLER_COMPUTE_B    0xA1C0
-
-typedef volatile struct _cla1c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 Reserved_0x148[0x2];
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 Reserved_0x1E8[0x2];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 SetValidSpanOverflowAreaA;
-    NvU32 SetValidSpanOverflowAreaB;
-    NvU32 SetValidSpanOverflowAreaC;
-    NvU32 SetCoalesceWaitingPeriodUnit;
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 Reserved_0x218[0x1];
-    NvU32 InvalidateShaderCaches;
-    NvU32 Reserved_0x220[0x8];
-    NvU32 SetCwdControl;
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 Reserved_0x24C[0xA];
-    NvU32 InvalidateConstantBufferCacheA;
-    NvU32 InvalidateConstantBufferCacheB;
-    NvU32 InvalidateConstantBufferCacheC;
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 Reserved_0x28C[0x1];
-    NvU32 CheckQmdVersion;
-    NvU32 Reserved_0x294[0x7];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x1];
-    NvU32 SetGlobalLoadViaTexture;
-    NvU32 Reserved_0x2C8[0x7];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 SetShaderLocalMemoryThrottledA;
-    NvU32 SetShaderLocalMemoryThrottledB;
-    NvU32 SetShaderLocalMemoryThrottledC;
-    NvU32 Reserved_0x2FC[0x5];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x7B];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x7F];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 Reserved_0x780[0x4];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x17F];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x3B];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x86];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x7];
-    NvU32 ActivatePerfSettingsForComputeContext;
-    NvU32 Reserved_0x12AC[0x21];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x20];
-    NvU32 SetShaderControl;
-    NvU32 Reserved_0x1694[0x1];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BE];
-    NvU32 SetBindlessTexture;
-    NvU32 SetTrapHandler;
-    NvU32 Reserved_0x2610[0x353];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 Reserved_0x33E0[0x8];
-    NvU32 SetMmeShadowScratch[0x8];
-} kepler_compute_b_t;
-
-
-#define NVA1C0_SET_OBJECT                                                                                  0x0000
-#define NVA1C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVA1C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVA1C0_NO_OPERATION                                                                                0x0100
-#define NVA1C0_NO_OPERATION_V                                                                                31:0
-
-#define NVA1C0_SET_NOTIFY_A                                                                                0x0104
-#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVA1C0_SET_NOTIFY_B                                                                                0x0108
-#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVA1C0_NOTIFY                                                                                      0x010c
-#define NVA1C0_NOTIFY_TYPE                                                                                   31:0
-#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVA1C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVA1C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVA1C0_SEND_GO_IDLE                                                                                0x013c
-#define NVA1C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVA1C0_PM_TRIGGER                                                                                  0x0140
-#define NVA1C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVA1C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVA1C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVA1C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVA1C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVA1C0_LINE_COUNT                                                                                  0x0184
-#define NVA1C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVA1C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVA1C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
-
-#define NVA1C0_OFFSET_OUT                                                                                  0x018c
-#define NVA1C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVA1C0_PITCH_OUT                                                                                   0x0190
-#define NVA1C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVA1C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVA1C0_SET_DST_WIDTH                                                                               0x0198
-#define NVA1C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVA1C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVA1C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVA1C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVA1C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVA1C0_SET_DST_LAYER                                                                               0x01a4
-#define NVA1C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVA1C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
-
-#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
-
-#define NVA1C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVA1C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVA1C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVA1C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVA1C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVA1C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVA1C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVA1C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVA1C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVA1C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVA1C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVA1C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVA1C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVA1C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
-#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
-
-#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
-#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
-
-#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
-#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
-
-#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
-#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
-
-#define NVA1C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVA1C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NVA1C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVA1C0_SET_CWD_CONTROL                                                                             0x0240
-#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
-#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
-#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
-
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVA1C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVA1C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVA1C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
-
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
-
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
-#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
-
-#define NVA1C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVA1C0_SET_QMD_VERSION                                                                             0x0288
-#define NVA1C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVA1C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVA1C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVA1C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVA1C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVA1C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVA1C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVA1C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVA1C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVA1C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE                                                                 0x02c4
-#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE                                                             0:0
-#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE                                                0x00000000
-#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE                                                 0x00000001
-#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX                                                      23:4
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
-
-#define NVA1C0_SET_SPA_VERSION                                                                             0x0310
-#define NVA1C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVA1C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVA1C0_SET_FALCON00                                                                                0x0500
-#define NVA1C0_SET_FALCON00_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON01                                                                                0x0504
-#define NVA1C0_SET_FALCON01_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON02                                                                                0x0508
-#define NVA1C0_SET_FALCON02_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON03                                                                                0x050c
-#define NVA1C0_SET_FALCON03_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON04                                                                                0x0510
-#define NVA1C0_SET_FALCON04_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON05                                                                                0x0514
-#define NVA1C0_SET_FALCON05_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON06                                                                                0x0518
-#define NVA1C0_SET_FALCON06_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON07                                                                                0x051c
-#define NVA1C0_SET_FALCON07_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON08                                                                                0x0520
-#define NVA1C0_SET_FALCON08_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON09                                                                                0x0524
-#define NVA1C0_SET_FALCON09_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON10                                                                                0x0528
-#define NVA1C0_SET_FALCON10_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON11                                                                                0x052c
-#define NVA1C0_SET_FALCON11_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON12                                                                                0x0530
-#define NVA1C0_SET_FALCON12_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON13                                                                                0x0534
-#define NVA1C0_SET_FALCON13_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON14                                                                                0x0538
-#define NVA1C0_SET_FALCON14_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON15                                                                                0x053c
-#define NVA1C0_SET_FALCON15_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON16                                                                                0x0540
-#define NVA1C0_SET_FALCON16_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON17                                                                                0x0544
-#define NVA1C0_SET_FALCON17_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON18                                                                                0x0548
-#define NVA1C0_SET_FALCON18_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON19                                                                                0x054c
-#define NVA1C0_SET_FALCON19_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON20                                                                                0x0550
-#define NVA1C0_SET_FALCON20_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON21                                                                                0x0554
-#define NVA1C0_SET_FALCON21_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON22                                                                                0x0558
-#define NVA1C0_SET_FALCON22_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON23                                                                                0x055c
-#define NVA1C0_SET_FALCON23_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON24                                                                                0x0560
-#define NVA1C0_SET_FALCON24_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON25                                                                                0x0564
-#define NVA1C0_SET_FALCON25_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON26                                                                                0x0568
-#define NVA1C0_SET_FALCON26_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON27                                                                                0x056c
-#define NVA1C0_SET_FALCON27_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON28                                                                                0x0570
-#define NVA1C0_SET_FALCON28_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON29                                                                                0x0574
-#define NVA1C0_SET_FALCON29_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON30                                                                                0x0578
-#define NVA1C0_SET_FALCON30_V                                                                                31:0
-
-#define NVA1C0_SET_FALCON31                                                                                0x057c
-#define NVA1C0_SET_FALCON31_V                                                                                31:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
-
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVA1C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVA1C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVA1C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NVA1C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NVA1C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NVA1C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NVA1C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NVA1C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NVA1C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NVA1C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NVA1C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NVA1C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NVA1C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NVA1C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NVA1C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NVA1C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NVA1C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NVA1C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NVA1C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NVA1C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
-#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
-#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
-#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
-
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVA1C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVA1C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVA1C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVA1C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVA1C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVA1C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NVA1C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVA1C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVA1C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NVA1C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVA1C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVA1C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
-
-#define NVA1C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NVA1C0_SET_SHADER_CONTROL                                                                          0x1690
-#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
-#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
-#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
-
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVA1C0_PIPE_NOP                                                                                    0x1a2c
-#define NVA1C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVA1C0_SET_SPARE00                                                                                 0x1a30
-#define NVA1C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVA1C0_SET_SPARE01                                                                                 0x1a34
-#define NVA1C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVA1C0_SET_SPARE02                                                                                 0x1a38
-#define NVA1C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVA1C0_SET_SPARE03                                                                                 0x1a3c
-#define NVA1C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVA1C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVA1C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVA1C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVA1C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-
-#define NVA1C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVA1C0_SET_TRAP_HANDLER                                                                            0x260c
-#define NVA1C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
-
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVA1C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVA1C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_kepler_compute_b_h_ */
diff --git a/Compute-Class-Methods/clb0c0.h b/Compute-Class-Methods/clb0c0.h
deleted file mode 100644
index 7f63b4a..0000000
--- a/Compute-Class-Methods/clb0c0.h
+++ /dev/null
@@ -1,931 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_maxwell_compute_a_h_
-#define _cl_maxwell_compute_a_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */
-
-#include "nvtypes.h"
-
-#define MAXWELL_COMPUTE_A    0xB0C0
-
-typedef volatile struct _clb0c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 Reserved_0x148[0x2];
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 Reserved_0x1E8[0x2];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 SetValidSpanOverflowAreaA;
-    NvU32 SetValidSpanOverflowAreaB;
-    NvU32 SetValidSpanOverflowAreaC;
-    NvU32 SetCoalesceWaitingPeriodUnit;
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 SetSelectMaxwellTextureHeaders;
-    NvU32 InvalidateShaderCaches;
-    NvU32 SetReservedSwMethod00;
-    NvU32 SetReservedSwMethod01;
-    NvU32 SetReservedSwMethod02;
-    NvU32 SetReservedSwMethod03;
-    NvU32 SetReservedSwMethod04;
-    NvU32 SetReservedSwMethod05;
-    NvU32 SetReservedSwMethod06;
-    NvU32 SetReservedSwMethod07;
-    NvU32 SetCwdControl;
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 SetReservedSwMethod08;
-    NvU32 SetReservedSwMethod09;
-    NvU32 SetReservedSwMethod10;
-    NvU32 SetReservedSwMethod11;
-    NvU32 SetReservedSwMethod12;
-    NvU32 SetReservedSwMethod13;
-    NvU32 SetReservedSwMethod14;
-    NvU32 SetReservedSwMethod15;
-    NvU32 Reserved_0x26C[0x2];
-    NvU32 InvalidateConstantBufferCacheA;
-    NvU32 InvalidateConstantBufferCacheB;
-    NvU32 InvalidateConstantBufferCacheC;
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 Reserved_0x28C[0x1];
-    NvU32 CheckQmdVersion;
-    NvU32 Reserved_0x294[0x7];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x9];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 SetShaderLocalMemoryThrottledA;
-    NvU32 SetShaderLocalMemoryThrottledB;
-    NvU32 SetShaderLocalMemoryThrottledC;
-    NvU32 Reserved_0x2FC[0x5];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x7B];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x7F];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 Reserved_0x780[0x4];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x17F];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x3B];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x86];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x7];
-    NvU32 ActivatePerfSettingsForComputeContext;
-    NvU32 Reserved_0x12AC[0x21];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x22];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BE];
-    NvU32 SetBindlessTexture;
-    NvU32 SetTrapHandler;
-    NvU32 Reserved_0x2610[0x34B];
-    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 StartShaderPerformanceCounter;
-    NvU32 StopShaderPerformanceCounter;
-    NvU32 Reserved_0x33E8[0x6];
-    NvU32 SetMmeShadowScratch[0x8];
-} maxwell_compute_a_t;
-
-
-#define NVB0C0_SET_OBJECT                                                                                  0x0000
-#define NVB0C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVB0C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVB0C0_NO_OPERATION                                                                                0x0100
-#define NVB0C0_NO_OPERATION_V                                                                                31:0
-
-#define NVB0C0_SET_NOTIFY_A                                                                                0x0104
-#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVB0C0_SET_NOTIFY_B                                                                                0x0108
-#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVB0C0_NOTIFY                                                                                      0x010c
-#define NVB0C0_NOTIFY_TYPE                                                                                   31:0
-#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVB0C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVB0C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVB0C0_SEND_GO_IDLE                                                                                0x013c
-#define NVB0C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVB0C0_PM_TRIGGER                                                                                  0x0140
-#define NVB0C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVB0C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVB0C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVB0C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVB0C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVB0C0_LINE_COUNT                                                                                  0x0184
-#define NVB0C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVB0C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVB0C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
-
-#define NVB0C0_OFFSET_OUT                                                                                  0x018c
-#define NVB0C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVB0C0_PITCH_OUT                                                                                   0x0190
-#define NVB0C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVB0C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVB0C0_SET_DST_WIDTH                                                                               0x0198
-#define NVB0C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVB0C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVB0C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVB0C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVB0C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVB0C0_SET_DST_LAYER                                                                               0x01a4
-#define NVB0C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVB0C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
-
-#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
-
-#define NVB0C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVB0C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVB0C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVB0C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVB0C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVB0C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVB0C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVB0C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVB0C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVB0C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVB0C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVB0C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVB0C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVB0C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
-#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
-
-#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
-#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
-
-#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
-#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
-
-#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
-#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
-
-#define NVB0C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVB0C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
-#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
-#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
-#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
-
-#define NVB0C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVB0C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
-#define NVB0C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
-#define NVB0C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
-#define NVB0C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
-#define NVB0C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
-#define NVB0C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
-#define NVB0C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
-#define NVB0C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
-#define NVB0C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
-
-#define NVB0C0_SET_CWD_CONTROL                                                                             0x0240
-#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
-#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
-#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
-
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVB0C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVB0C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVB0C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVB0C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
-#define NVB0C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
-#define NVB0C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
-#define NVB0C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
-#define NVB0C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
-#define NVB0C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
-#define NVB0C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
-#define NVB0C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
-
-#define NVB0C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
-#define NVB0C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
-
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
-
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
-
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
-#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
-
-#define NVB0C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVB0C0_SET_QMD_VERSION                                                                             0x0288
-#define NVB0C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVB0C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVB0C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVB0C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVB0C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVB0C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVB0C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVB0C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVB0C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVB0C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
-
-#define NVB0C0_SET_SPA_VERSION                                                                             0x0310
-#define NVB0C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVB0C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVB0C0_SET_FALCON00                                                                                0x0500
-#define NVB0C0_SET_FALCON00_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON01                                                                                0x0504
-#define NVB0C0_SET_FALCON01_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON02                                                                                0x0508
-#define NVB0C0_SET_FALCON02_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON03                                                                                0x050c
-#define NVB0C0_SET_FALCON03_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON04                                                                                0x0510
-#define NVB0C0_SET_FALCON04_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON05                                                                                0x0514
-#define NVB0C0_SET_FALCON05_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON06                                                                                0x0518
-#define NVB0C0_SET_FALCON06_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON07                                                                                0x051c
-#define NVB0C0_SET_FALCON07_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON08                                                                                0x0520
-#define NVB0C0_SET_FALCON08_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON09                                                                                0x0524
-#define NVB0C0_SET_FALCON09_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON10                                                                                0x0528
-#define NVB0C0_SET_FALCON10_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON11                                                                                0x052c
-#define NVB0C0_SET_FALCON11_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON12                                                                                0x0530
-#define NVB0C0_SET_FALCON12_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON13                                                                                0x0534
-#define NVB0C0_SET_FALCON13_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON14                                                                                0x0538
-#define NVB0C0_SET_FALCON14_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON15                                                                                0x053c
-#define NVB0C0_SET_FALCON15_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON16                                                                                0x0540
-#define NVB0C0_SET_FALCON16_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON17                                                                                0x0544
-#define NVB0C0_SET_FALCON17_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON18                                                                                0x0548
-#define NVB0C0_SET_FALCON18_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON19                                                                                0x054c
-#define NVB0C0_SET_FALCON19_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON20                                                                                0x0550
-#define NVB0C0_SET_FALCON20_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON21                                                                                0x0554
-#define NVB0C0_SET_FALCON21_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON22                                                                                0x0558
-#define NVB0C0_SET_FALCON22_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON23                                                                                0x055c
-#define NVB0C0_SET_FALCON23_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON24                                                                                0x0560
-#define NVB0C0_SET_FALCON24_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON25                                                                                0x0564
-#define NVB0C0_SET_FALCON25_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON26                                                                                0x0568
-#define NVB0C0_SET_FALCON26_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON27                                                                                0x056c
-#define NVB0C0_SET_FALCON27_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON28                                                                                0x0570
-#define NVB0C0_SET_FALCON28_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON29                                                                                0x0574
-#define NVB0C0_SET_FALCON29_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON30                                                                                0x0578
-#define NVB0C0_SET_FALCON30_V                                                                                31:0
-
-#define NVB0C0_SET_FALCON31                                                                                0x057c
-#define NVB0C0_SET_FALCON31_V                                                                                31:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
-
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVB0C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVB0C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVB0C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NVB0C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NVB0C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NVB0C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NVB0C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NVB0C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NVB0C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NVB0C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NVB0C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NVB0C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NVB0C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NVB0C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NVB0C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NVB0C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NVB0C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NVB0C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NVB0C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NVB0C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
-#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
-#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
-#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
-
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVB0C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVB0C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVB0C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVB0C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVB0C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVB0C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NVB0C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVB0C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVB0C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NVB0C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVB0C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVB0C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
-
-#define NVB0C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVB0C0_PIPE_NOP                                                                                    0x1a2c
-#define NVB0C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVB0C0_SET_SPARE00                                                                                 0x1a30
-#define NVB0C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVB0C0_SET_SPARE01                                                                                 0x1a34
-#define NVB0C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVB0C0_SET_SPARE02                                                                                 0x1a38
-#define NVB0C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVB0C0_SET_SPARE03                                                                                 0x1a3c
-#define NVB0C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVB0C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVB0C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVB0C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVB0C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-
-#define NVB0C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVB0C0_SET_TRAP_HANDLER                                                                            0x260c
-#define NVB0C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
-
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
-
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
-#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
-
-#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
-#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
-
-#define NVB0C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVB0C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_maxwell_compute_a_h_ */
diff --git a/Compute-Class-Methods/clb1c0.h b/Compute-Class-Methods/clb1c0.h
deleted file mode 100644
index ba5519d..0000000
--- a/Compute-Class-Methods/clb1c0.h
+++ /dev/null
@@ -1,968 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_maxwell_compute_b_h_
-#define _cl_maxwell_compute_b_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */
-
-#include "nvtypes.h"
-
-#define MAXWELL_COMPUTE_B    0xB1C0
-
-typedef volatile struct _clb1c0_tag0 {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 Reserved_0x148[0x2];
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 Reserved_0x1E8[0x2];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 SetValidSpanOverflowAreaA;
-    NvU32 SetValidSpanOverflowAreaB;
-    NvU32 SetValidSpanOverflowAreaC;
-    NvU32 SetCoalesceWaitingPeriodUnit;
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 SetSelectMaxwellTextureHeaders;
-    NvU32 InvalidateShaderCaches;
-    NvU32 SetReservedSwMethod00;
-    NvU32 SetReservedSwMethod01;
-    NvU32 SetReservedSwMethod02;
-    NvU32 SetReservedSwMethod03;
-    NvU32 SetReservedSwMethod04;
-    NvU32 SetReservedSwMethod05;
-    NvU32 SetReservedSwMethod06;
-    NvU32 SetReservedSwMethod07;
-    NvU32 SetCwdControl;
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 SetReservedSwMethod08;
-    NvU32 SetReservedSwMethod09;
-    NvU32 SetReservedSwMethod10;
-    NvU32 SetReservedSwMethod11;
-    NvU32 SetReservedSwMethod12;
-    NvU32 SetReservedSwMethod13;
-    NvU32 SetReservedSwMethod14;
-    NvU32 SetReservedSwMethod15;
-    NvU32 SetGwcScgType;
-    NvU32 SetScgControl;
-    NvU32 InvalidateConstantBufferCacheA;
-    NvU32 InvalidateConstantBufferCacheB;
-    NvU32 InvalidateConstantBufferCacheC;
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 SetWfiConfig;
-    NvU32 CheckQmdVersion;
-    NvU32 WaitForIdleScgType;
-    NvU32 InvalidateSkedCaches;
-    NvU32 SetScgRenderEnableControl;
-    NvU32 Reserved_0x2A0[0x4];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x9];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 SetShaderLocalMemoryThrottledA;
-    NvU32 SetShaderLocalMemoryThrottledB;
-    NvU32 SetShaderLocalMemoryThrottledC;
-    NvU32 Reserved_0x2FC[0x5];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x7B];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x7F];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 Reserved_0x780[0x4];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x17F];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x3B];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x67];
-    NvU32 InvalidateSamplerCacheAll;
-    NvU32 InvalidateTextureHeaderCacheAll;
-    NvU32 Reserved_0x1214[0x1D];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x7];
-    NvU32 ActivatePerfSettingsForComputeContext;
-    NvU32 Reserved_0x12AC[0x21];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x22];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BE];
-    NvU32 SetBindlessTexture;
-    NvU32 SetTrapHandler;
-    NvU32 Reserved_0x2610[0x34B];
-    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 StartShaderPerformanceCounter;
-    NvU32 StopShaderPerformanceCounter;
-    NvU32 Reserved_0x33E8[0x6];
-    NvU32 SetMmeShadowScratch[0x8];
-} maxwell_compute_b_t;
-
-
-#define NVB1C0_SET_OBJECT                                                                                  0x0000
-#define NVB1C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVB1C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVB1C0_NO_OPERATION                                                                                0x0100
-#define NVB1C0_NO_OPERATION_V                                                                                31:0
-
-#define NVB1C0_SET_NOTIFY_A                                                                                0x0104
-#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVB1C0_SET_NOTIFY_B                                                                                0x0108
-#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVB1C0_NOTIFY                                                                                      0x010c
-#define NVB1C0_NOTIFY_TYPE                                                                                   31:0
-#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVB1C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVB1C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVB1C0_SEND_GO_IDLE                                                                                0x013c
-#define NVB1C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVB1C0_PM_TRIGGER                                                                                  0x0140
-#define NVB1C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVB1C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVB1C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVB1C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVB1C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVB1C0_LINE_COUNT                                                                                  0x0184
-#define NVB1C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVB1C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVB1C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
-
-#define NVB1C0_OFFSET_OUT                                                                                  0x018c
-#define NVB1C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVB1C0_PITCH_OUT                                                                                   0x0190
-#define NVB1C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVB1C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVB1C0_SET_DST_WIDTH                                                                               0x0198
-#define NVB1C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVB1C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVB1C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVB1C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVB1C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVB1C0_SET_DST_LAYER                                                                               0x01a4
-#define NVB1C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVB1C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
-
-#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
-
-#define NVB1C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVB1C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVB1C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVB1C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVB1C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVB1C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVB1C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVB1C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVB1C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVB1C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVB1C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVB1C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVB1C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVB1C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
-#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
-
-#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
-#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
-
-#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
-#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
-
-#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
-#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
-
-#define NVB1C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVB1C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
-#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
-#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
-#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
-
-#define NVB1C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVB1C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
-#define NVB1C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
-#define NVB1C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
-#define NVB1C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
-#define NVB1C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
-#define NVB1C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
-#define NVB1C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
-#define NVB1C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
-#define NVB1C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
-
-#define NVB1C0_SET_CWD_CONTROL                                                                             0x0240
-#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
-#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
-#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
-
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVB1C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVB1C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVB1C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVB1C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
-#define NVB1C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
-#define NVB1C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
-#define NVB1C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
-#define NVB1C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
-#define NVB1C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
-#define NVB1C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
-#define NVB1C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
-
-#define NVB1C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
-#define NVB1C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
-
-#define NVB1C0_SET_GWC_SCG_TYPE                                                                            0x026c
-#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE                                                                      0:0
-#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0                                             0x00000000
-#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1                                                      0x00000001
-
-#define NVB1C0_SET_SCG_CONTROL                                                                             0x0270
-#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
-
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
-
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
-
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
-#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
-
-#define NVB1C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVB1C0_SET_QMD_VERSION                                                                             0x0288
-#define NVB1C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVB1C0_SET_WFI_CONFIG                                                                              0x028c
-#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI                                                             0:0
-#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE                                                0x00000000
-#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE                                                 0x00000001
-
-#define NVB1C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVB1C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE                                                                      0x0294
-#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V                                                                      31:0
-
-#define NVB1C0_INVALIDATE_SKED_CACHES                                                                      0x0298
-#define NVB1C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
-
-#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL                                                               0x029c
-#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE                                      0:0
-#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE                         0x00000000
-#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE                          0x00000001
-
-#define NVB1C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVB1C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVB1C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVB1C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVB1C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVB1C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVB1C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
-
-#define NVB1C0_SET_SPA_VERSION                                                                             0x0310
-#define NVB1C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVB1C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVB1C0_SET_FALCON00                                                                                0x0500
-#define NVB1C0_SET_FALCON00_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON01                                                                                0x0504
-#define NVB1C0_SET_FALCON01_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON02                                                                                0x0508
-#define NVB1C0_SET_FALCON02_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON03                                                                                0x050c
-#define NVB1C0_SET_FALCON03_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON04                                                                                0x0510
-#define NVB1C0_SET_FALCON04_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON05                                                                                0x0514
-#define NVB1C0_SET_FALCON05_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON06                                                                                0x0518
-#define NVB1C0_SET_FALCON06_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON07                                                                                0x051c
-#define NVB1C0_SET_FALCON07_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON08                                                                                0x0520
-#define NVB1C0_SET_FALCON08_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON09                                                                                0x0524
-#define NVB1C0_SET_FALCON09_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON10                                                                                0x0528
-#define NVB1C0_SET_FALCON10_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON11                                                                                0x052c
-#define NVB1C0_SET_FALCON11_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON12                                                                                0x0530
-#define NVB1C0_SET_FALCON12_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON13                                                                                0x0534
-#define NVB1C0_SET_FALCON13_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON14                                                                                0x0538
-#define NVB1C0_SET_FALCON14_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON15                                                                                0x053c
-#define NVB1C0_SET_FALCON15_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON16                                                                                0x0540
-#define NVB1C0_SET_FALCON16_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON17                                                                                0x0544
-#define NVB1C0_SET_FALCON17_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON18                                                                                0x0548
-#define NVB1C0_SET_FALCON18_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON19                                                                                0x054c
-#define NVB1C0_SET_FALCON19_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON20                                                                                0x0550
-#define NVB1C0_SET_FALCON20_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON21                                                                                0x0554
-#define NVB1C0_SET_FALCON21_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON22                                                                                0x0558
-#define NVB1C0_SET_FALCON22_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON23                                                                                0x055c
-#define NVB1C0_SET_FALCON23_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON24                                                                                0x0560
-#define NVB1C0_SET_FALCON24_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON25                                                                                0x0564
-#define NVB1C0_SET_FALCON25_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON26                                                                                0x0568
-#define NVB1C0_SET_FALCON26_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON27                                                                                0x056c
-#define NVB1C0_SET_FALCON27_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON28                                                                                0x0570
-#define NVB1C0_SET_FALCON28_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON29                                                                                0x0574
-#define NVB1C0_SET_FALCON29_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON30                                                                                0x0578
-#define NVB1C0_SET_FALCON30_V                                                                                31:0
-
-#define NVB1C0_SET_FALCON31                                                                                0x057c
-#define NVB1C0_SET_FALCON31_V                                                                                31:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
-
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVB1C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVB1C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVB1C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NVB1C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NVB1C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NVB1C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NVB1C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NVB1C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NVB1C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NVB1C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NVB1C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NVB1C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NVB1C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NVB1C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NVB1C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NVB1C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NVB1C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NVB1C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NVB1C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NVB1C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
-
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
-
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
-#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
-#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
-#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
-
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVB1C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVB1C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVB1C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVB1C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVB1C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVB1C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
-
-#define NVB1C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVB1C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVB1C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
-
-#define NVB1C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVB1C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVB1C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
-
-#define NVB1C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVB1C0_PIPE_NOP                                                                                    0x1a2c
-#define NVB1C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVB1C0_SET_SPARE00                                                                                 0x1a30
-#define NVB1C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVB1C0_SET_SPARE01                                                                                 0x1a34
-#define NVB1C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVB1C0_SET_SPARE02                                                                                 0x1a38
-#define NVB1C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVB1C0_SET_SPARE03                                                                                 0x1a3c
-#define NVB1C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVB1C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVB1C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVB1C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVB1C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-
-#define NVB1C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVB1C0_SET_TRAP_HANDLER                                                                            0x260c
-#define NVB1C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
-
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
-
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
-#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
-
-#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
-#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
-
-#define NVB1C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVB1C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_maxwell_compute_b_h_ */
diff --git a/Compute-Class-Methods/clc0c0.h b/Compute-Class-Methods/clc0c0.h
deleted file mode 100644
index ee090ec..0000000
--- a/Compute-Class-Methods/clc0c0.h
+++ /dev/null
@@ -1,1006 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_pascal_compute_a_h_
-#define _cl_pascal_compute_a_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */
-
-#include "nvtypes.h"
-
-#define PASCAL_COMPUTE_A    0xC0C0
-
-typedef volatile struct pascal_compute_a_struct {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 Reserved_0x148[0x2];
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 Reserved_0x1E8[0x2];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 SetValidSpanOverflowAreaA;
-    NvU32 SetValidSpanOverflowAreaB;
-    NvU32 SetValidSpanOverflowAreaC;
-    NvU32 SetCoalesceWaitingPeriodUnit;
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 SetSelectMaxwellTextureHeaders;
-    NvU32 InvalidateShaderCaches;
-    NvU32 SetReservedSwMethod00;
-    NvU32 SetReservedSwMethod01;
-    NvU32 SetReservedSwMethod02;
-    NvU32 SetReservedSwMethod03;
-    NvU32 SetReservedSwMethod04;
-    NvU32 SetReservedSwMethod05;
-    NvU32 SetReservedSwMethod06;
-    NvU32 SetReservedSwMethod07;
-    NvU32 SetCwdControl;
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 SetReservedSwMethod08;
-    NvU32 SetReservedSwMethod09;
-    NvU32 SetReservedSwMethod10;
-    NvU32 SetReservedSwMethod11;
-    NvU32 SetReservedSwMethod12;
-    NvU32 SetReservedSwMethod13;
-    NvU32 SetReservedSwMethod14;
-    NvU32 SetReservedSwMethod15;
-    NvU32 SetGwcScgType;
-    NvU32 SetScgControl;
-    NvU32 InvalidateConstantBufferCacheA;
-    NvU32 InvalidateConstantBufferCacheB;
-    NvU32 InvalidateConstantBufferCacheC;
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 SetWfiConfig;
-    NvU32 CheckQmdVersion;
-    NvU32 WaitForIdleScgType;
-    NvU32 InvalidateSkedCaches;
-    NvU32 SetScgRenderEnableControl;
-    NvU32 SetShaderSharedMemoryWindowA;
-    NvU32 SetShaderSharedMemoryWindowB;
-    NvU32 Reserved_0x2A8[0x2];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x9];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 SetShaderLocalMemoryThrottledA;
-    NvU32 SetShaderLocalMemoryThrottledB;
-    NvU32 SetShaderLocalMemoryThrottledC;
-    NvU32 Reserved_0x2FC[0x5];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x1];
-    NvU32 SetInlineQmdAddressA;
-    NvU32 SetInlineQmdAddressB;
-    NvU32 LoadInlineQmdData[0x40];
-    NvU32 Reserved_0x420[0x38];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x7F];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 Reserved_0x780[0x4];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x6];
-    NvU32 SetShaderLocalMemoryWindowA;
-    NvU32 SetShaderLocalMemoryWindowB;
-    NvU32 Reserved_0x7B8[0x177];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x3B];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x67];
-    NvU32 InvalidateSamplerCacheAll;
-    NvU32 InvalidateTextureHeaderCacheAll;
-    NvU32 Reserved_0x1214[0x1D];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x7];
-    NvU32 ActivatePerfSettingsForComputeContext;
-    NvU32 Reserved_0x12AC[0x21];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x22];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BE];
-    NvU32 SetBindlessTexture;
-    NvU32 SetTrapHandler;
-    NvU32 Reserved_0x2610[0x34B];
-    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 StartShaderPerformanceCounter;
-    NvU32 StopShaderPerformanceCounter;
-    NvU32 SetShaderPerformanceCounterSctlFilter;
-    NvU32 SetShaderPerformanceCounterCoreMioFilter;
-    NvU32 Reserved_0x33F0[0x4];
-    NvU32 SetMmeShadowScratch[0x8];
-} pascal_compute_a_t;
-
-
-#define NVC0C0_SET_OBJECT                                                                                  0x0000
-#define NVC0C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVC0C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVC0C0_NO_OPERATION                                                                                0x0100
-#define NVC0C0_NO_OPERATION_V                                                                                31:0
-
-#define NVC0C0_SET_NOTIFY_A                                                                                0x0104
-#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVC0C0_SET_NOTIFY_B                                                                                0x0108
-#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVC0C0_NOTIFY                                                                                      0x010c
-#define NVC0C0_NOTIFY_TYPE                                                                                   31:0
-#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVC0C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVC0C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVC0C0_SEND_GO_IDLE                                                                                0x013c
-#define NVC0C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVC0C0_PM_TRIGGER                                                                                  0x0140
-#define NVC0C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVC0C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVC0C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVC0C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVC0C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVC0C0_LINE_COUNT                                                                                  0x0184
-#define NVC0C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVC0C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVC0C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
-
-#define NVC0C0_OFFSET_OUT                                                                                  0x018c
-#define NVC0C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVC0C0_PITCH_OUT                                                                                   0x0190
-#define NVC0C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVC0C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVC0C0_SET_DST_WIDTH                                                                               0x0198
-#define NVC0C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVC0C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVC0C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVC0C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVC0C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVC0C0_SET_DST_LAYER                                                                               0x01a4
-#define NVC0C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVC0C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
-
-#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
-
-#define NVC0C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVC0C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVC0C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVC0C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC0C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC0C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVC0C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVC0C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVC0C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVC0C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVC0C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVC0C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVC0C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVC0C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
-#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
-
-#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
-#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
-
-#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
-#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
-
-#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
-#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
-
-#define NVC0C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVC0C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
-#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
-#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
-#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
-
-#define NVC0C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVC0C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
-#define NVC0C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
-#define NVC0C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
-#define NVC0C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
-#define NVC0C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
-#define NVC0C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
-#define NVC0C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
-#define NVC0C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
-#define NVC0C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
-
-#define NVC0C0_SET_CWD_CONTROL                                                                             0x0240
-#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
-#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
-#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
-
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVC0C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVC0C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVC0C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVC0C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
-#define NVC0C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
-#define NVC0C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
-#define NVC0C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
-#define NVC0C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
-#define NVC0C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
-#define NVC0C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
-#define NVC0C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
-
-#define NVC0C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
-#define NVC0C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
-
-#define NVC0C0_SET_GWC_SCG_TYPE                                                                            0x026c
-#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE                                                                      0:0
-#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0                                             0x00000000
-#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1                                                      0x00000001
-
-#define NVC0C0_SET_SCG_CONTROL                                                                             0x0270
-#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
-
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                              16:0
-
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
-
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
-#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
-
-#define NVC0C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVC0C0_SET_QMD_VERSION                                                                             0x0288
-#define NVC0C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVC0C0_SET_WFI_CONFIG                                                                              0x028c
-#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI                                                             0:0
-#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE                                                0x00000000
-#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE                                                 0x00000001
-
-#define NVC0C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVC0C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE                                                                      0x0294
-#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V                                                                      31:0
-
-#define NVC0C0_INVALIDATE_SKED_CACHES                                                                      0x0298
-#define NVC0C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
-
-#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL                                                               0x029c
-#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE                                      0:0
-#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE                         0x00000000
-#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE                          0x00000001
-
-#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
-#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
-
-#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
-#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
-
-#define NVC0C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVC0C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVC0C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVC0C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVC0C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVC0C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVC0C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
-
-#define NVC0C0_SET_SPA_VERSION                                                                             0x0310
-#define NVC0C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVC0C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVC0C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
-#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
-
-#define NVC0C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
-#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
-
-#define NVC0C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
-#define NVC0C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
-
-#define NVC0C0_SET_FALCON00                                                                                0x0500
-#define NVC0C0_SET_FALCON00_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON01                                                                                0x0504
-#define NVC0C0_SET_FALCON01_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON02                                                                                0x0508
-#define NVC0C0_SET_FALCON02_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON03                                                                                0x050c
-#define NVC0C0_SET_FALCON03_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON04                                                                                0x0510
-#define NVC0C0_SET_FALCON04_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON05                                                                                0x0514
-#define NVC0C0_SET_FALCON05_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON06                                                                                0x0518
-#define NVC0C0_SET_FALCON06_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON07                                                                                0x051c
-#define NVC0C0_SET_FALCON07_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON08                                                                                0x0520
-#define NVC0C0_SET_FALCON08_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON09                                                                                0x0524
-#define NVC0C0_SET_FALCON09_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON10                                                                                0x0528
-#define NVC0C0_SET_FALCON10_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON11                                                                                0x052c
-#define NVC0C0_SET_FALCON11_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON12                                                                                0x0530
-#define NVC0C0_SET_FALCON12_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON13                                                                                0x0534
-#define NVC0C0_SET_FALCON13_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON14                                                                                0x0538
-#define NVC0C0_SET_FALCON14_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON15                                                                                0x053c
-#define NVC0C0_SET_FALCON15_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON16                                                                                0x0540
-#define NVC0C0_SET_FALCON16_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON17                                                                                0x0544
-#define NVC0C0_SET_FALCON17_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON18                                                                                0x0548
-#define NVC0C0_SET_FALCON18_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON19                                                                                0x054c
-#define NVC0C0_SET_FALCON19_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON20                                                                                0x0550
-#define NVC0C0_SET_FALCON20_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON21                                                                                0x0554
-#define NVC0C0_SET_FALCON21_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON22                                                                                0x0558
-#define NVC0C0_SET_FALCON22_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON23                                                                                0x055c
-#define NVC0C0_SET_FALCON23_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON24                                                                                0x0560
-#define NVC0C0_SET_FALCON24_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON25                                                                                0x0564
-#define NVC0C0_SET_FALCON25_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON26                                                                                0x0568
-#define NVC0C0_SET_FALCON26_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON27                                                                                0x056c
-#define NVC0C0_SET_FALCON27_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON28                                                                                0x0570
-#define NVC0C0_SET_FALCON28_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON29                                                                                0x0574
-#define NVC0C0_SET_FALCON29_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON30                                                                                0x0578
-#define NVC0C0_SET_FALCON30_V                                                                                31:0
-
-#define NVC0C0_SET_FALCON31                                                                                0x057c
-#define NVC0C0_SET_FALCON31_V                                                                                31:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
-
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
-#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
-
-#define NVC0C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVC0C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVC0C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NVC0C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NVC0C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NVC0C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NVC0C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NVC0C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NVC0C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NVC0C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NVC0C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NVC0C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NVC0C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NVC0C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NVC0C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NVC0C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NVC0C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NVC0C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NVC0C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NVC0C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
-
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
-
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
-#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
-#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
-#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
-
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVC0C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVC0C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC0C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC0C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVC0C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVC0C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
-
-#define NVC0C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVC0C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVC0C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
-
-#define NVC0C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVC0C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVC0C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                            16:0
-
-#define NVC0C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVC0C0_PIPE_NOP                                                                                    0x1a2c
-#define NVC0C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVC0C0_SET_SPARE00                                                                                 0x1a30
-#define NVC0C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVC0C0_SET_SPARE01                                                                                 0x1a34
-#define NVC0C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVC0C0_SET_SPARE02                                                                                 0x1a38
-#define NVC0C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVC0C0_SET_SPARE03                                                                                 0x1a3c
-#define NVC0C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVC0C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVC0C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVC0C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVC0C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-
-#define NVC0C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVC0C0_SET_TRAP_HANDLER                                                                            0x260c
-#define NVC0C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
-#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
-
-#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
-#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
-
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
-#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
-
-#define NVC0C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVC0C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_pascal_compute_a_h_ */
diff --git a/Compute-Class-Methods/clc1c0.h b/Compute-Class-Methods/clc1c0.h
deleted file mode 100644
index e5d824f..0000000
--- a/Compute-Class-Methods/clc1c0.h
+++ /dev/null
@@ -1,1026 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_pascal_compute_b_h_
-#define _cl_pascal_compute_b_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */
-
-#include "nvtypes.h"
-
-#define PASCAL_COMPUTE_B    0xC1C0
-
-typedef volatile struct pascal_compute_b_struct {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 FeAtomicSequenceBegin;
-    NvU32 FeAtomicSequenceEnd;
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 Reserved_0x1E8[0x2];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 SetValidSpanOverflowAreaA;
-    NvU32 SetValidSpanOverflowAreaB;
-    NvU32 SetValidSpanOverflowAreaC;
-    NvU32 SetCoalesceWaitingPeriodUnit;
-    NvU32 PerfmonTransfer;
-    NvU32 SetShaderSharedMemoryWindow;
-    NvU32 SetSelectMaxwellTextureHeaders;
-    NvU32 InvalidateShaderCaches;
-    NvU32 SetReservedSwMethod00;
-    NvU32 SetReservedSwMethod01;
-    NvU32 SetReservedSwMethod02;
-    NvU32 SetReservedSwMethod03;
-    NvU32 SetReservedSwMethod04;
-    NvU32 SetReservedSwMethod05;
-    NvU32 SetReservedSwMethod06;
-    NvU32 SetReservedSwMethod07;
-    NvU32 SetCwdControl;
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 SetReservedSwMethod08;
-    NvU32 SetReservedSwMethod09;
-    NvU32 SetReservedSwMethod10;
-    NvU32 SetReservedSwMethod11;
-    NvU32 SetReservedSwMethod12;
-    NvU32 SetReservedSwMethod13;
-    NvU32 SetReservedSwMethod14;
-    NvU32 SetReservedSwMethod15;
-    NvU32 SetGwcScgType;
-    NvU32 SetScgControl;
-    NvU32 InvalidateConstantBufferCacheA;
-    NvU32 InvalidateConstantBufferCacheB;
-    NvU32 InvalidateConstantBufferCacheC;
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 SetWfiConfig;
-    NvU32 CheckQmdVersion;
-    NvU32 WaitForIdleScgType;
-    NvU32 InvalidateSkedCaches;
-    NvU32 SetScgRenderEnableControl;
-    NvU32 SetShaderSharedMemoryWindowA;
-    NvU32 SetShaderSharedMemoryWindowB;
-    NvU32 ScgHysteresisControl;
-    NvU32 Reserved_0x2AC[0x1];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x9];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 SetShaderLocalMemoryThrottledA;
-    NvU32 SetShaderLocalMemoryThrottledB;
-    NvU32 SetShaderLocalMemoryThrottledC;
-    NvU32 Reserved_0x2FC[0x5];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x1];
-    NvU32 SetInlineQmdAddressA;
-    NvU32 SetInlineQmdAddressB;
-    NvU32 LoadInlineQmdData[0x40];
-    NvU32 Reserved_0x420[0x38];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x7F];
-    NvU32 SetShaderLocalMemoryWindow;
-    NvU32 Reserved_0x780[0x4];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x6];
-    NvU32 SetShaderLocalMemoryWindowA;
-    NvU32 SetShaderLocalMemoryWindowB;
-    NvU32 Reserved_0x7B8[0x177];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x57];
-    NvU32 SetSpareNoop12;
-    NvU32 SetSpareNoop13;
-    NvU32 SetSpareNoop14;
-    NvU32 SetSpareNoop15;
-    NvU32 Reserved_0xF54[0x3B];
-    NvU32 SetSpareNoop00;
-    NvU32 SetSpareNoop01;
-    NvU32 SetSpareNoop02;
-    NvU32 SetSpareNoop03;
-    NvU32 SetSpareNoop04;
-    NvU32 SetSpareNoop05;
-    NvU32 SetSpareNoop06;
-    NvU32 SetSpareNoop07;
-    NvU32 SetSpareNoop08;
-    NvU32 SetSpareNoop09;
-    NvU32 SetSpareNoop10;
-    NvU32 SetSpareNoop11;
-    NvU32 Reserved_0x1070[0x67];
-    NvU32 InvalidateSamplerCacheAll;
-    NvU32 InvalidateTextureHeaderCacheAll;
-    NvU32 Reserved_0x1214[0x1D];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x7];
-    NvU32 ActivatePerfSettingsForComputeContext;
-    NvU32 Reserved_0x12AC[0x21];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x22];
-    NvU32 SetProgramRegionA;
-    NvU32 SetProgramRegionB;
-    NvU32 Reserved_0x1610[0x22];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A24[0x1];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BE];
-    NvU32 SetBindlessTexture;
-    NvU32 SetTrapHandler;
-    NvU32 Reserved_0x2610[0x34B];
-    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 StartShaderPerformanceCounter;
-    NvU32 StopShaderPerformanceCounter;
-    NvU32 SetShaderPerformanceCounterSctlFilter;
-    NvU32 SetShaderPerformanceCounterCoreMioFilter;
-    NvU32 Reserved_0x33F0[0x4];
-    NvU32 SetMmeShadowScratch[0x8];
-} pascal_compute_b_t;
-
-
-#define NVC1C0_SET_OBJECT                                                                                  0x0000
-#define NVC1C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVC1C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVC1C0_NO_OPERATION                                                                                0x0100
-#define NVC1C0_NO_OPERATION_V                                                                                31:0
-
-#define NVC1C0_SET_NOTIFY_A                                                                                0x0104
-#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVC1C0_SET_NOTIFY_B                                                                                0x0108
-#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVC1C0_NOTIFY                                                                                      0x010c
-#define NVC1C0_NOTIFY_TYPE                                                                                   31:0
-#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVC1C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVC1C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVC1C0_SEND_GO_IDLE                                                                                0x013c
-#define NVC1C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVC1C0_PM_TRIGGER                                                                                  0x0140
-#define NVC1C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVC1C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVC1C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN                                                                    0x0148
-#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V                                                                    31:0
-
-#define NVC1C0_FE_ATOMIC_SEQUENCE_END                                                                      0x014c
-#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V                                                                      31:0
-
-#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVC1C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVC1C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVC1C0_LINE_COUNT                                                                                  0x0184
-#define NVC1C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVC1C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVC1C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
-
-#define NVC1C0_OFFSET_OUT                                                                                  0x018c
-#define NVC1C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVC1C0_PITCH_OUT                                                                                   0x0190
-#define NVC1C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVC1C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVC1C0_SET_DST_WIDTH                                                                               0x0198
-#define NVC1C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVC1C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVC1C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVC1C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVC1C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVC1C0_SET_DST_LAYER                                                                               0x01a4
-#define NVC1C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVC1C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
-
-#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
-
-#define NVC1C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVC1C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVC1C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVC1C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC1C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC1C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVC1C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVC1C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVC1C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVC1C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVC1C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVC1C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVC1C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVC1C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
-#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
-
-#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
-#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
-
-#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
-#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
-
-#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
-#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
-
-#define NVC1C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVC1C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
-#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
-
-#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
-#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
-#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
-#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
-
-#define NVC1C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVC1C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
-#define NVC1C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
-#define NVC1C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
-#define NVC1C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
-#define NVC1C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
-#define NVC1C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
-#define NVC1C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
-#define NVC1C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
-#define NVC1C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
-
-#define NVC1C0_SET_CWD_CONTROL                                                                             0x0240
-#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
-#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
-#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
-
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVC1C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVC1C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVC1C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVC1C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
-#define NVC1C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
-#define NVC1C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
-#define NVC1C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
-#define NVC1C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
-#define NVC1C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
-#define NVC1C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
-#define NVC1C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
-
-#define NVC1C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
-#define NVC1C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
-
-#define NVC1C0_SET_GWC_SCG_TYPE                                                                            0x026c
-#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE                                                                      0:0
-#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0                                             0x00000000
-#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1                                                      0x00000001
-
-#define NVC1C0_SET_SCG_CONTROL                                                                             0x0270
-#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
-#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT                                                        20:12
-#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE                                        24:24
-#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE                             0x00000000
-#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE                              0x00000001
-
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                              16:0
-
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
-
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
-#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
-
-#define NVC1C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVC1C0_SET_QMD_VERSION                                                                             0x0288
-#define NVC1C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVC1C0_SET_WFI_CONFIG                                                                              0x028c
-#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI                                                             0:0
-#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE                                                0x00000000
-#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE                                                 0x00000001
-
-#define NVC1C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVC1C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE                                                                      0x0294
-#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V                                                                      31:0
-
-#define NVC1C0_INVALIDATE_SKED_CACHES                                                                      0x0298
-#define NVC1C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
-
-#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL                                                               0x029c
-#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE                                      0:0
-#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE                         0x00000000
-#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE                          0x00000001
-
-#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
-#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
-
-#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
-#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
-
-#define NVC1C0_SCG_HYSTERESIS_CONTROL                                                                      0x02a8
-#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE                                                        0:0
-#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE                                           0x00000000
-#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE                                            0x00000001
-#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE                                                   1:1
-#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE                                      0x00000000
-#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE                                       0x00000001
-
-#define NVC1C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVC1C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVC1C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVC1C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVC1C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVC1C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVC1C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
-
-#define NVC1C0_SET_SPA_VERSION                                                                             0x0310
-#define NVC1C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVC1C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVC1C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
-#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
-
-#define NVC1C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
-#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
-
-#define NVC1C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
-#define NVC1C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
-
-#define NVC1C0_SET_FALCON00                                                                                0x0500
-#define NVC1C0_SET_FALCON00_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON01                                                                                0x0504
-#define NVC1C0_SET_FALCON01_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON02                                                                                0x0508
-#define NVC1C0_SET_FALCON02_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON03                                                                                0x050c
-#define NVC1C0_SET_FALCON03_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON04                                                                                0x0510
-#define NVC1C0_SET_FALCON04_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON05                                                                                0x0514
-#define NVC1C0_SET_FALCON05_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON06                                                                                0x0518
-#define NVC1C0_SET_FALCON06_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON07                                                                                0x051c
-#define NVC1C0_SET_FALCON07_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON08                                                                                0x0520
-#define NVC1C0_SET_FALCON08_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON09                                                                                0x0524
-#define NVC1C0_SET_FALCON09_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON10                                                                                0x0528
-#define NVC1C0_SET_FALCON10_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON11                                                                                0x052c
-#define NVC1C0_SET_FALCON11_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON12                                                                                0x0530
-#define NVC1C0_SET_FALCON12_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON13                                                                                0x0534
-#define NVC1C0_SET_FALCON13_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON14                                                                                0x0538
-#define NVC1C0_SET_FALCON14_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON15                                                                                0x053c
-#define NVC1C0_SET_FALCON15_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON16                                                                                0x0540
-#define NVC1C0_SET_FALCON16_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON17                                                                                0x0544
-#define NVC1C0_SET_FALCON17_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON18                                                                                0x0548
-#define NVC1C0_SET_FALCON18_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON19                                                                                0x054c
-#define NVC1C0_SET_FALCON19_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON20                                                                                0x0550
-#define NVC1C0_SET_FALCON20_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON21                                                                                0x0554
-#define NVC1C0_SET_FALCON21_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON22                                                                                0x0558
-#define NVC1C0_SET_FALCON22_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON23                                                                                0x055c
-#define NVC1C0_SET_FALCON23_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON24                                                                                0x0560
-#define NVC1C0_SET_FALCON24_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON25                                                                                0x0564
-#define NVC1C0_SET_FALCON25_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON26                                                                                0x0568
-#define NVC1C0_SET_FALCON26_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON27                                                                                0x056c
-#define NVC1C0_SET_FALCON27_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON28                                                                                0x0570
-#define NVC1C0_SET_FALCON28_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON29                                                                                0x0574
-#define NVC1C0_SET_FALCON29_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON30                                                                                0x0578
-#define NVC1C0_SET_FALCON30_V                                                                                31:0
-
-#define NVC1C0_SET_FALCON31                                                                                0x057c
-#define NVC1C0_SET_FALCON31_V                                                                                31:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
-
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
-#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
-
-#define NVC1C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVC1C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVC1C0_SET_SPARE_NOOP12                                                                            0x0f44
-#define NVC1C0_SET_SPARE_NOOP12_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP13                                                                            0x0f48
-#define NVC1C0_SET_SPARE_NOOP13_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP14                                                                            0x0f4c
-#define NVC1C0_SET_SPARE_NOOP14_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP15                                                                            0x0f50
-#define NVC1C0_SET_SPARE_NOOP15_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP00                                                                            0x1040
-#define NVC1C0_SET_SPARE_NOOP00_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP01                                                                            0x1044
-#define NVC1C0_SET_SPARE_NOOP01_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP02                                                                            0x1048
-#define NVC1C0_SET_SPARE_NOOP02_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP03                                                                            0x104c
-#define NVC1C0_SET_SPARE_NOOP03_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP04                                                                            0x1050
-#define NVC1C0_SET_SPARE_NOOP04_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP05                                                                            0x1054
-#define NVC1C0_SET_SPARE_NOOP05_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP06                                                                            0x1058
-#define NVC1C0_SET_SPARE_NOOP06_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP07                                                                            0x105c
-#define NVC1C0_SET_SPARE_NOOP07_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP08                                                                            0x1060
-#define NVC1C0_SET_SPARE_NOOP08_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP09                                                                            0x1064
-#define NVC1C0_SET_SPARE_NOOP09_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP10                                                                            0x1068
-#define NVC1C0_SET_SPARE_NOOP10_V                                                                            31:0
-
-#define NVC1C0_SET_SPARE_NOOP11                                                                            0x106c
-#define NVC1C0_SET_SPARE_NOOP11_V                                                                            31:0
-
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
-
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
-
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
-#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
-#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
-#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
-
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVC1C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVC1C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC1C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC1C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVC1C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVC1C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
-
-#define NVC1C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVC1C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVC1C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
-
-#define NVC1C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVC1C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVC1C0_SET_PROGRAM_REGION_A                                                                        0x1608
-#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                            16:0
-
-#define NVC1C0_SET_PROGRAM_REGION_B                                                                        0x160c
-#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
-
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVC1C0_PIPE_NOP                                                                                    0x1a2c
-#define NVC1C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVC1C0_SET_SPARE00                                                                                 0x1a30
-#define NVC1C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVC1C0_SET_SPARE01                                                                                 0x1a34
-#define NVC1C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVC1C0_SET_SPARE02                                                                                 0x1a38
-#define NVC1C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVC1C0_SET_SPARE03                                                                                 0x1a3c
-#define NVC1C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVC1C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVC1C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVC1C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVC1C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-
-#define NVC1C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVC1C0_SET_TRAP_HANDLER                                                                            0x260c
-#define NVC1C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
-#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
-
-#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
-#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
-
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
-#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
-
-#define NVC1C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVC1C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_pascal_compute_b_h_ */
diff --git a/Compute-Class-Methods/clc3c0.h b/Compute-Class-Methods/clc3c0.h
deleted file mode 100644
index c70a44f..0000000
--- a/Compute-Class-Methods/clc3c0.h
+++ /dev/null
@@ -1,912 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_volta_compute_a_h_
-#define _cl_volta_compute_a_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */
-
-#include "nvtypes.h"
-
-#define VOLTA_COMPUTE_A    0xC3C0
-
-typedef volatile struct volta_compute_a_struct {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 FeAtomicSequenceBegin;
-    NvU32 FeAtomicSequenceEnd;
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 Reserved_0x1E8[0x2];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 SetValidSpanOverflowAreaA;
-    NvU32 SetValidSpanOverflowAreaB;
-    NvU32 SetValidSpanOverflowAreaC;
-    NvU32 Reserved_0x20C[0x1];
-    NvU32 PerfmonTransfer;
-    NvU32 Reserved_0x214[0x2];
-    NvU32 InvalidateShaderCaches;
-    NvU32 SetReservedSwMethod00;
-    NvU32 SetReservedSwMethod01;
-    NvU32 SetReservedSwMethod02;
-    NvU32 SetReservedSwMethod03;
-    NvU32 SetReservedSwMethod04;
-    NvU32 SetReservedSwMethod05;
-    NvU32 SetReservedSwMethod06;
-    NvU32 SetReservedSwMethod07;
-    NvU32 Reserved_0x240[0x1];
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 SetReservedSwMethod08;
-    NvU32 SetReservedSwMethod09;
-    NvU32 SetReservedSwMethod10;
-    NvU32 SetReservedSwMethod11;
-    NvU32 SetReservedSwMethod12;
-    NvU32 SetReservedSwMethod13;
-    NvU32 SetReservedSwMethod14;
-    NvU32 SetReservedSwMethod15;
-    NvU32 Reserved_0x26C[0x1];
-    NvU32 SetScgControl;
-    NvU32 Reserved_0x274[0x3];
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 Reserved_0x28C[0x1];
-    NvU32 CheckQmdVersion;
-    NvU32 Reserved_0x294[0x1];
-    NvU32 InvalidateSkedCaches;
-    NvU32 Reserved_0x29C[0x1];
-    NvU32 SetShaderSharedMemoryWindowA;
-    NvU32 SetShaderSharedMemoryWindowB;
-    NvU32 ScgHysteresisControl;
-    NvU32 Reserved_0x2AC[0x1];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x3];
-    NvU32 SetSkedCacheControl;
-    NvU32 Reserved_0x2D0[0x5];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 Reserved_0x2F0[0x8];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x1];
-    NvU32 SetInlineQmdAddressA;
-    NvU32 SetInlineQmdAddressB;
-    NvU32 LoadInlineQmdData[0x40];
-    NvU32 Reserved_0x420[0x38];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x84];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x6];
-    NvU32 SetShaderLocalMemoryWindowA;
-    NvU32 SetShaderLocalMemoryWindowB;
-    NvU32 Reserved_0x7B8[0x177];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x13];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x109];
-    NvU32 InvalidateSamplerCacheAll;
-    NvU32 InvalidateTextureHeaderCacheAll;
-    NvU32 Reserved_0x1214[0x1D];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x7];
-    NvU32 ActivatePerfSettingsForComputeContext;
-    NvU32 Reserved_0x12AC[0x21];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x46];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BA];
-    NvU32 SetTrapHandlerA;
-    NvU32 SetTrapHandlerB;
-    NvU32 Reserved_0x2600[0x2];
-    NvU32 SetBindlessTexture;
-    NvU32 Reserved_0x260C[0x33A];
-    NvU32 SetShaderPerformanceSnapshotCounterValue[0x8];
-    NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8];
-    NvU32 EnableShaderPerformanceSnapshotCounter;
-    NvU32 DisableShaderPerformanceSnapshotCounter;
-    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 StartShaderPerformanceCounter;
-    NvU32 StopShaderPerformanceCounter;
-    NvU32 SetShaderPerformanceCounterSctlFilter;
-    NvU32 SetShaderPerformanceCounterCoreMioFilter;
-    NvU32 Reserved_0x33F0[0x4];
-    NvU32 SetMmeShadowScratch[0x8];
-} volta_compute_a_t;
-
-
-#define NVC3C0_SET_OBJECT                                                                                  0x0000
-#define NVC3C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVC3C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVC3C0_NO_OPERATION                                                                                0x0100
-#define NVC3C0_NO_OPERATION_V                                                                                31:0
-
-#define NVC3C0_SET_NOTIFY_A                                                                                0x0104
-#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVC3C0_SET_NOTIFY_B                                                                                0x0108
-#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVC3C0_NOTIFY                                                                                      0x010c
-#define NVC3C0_NOTIFY_TYPE                                                                                   31:0
-#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVC3C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVC3C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVC3C0_SEND_GO_IDLE                                                                                0x013c
-#define NVC3C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVC3C0_PM_TRIGGER                                                                                  0x0140
-#define NVC3C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVC3C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVC3C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN                                                                    0x0148
-#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V                                                                    31:0
-
-#define NVC3C0_FE_ATOMIC_SEQUENCE_END                                                                      0x014c
-#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V                                                                      31:0
-
-#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVC3C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVC3C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVC3C0_LINE_COUNT                                                                                  0x0184
-#define NVC3C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVC3C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVC3C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
-
-#define NVC3C0_OFFSET_OUT                                                                                  0x018c
-#define NVC3C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVC3C0_PITCH_OUT                                                                                   0x0190
-#define NVC3C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVC3C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVC3C0_SET_DST_WIDTH                                                                               0x0198
-#define NVC3C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVC3C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVC3C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVC3C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVC3C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVC3C0_SET_DST_LAYER                                                                               0x01a4
-#define NVC3C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVC3C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
-
-#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
-
-#define NVC3C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVC3C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVC3C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVC3C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC3C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC3C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVC3C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVC3C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVC3C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVC3C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVC3C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVC3C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVC3C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVC3C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
-#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
-
-#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
-#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
-
-#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
-#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
-
-#define NVC3C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVC3C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVC3C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVC3C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
-#define NVC3C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
-#define NVC3C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
-#define NVC3C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
-#define NVC3C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
-#define NVC3C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
-#define NVC3C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
-#define NVC3C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
-#define NVC3C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
-
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVC3C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVC3C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVC3C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVC3C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
-#define NVC3C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
-#define NVC3C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
-#define NVC3C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
-#define NVC3C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
-#define NVC3C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
-#define NVC3C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
-#define NVC3C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
-
-#define NVC3C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
-#define NVC3C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
-
-#define NVC3C0_SET_SCG_CONTROL                                                                             0x0270
-#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
-#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT                                                        20:12
-#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE                                        24:24
-#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE                             0x00000000
-#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE                              0x00000001
-
-#define NVC3C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVC3C0_SET_QMD_VERSION                                                                             0x0288
-#define NVC3C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVC3C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVC3C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVC3C0_INVALIDATE_SKED_CACHES                                                                      0x0298
-#define NVC3C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
-
-#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
-#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
-
-#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
-#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
-
-#define NVC3C0_SCG_HYSTERESIS_CONTROL                                                                      0x02a8
-#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE                                                        0:0
-#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE                                           0x00000000
-#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE                                            0x00000001
-#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE                                                   1:1
-#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE                                      0x00000000
-#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE                                       0x00000001
-
-#define NVC3C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVC3C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVC3C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVC3C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVC3C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVC3C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVC3C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVC3C0_SET_SKED_CACHE_CONTROL                                                                      0x02cc
-#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID                                                             0:0
-#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE                                                0x00000000
-#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE                                                 0x00000001
-
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVC3C0_SET_SPA_VERSION                                                                             0x0310
-#define NVC3C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVC3C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVC3C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
-#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
-
-#define NVC3C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
-#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
-
-#define NVC3C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
-#define NVC3C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
-
-#define NVC3C0_SET_FALCON00                                                                                0x0500
-#define NVC3C0_SET_FALCON00_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON01                                                                                0x0504
-#define NVC3C0_SET_FALCON01_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON02                                                                                0x0508
-#define NVC3C0_SET_FALCON02_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON03                                                                                0x050c
-#define NVC3C0_SET_FALCON03_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON04                                                                                0x0510
-#define NVC3C0_SET_FALCON04_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON05                                                                                0x0514
-#define NVC3C0_SET_FALCON05_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON06                                                                                0x0518
-#define NVC3C0_SET_FALCON06_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON07                                                                                0x051c
-#define NVC3C0_SET_FALCON07_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON08                                                                                0x0520
-#define NVC3C0_SET_FALCON08_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON09                                                                                0x0524
-#define NVC3C0_SET_FALCON09_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON10                                                                                0x0528
-#define NVC3C0_SET_FALCON10_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON11                                                                                0x052c
-#define NVC3C0_SET_FALCON11_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON12                                                                                0x0530
-#define NVC3C0_SET_FALCON12_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON13                                                                                0x0534
-#define NVC3C0_SET_FALCON13_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON14                                                                                0x0538
-#define NVC3C0_SET_FALCON14_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON15                                                                                0x053c
-#define NVC3C0_SET_FALCON15_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON16                                                                                0x0540
-#define NVC3C0_SET_FALCON16_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON17                                                                                0x0544
-#define NVC3C0_SET_FALCON17_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON18                                                                                0x0548
-#define NVC3C0_SET_FALCON18_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON19                                                                                0x054c
-#define NVC3C0_SET_FALCON19_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON20                                                                                0x0550
-#define NVC3C0_SET_FALCON20_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON21                                                                                0x0554
-#define NVC3C0_SET_FALCON21_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON22                                                                                0x0558
-#define NVC3C0_SET_FALCON22_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON23                                                                                0x055c
-#define NVC3C0_SET_FALCON23_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON24                                                                                0x0560
-#define NVC3C0_SET_FALCON24_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON25                                                                                0x0564
-#define NVC3C0_SET_FALCON25_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON26                                                                                0x0568
-#define NVC3C0_SET_FALCON26_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON27                                                                                0x056c
-#define NVC3C0_SET_FALCON27_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON28                                                                                0x0570
-#define NVC3C0_SET_FALCON28_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON29                                                                                0x0574
-#define NVC3C0_SET_FALCON29_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON30                                                                                0x0578
-#define NVC3C0_SET_FALCON30_V                                                                                31:0
-
-#define NVC3C0_SET_FALCON31                                                                                0x057c
-#define NVC3C0_SET_FALCON31_V                                                                                31:0
-
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
-
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
-
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
-#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
-
-#define NVC3C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVC3C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
-
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
-
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
-#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
-#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
-#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
-
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVC3C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVC3C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC3C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC3C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVC3C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVC3C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
-
-#define NVC3C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVC3C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVC3C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
-
-#define NVC3C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVC3C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVC3C0_PIPE_NOP                                                                                    0x1a2c
-#define NVC3C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVC3C0_SET_SPARE00                                                                                 0x1a30
-#define NVC3C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVC3C0_SET_SPARE01                                                                                 0x1a34
-#define NVC3C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVC3C0_SET_SPARE02                                                                                 0x1a38
-#define NVC3C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVC3C0_SET_SPARE03                                                                                 0x1a3c
-#define NVC3C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVC3C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVC3C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVC3C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVC3C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-
-#define NVC3C0_SET_TRAP_HANDLER_A                                                                          0x25f8
-#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER                                                              16:0
-
-#define NVC3C0_SET_TRAP_HANDLER_B                                                                          0x25fc
-#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER                                                              31:0
-
-#define NVC3C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i)                                    (0x32f4+(i)*4)
-#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V                                               31:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i)                              (0x3314+(i)*4)
-#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V                                         31:0
-
-#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                  0x3334
-#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                   0:0
-
-#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                 0x3338
-#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                  0:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
-#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
-
-#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
-#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
-
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
-#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
-
-#define NVC3C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVC3C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_volta_compute_a_h_ */
diff --git a/Compute-Class-Methods/clc5c0.h b/Compute-Class-Methods/clc5c0.h
deleted file mode 100644
index 3d0fd54..0000000
--- a/Compute-Class-Methods/clc5c0.h
+++ /dev/null
@@ -1,942 +0,0 @@
-/*
- * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_turing_compute_a_h_
-#define _cl_turing_compute_a_h_
-
-/* AUTO GENERATED FILE -- DO NOT EDIT */
-/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */
-
-#include "nvtypes.h"
-
-#define TURING_COMPUTE_A    0xC5C0
-
-typedef volatile struct turing_compute_a_struct {
-    NvU32 SetObject;
-    NvU32 Reserved_0x04[0x3F];
-    NvU32 NoOperation;
-    NvU32 SetNotifyA;
-    NvU32 SetNotifyB;
-    NvU32 Notify;
-    NvU32 WaitForIdle;
-    NvU32 Reserved_0x114[0x7];
-    NvU32 SetGlobalRenderEnableA;
-    NvU32 SetGlobalRenderEnableB;
-    NvU32 SetGlobalRenderEnableC;
-    NvU32 SendGoIdle;
-    NvU32 PmTrigger;
-    NvU32 PmTriggerWfi;
-    NvU32 FeAtomicSequenceBegin;
-    NvU32 FeAtomicSequenceEnd;
-    NvU32 SetInstrumentationMethodHeader;
-    NvU32 SetInstrumentationMethodData;
-    NvU32 Reserved_0x158[0xA];
-    NvU32 LineLengthIn;
-    NvU32 LineCount;
-    NvU32 OffsetOutUpper;
-    NvU32 OffsetOut;
-    NvU32 PitchOut;
-    NvU32 SetDstBlockSize;
-    NvU32 SetDstWidth;
-    NvU32 SetDstHeight;
-    NvU32 SetDstDepth;
-    NvU32 SetDstLayer;
-    NvU32 SetDstOriginBytesX;
-    NvU32 SetDstOriginSamplesY;
-    NvU32 LaunchDma;
-    NvU32 LoadInlineData;
-    NvU32 Reserved_0x1B8[0x9];
-    NvU32 SetI2mSemaphoreA;
-    NvU32 SetI2mSemaphoreB;
-    NvU32 SetI2mSemaphoreC;
-    NvU32 SetSmScgControl;
-    NvU32 Reserved_0x1EC[0x1];
-    NvU32 SetI2mSpareNoop00;
-    NvU32 SetI2mSpareNoop01;
-    NvU32 SetI2mSpareNoop02;
-    NvU32 SetI2mSpareNoop03;
-    NvU32 SetValidSpanOverflowAreaA;
-    NvU32 SetValidSpanOverflowAreaB;
-    NvU32 SetValidSpanOverflowAreaC;
-    NvU32 Reserved_0x20C[0x1];
-    NvU32 PerfmonTransfer;
-    NvU32 SetQmdVirtualizationBaseA;
-    NvU32 SetQmdVirtualizationBaseB;
-    NvU32 InvalidateShaderCaches;
-    NvU32 SetReservedSwMethod00;
-    NvU32 SetReservedSwMethod01;
-    NvU32 SetReservedSwMethod02;
-    NvU32 SetReservedSwMethod03;
-    NvU32 SetReservedSwMethod04;
-    NvU32 SetReservedSwMethod05;
-    NvU32 SetReservedSwMethod06;
-    NvU32 SetReservedSwMethod07;
-    NvU32 Reserved_0x240[0x1];
-    NvU32 InvalidateTextureHeaderCacheNoWfi;
-    NvU32 SetCwdRefCounter;
-    NvU32 SetReservedSwMethod08;
-    NvU32 SetReservedSwMethod09;
-    NvU32 SetReservedSwMethod10;
-    NvU32 SetReservedSwMethod11;
-    NvU32 SetReservedSwMethod12;
-    NvU32 SetReservedSwMethod13;
-    NvU32 SetReservedSwMethod14;
-    NvU32 SetReservedSwMethod15;
-    NvU32 Reserved_0x26C[0x1];
-    NvU32 SetScgControl;
-    NvU32 Reserved_0x274[0x3];
-    NvU32 SetComputeClassVersion;
-    NvU32 CheckComputeClassVersion;
-    NvU32 SetQmdVersion;
-    NvU32 Reserved_0x28C[0x1];
-    NvU32 CheckQmdVersion;
-    NvU32 Reserved_0x294[0x1];
-    NvU32 InvalidateSkedCaches;
-    NvU32 SetQmdVirtualizationControl;
-    NvU32 SetShaderSharedMemoryWindowA;
-    NvU32 SetShaderSharedMemoryWindowB;
-    NvU32 ScgHysteresisControl;
-    NvU32 Reserved_0x2AC[0x1];
-    NvU32 SetCwdSlotCount;
-    NvU32 SendPcasA;
-    NvU32 SendPcasB;
-    NvU32 SendSignalingPcasB;
-    NvU32 Reserved_0x2C0[0x3];
-    NvU32 SetSkedCacheControl;
-    NvU32 Reserved_0x2D0[0x5];
-    NvU32 SetShaderLocalMemoryNonThrottledA;
-    NvU32 SetShaderLocalMemoryNonThrottledB;
-    NvU32 SetShaderLocalMemoryNonThrottledC;
-    NvU32 Reserved_0x2F0[0x8];
-    NvU32 SetSpaVersion;
-    NvU32 Reserved_0x314[0x1];
-    NvU32 SetInlineQmdAddressA;
-    NvU32 SetInlineQmdAddressB;
-    NvU32 LoadInlineQmdData[0x40];
-    NvU32 Reserved_0x420[0x38];
-    NvU32 SetFalcon00;
-    NvU32 SetFalcon01;
-    NvU32 SetFalcon02;
-    NvU32 SetFalcon03;
-    NvU32 SetFalcon04;
-    NvU32 SetFalcon05;
-    NvU32 SetFalcon06;
-    NvU32 SetFalcon07;
-    NvU32 SetFalcon08;
-    NvU32 SetFalcon09;
-    NvU32 SetFalcon10;
-    NvU32 SetFalcon11;
-    NvU32 SetFalcon12;
-    NvU32 SetFalcon13;
-    NvU32 SetFalcon14;
-    NvU32 SetFalcon15;
-    NvU32 SetFalcon16;
-    NvU32 SetFalcon17;
-    NvU32 SetFalcon18;
-    NvU32 SetFalcon19;
-    NvU32 SetFalcon20;
-    NvU32 SetFalcon21;
-    NvU32 SetFalcon22;
-    NvU32 SetFalcon23;
-    NvU32 SetFalcon24;
-    NvU32 SetFalcon25;
-    NvU32 SetFalcon26;
-    NvU32 SetFalcon27;
-    NvU32 SetFalcon28;
-    NvU32 SetFalcon29;
-    NvU32 SetFalcon30;
-    NvU32 SetFalcon31;
-    NvU32 Reserved_0x580[0x84];
-    NvU32 SetShaderLocalMemoryA;
-    NvU32 SetShaderLocalMemoryB;
-    NvU32 Reserved_0x798[0x6];
-    NvU32 SetShaderLocalMemoryWindowA;
-    NvU32 SetShaderLocalMemoryWindowB;
-    NvU32 Reserved_0x7B8[0x177];
-    NvU32 SetShaderCacheControl;
-    NvU32 Reserved_0xD98[0x2];
-    NvU32 SetScgComputeSchedulingParameters[0x10];
-    NvU32 Reserved_0xDE0[0x1];
-    NvU32 SetSmTimeoutInterval;
-    NvU32 Reserved_0xDE8[0x128];
-    NvU32 InvalidateTextureDataCacheNoWfi;
-    NvU32 Reserved_0x128C[0x7];
-    NvU32 ActivatePerfSettingsForComputeContext;
-    NvU32 Reserved_0x12AC[0x21];
-    NvU32 InvalidateSamplerCache;
-    NvU32 InvalidateTextureHeaderCache;
-    NvU32 InvalidateTextureDataCache;
-    NvU32 Reserved_0x133C[0x3A];
-    NvU32 InvalidateSamplerCacheNoWfi;
-    NvU32 Reserved_0x1428[0x40];
-    NvU32 SetShaderExceptions;
-    NvU32 Reserved_0x152C[0x9];
-    NvU32 SetRenderEnableA;
-    NvU32 SetRenderEnableB;
-    NvU32 SetRenderEnableC;
-    NvU32 SetTexSamplerPoolA;
-    NvU32 SetTexSamplerPoolB;
-    NvU32 SetTexSamplerPoolC;
-    NvU32 Reserved_0x1568[0x3];
-    NvU32 SetTexHeaderPoolA;
-    NvU32 SetTexHeaderPoolB;
-    NvU32 SetTexHeaderPoolC;
-    NvU32 Reserved_0x1580[0x46];
-    NvU32 InvalidateShaderCachesNoWfi;
-    NvU32 Reserved_0x169C[0xAA];
-    NvU32 SetRenderEnableOverride;
-    NvU32 Reserved_0x1948[0x37];
-    NvU32 Reserved_0x1A28[0x1];
-    NvU32 PipeNop;
-    NvU32 SetSpare00;
-    NvU32 SetSpare01;
-    NvU32 SetSpare02;
-    NvU32 SetSpare03;
-    NvU32 Reserved_0x1A40[0x30];
-    NvU32 SetReportSemaphoreA;
-    NvU32 SetReportSemaphoreB;
-    NvU32 SetReportSemaphoreC;
-    NvU32 SetReportSemaphoreD;
-    NvU32 Reserved_0x1B10[0x2BA];
-    NvU32 SetTrapHandlerA;
-    NvU32 SetTrapHandlerB;
-    NvU32 Reserved_0x2600[0x2];
-    NvU32 SetBindlessTexture;
-    NvU32 Reserved_0x260C[0x33A];
-    NvU32 SetShaderPerformanceSnapshotCounterValue[0x8];
-    NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8];
-    NvU32 EnableShaderPerformanceSnapshotCounter;
-    NvU32 DisableShaderPerformanceSnapshotCounter;
-    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
-    NvU32 SetShaderPerformanceCounterValue[0x8];
-    NvU32 SetShaderPerformanceCounterEvent[0x8];
-    NvU32 SetShaderPerformanceCounterControlA[0x8];
-    NvU32 SetShaderPerformanceCounterControlB[0x8];
-    NvU32 SetShaderPerformanceCounterTrapControl;
-    NvU32 StartShaderPerformanceCounter;
-    NvU32 StopShaderPerformanceCounter;
-    NvU32 SetShaderPerformanceCounterSctlFilter;
-    NvU32 SetShaderPerformanceCounterCoreMioFilter;
-    NvU32 Reserved_0x33F0[0x4];
-    NvU32 SetMmeShadowScratch[0x8];
-} turing_compute_a_t;
-
-
-#define NVC5C0_SET_OBJECT                                                                                  0x0000
-#define NVC5C0_SET_OBJECT_CLASS_ID                                                                           15:0
-#define NVC5C0_SET_OBJECT_ENGINE_ID                                                                         20:16
-
-#define NVC5C0_NO_OPERATION                                                                                0x0100
-#define NVC5C0_NO_OPERATION_V                                                                                31:0
-
-#define NVC5C0_SET_NOTIFY_A                                                                                0x0104
-#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
-
-#define NVC5C0_SET_NOTIFY_B                                                                                0x0108
-#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
-
-#define NVC5C0_NOTIFY                                                                                      0x010c
-#define NVC5C0_NOTIFY_TYPE                                                                                   31:0
-#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
-#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
-
-#define NVC5C0_WAIT_FOR_IDLE                                                                               0x0110
-#define NVC5C0_WAIT_FOR_IDLE_V                                                                               31:0
-
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
-
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
-
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
-#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
-
-#define NVC5C0_SEND_GO_IDLE                                                                                0x013c
-#define NVC5C0_SEND_GO_IDLE_V                                                                                31:0
-
-#define NVC5C0_PM_TRIGGER                                                                                  0x0140
-#define NVC5C0_PM_TRIGGER_V                                                                                  31:0
-
-#define NVC5C0_PM_TRIGGER_WFI                                                                              0x0144
-#define NVC5C0_PM_TRIGGER_WFI_V                                                                              31:0
-
-#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN                                                                    0x0148
-#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V                                                                    31:0
-
-#define NVC5C0_FE_ATOMIC_SEQUENCE_END                                                                      0x014c
-#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V                                                                      31:0
-
-#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
-#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
-
-#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
-#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
-
-#define NVC5C0_LINE_LENGTH_IN                                                                              0x0180
-#define NVC5C0_LINE_LENGTH_IN_VALUE                                                                          31:0
-
-#define NVC5C0_LINE_COUNT                                                                                  0x0184
-#define NVC5C0_LINE_COUNT_VALUE                                                                              31:0
-
-#define NVC5C0_OFFSET_OUT_UPPER                                                                            0x0188
-#define NVC5C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
-
-#define NVC5C0_OFFSET_OUT                                                                                  0x018c
-#define NVC5C0_OFFSET_OUT_VALUE                                                                              31:0
-
-#define NVC5C0_PITCH_OUT                                                                                   0x0190
-#define NVC5C0_PITCH_OUT_VALUE                                                                               31:0
-
-#define NVC5C0_SET_DST_BLOCK_SIZE                                                                          0x0194
-#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
-#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
-#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
-#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
-#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
-#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
-#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
-#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
-#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
-#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
-#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
-#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
-#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
-#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
-#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
-#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
-
-#define NVC5C0_SET_DST_WIDTH                                                                               0x0198
-#define NVC5C0_SET_DST_WIDTH_V                                                                               31:0
-
-#define NVC5C0_SET_DST_HEIGHT                                                                              0x019c
-#define NVC5C0_SET_DST_HEIGHT_V                                                                              31:0
-
-#define NVC5C0_SET_DST_DEPTH                                                                               0x01a0
-#define NVC5C0_SET_DST_DEPTH_V                                                                               31:0
-
-#define NVC5C0_SET_DST_LAYER                                                                               0x01a4
-#define NVC5C0_SET_DST_LAYER_V                                                                               31:0
-
-#define NVC5C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
-#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
-
-#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
-#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
-
-#define NVC5C0_LAUNCH_DMA                                                                                  0x01b0
-#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
-#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
-#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
-#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
-#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
-#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
-#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
-#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
-#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
-#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
-#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
-#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
-#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
-#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
-#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
-#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
-#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
-#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
-#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
-#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
-#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
-#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
-#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
-
-#define NVC5C0_LOAD_INLINE_DATA                                                                            0x01b4
-#define NVC5C0_LOAD_INLINE_DATA_V                                                                            31:0
-
-#define NVC5C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
-#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC5C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
-#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC5C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
-#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
-
-#define NVC5C0_SET_SM_SCG_CONTROL                                                                          0x01e8
-#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS                                                         0:0
-#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE                                            0x00000000
-#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE                                             0x00000001
-
-#define NVC5C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
-#define NVC5C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
-
-#define NVC5C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
-#define NVC5C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
-
-#define NVC5C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
-#define NVC5C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
-
-#define NVC5C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
-#define NVC5C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
-
-#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
-#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
-
-#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
-#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
-
-#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
-#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
-
-#define NVC5C0_PERFMON_TRANSFER                                                                            0x0210
-#define NVC5C0_PERFMON_TRANSFER_V                                                                            31:0
-
-#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A                                                               0x0214
-#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER                                                    7:0
-
-#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B                                                               0x0218
-#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER                                                   31:0
-
-#define NVC5C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
-#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
-#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
-#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
-#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
-#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
-#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
-#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
-#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
-#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
-#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
-
-#define NVC5C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
-#define NVC5C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
-#define NVC5C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
-#define NVC5C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
-#define NVC5C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
-#define NVC5C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
-#define NVC5C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
-#define NVC5C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
-#define NVC5C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
-
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
-
-#define NVC5C0_SET_CWD_REF_COUNTER                                                                         0x0248
-#define NVC5C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
-#define NVC5C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
-
-#define NVC5C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
-#define NVC5C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
-#define NVC5C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
-#define NVC5C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
-#define NVC5C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
-#define NVC5C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
-#define NVC5C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
-#define NVC5C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
-
-#define NVC5C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
-#define NVC5C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
-
-#define NVC5C0_SET_SCG_CONTROL                                                                             0x0270
-#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
-#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT                                                        20:12
-#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE                                        24:24
-#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE                             0x00000000
-#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE                              0x00000001
-
-#define NVC5C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
-#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
-#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
-
-#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
-#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
-#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
-
-#define NVC5C0_SET_QMD_VERSION                                                                             0x0288
-#define NVC5C0_SET_QMD_VERSION_CURRENT                                                                       15:0
-#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
-
-#define NVC5C0_CHECK_QMD_VERSION                                                                           0x0290
-#define NVC5C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
-#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
-
-#define NVC5C0_INVALIDATE_SKED_CACHES                                                                      0x0298
-#define NVC5C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
-
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL                                                              0x029c
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK                                            7:0
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE                                                 8:8
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE                                    0x00000000
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE                                     0x00000001
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE                                    12:12
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE                         0x00000000
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE                          0x00000001
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE                                              16:16
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE                                   0x00000000
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE                                    0x00000001
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE                                   20:20
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE                        0x00000000
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE                         0x00000001
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE                                              24:24
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE                                   0x00000000
-#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE                                    0x00000001
-
-#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
-#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
-
-#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
-#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
-
-#define NVC5C0_SCG_HYSTERESIS_CONTROL                                                                      0x02a8
-#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE                                                        0:0
-#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE                                           0x00000000
-#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE                                            0x00000001
-#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE                                                   1:1
-#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE                                      0x00000000
-#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE                                       0x00000001
-
-#define NVC5C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
-#define NVC5C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
-
-#define NVC5C0_SEND_PCAS_A                                                                                 0x02b4
-#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
-
-#define NVC5C0_SEND_PCAS_B                                                                                 0x02b8
-#define NVC5C0_SEND_PCAS_B_FROM                                                                              23:0
-#define NVC5C0_SEND_PCAS_B_DELTA                                                                            31:24
-
-#define NVC5C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
-#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
-#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
-#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
-#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
-#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
-#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
-
-#define NVC5C0_SET_SKED_CACHE_CONTROL                                                                      0x02cc
-#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID                                                             0:0
-#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE                                                0x00000000
-#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE                                                 0x00000001
-
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
-
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
-
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
-
-#define NVC5C0_SET_SPA_VERSION                                                                             0x0310
-#define NVC5C0_SET_SPA_VERSION_MINOR                                                                          7:0
-#define NVC5C0_SET_SPA_VERSION_MAJOR                                                                         15:8
-
-#define NVC5C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
-#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
-
-#define NVC5C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
-#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
-
-#define NVC5C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
-#define NVC5C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
-
-#define NVC5C0_SET_FALCON00                                                                                0x0500
-#define NVC5C0_SET_FALCON00_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON01                                                                                0x0504
-#define NVC5C0_SET_FALCON01_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON02                                                                                0x0508
-#define NVC5C0_SET_FALCON02_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON03                                                                                0x050c
-#define NVC5C0_SET_FALCON03_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON04                                                                                0x0510
-#define NVC5C0_SET_FALCON04_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON05                                                                                0x0514
-#define NVC5C0_SET_FALCON05_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON06                                                                                0x0518
-#define NVC5C0_SET_FALCON06_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON07                                                                                0x051c
-#define NVC5C0_SET_FALCON07_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON08                                                                                0x0520
-#define NVC5C0_SET_FALCON08_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON09                                                                                0x0524
-#define NVC5C0_SET_FALCON09_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON10                                                                                0x0528
-#define NVC5C0_SET_FALCON10_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON11                                                                                0x052c
-#define NVC5C0_SET_FALCON11_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON12                                                                                0x0530
-#define NVC5C0_SET_FALCON12_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON13                                                                                0x0534
-#define NVC5C0_SET_FALCON13_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON14                                                                                0x0538
-#define NVC5C0_SET_FALCON14_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON15                                                                                0x053c
-#define NVC5C0_SET_FALCON15_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON16                                                                                0x0540
-#define NVC5C0_SET_FALCON16_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON17                                                                                0x0544
-#define NVC5C0_SET_FALCON17_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON18                                                                                0x0548
-#define NVC5C0_SET_FALCON18_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON19                                                                                0x054c
-#define NVC5C0_SET_FALCON19_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON20                                                                                0x0550
-#define NVC5C0_SET_FALCON20_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON21                                                                                0x0554
-#define NVC5C0_SET_FALCON21_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON22                                                                                0x0558
-#define NVC5C0_SET_FALCON22_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON23                                                                                0x055c
-#define NVC5C0_SET_FALCON23_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON24                                                                                0x0560
-#define NVC5C0_SET_FALCON24_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON25                                                                                0x0564
-#define NVC5C0_SET_FALCON25_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON26                                                                                0x0568
-#define NVC5C0_SET_FALCON26_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON27                                                                                0x056c
-#define NVC5C0_SET_FALCON27_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON28                                                                                0x0570
-#define NVC5C0_SET_FALCON28_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON29                                                                                0x0574
-#define NVC5C0_SET_FALCON29_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON30                                                                                0x0578
-#define NVC5C0_SET_FALCON30_V                                                                                31:0
-
-#define NVC5C0_SET_FALCON31                                                                                0x057c
-#define NVC5C0_SET_FALCON31_V                                                                                31:0
-
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
-
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
-
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
-
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
-#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
-
-#define NVC5C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
-#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
-#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
-#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
-
-#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i)                                            (0x0da0+(i)*4)
-#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V                                                       31:0
-
-#define NVC5C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
-#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
-
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
-
-#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
-#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
-#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
-#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
-
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
-
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
-#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
-
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
-#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
-
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
-#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
-
-#define NVC5C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
-#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
-#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
-#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
-
-#define NVC5C0_SET_RENDER_ENABLE_A                                                                         0x1550
-#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
-
-#define NVC5C0_SET_RENDER_ENABLE_B                                                                         0x1554
-#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
-
-#define NVC5C0_SET_RENDER_ENABLE_C                                                                         0x1558
-#define NVC5C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
-#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
-#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
-#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
-#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
-#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
-
-#define NVC5C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
-#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
-
-#define NVC5C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
-#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
-
-#define NVC5C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
-#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
-
-#define NVC5C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
-#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
-
-#define NVC5C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
-#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
-
-#define NVC5C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
-#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
-
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
-#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
-
-#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
-#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
-#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
-#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
-#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
-
-#define NVC5C0_PIPE_NOP                                                                                    0x1a2c
-#define NVC5C0_PIPE_NOP_V                                                                                    31:0
-
-#define NVC5C0_SET_SPARE00                                                                                 0x1a30
-#define NVC5C0_SET_SPARE00_V                                                                                 31:0
-
-#define NVC5C0_SET_SPARE01                                                                                 0x1a34
-#define NVC5C0_SET_SPARE01_V                                                                                 31:0
-
-#define NVC5C0_SET_SPARE02                                                                                 0x1a38
-#define NVC5C0_SET_SPARE02_V                                                                                 31:0
-
-#define NVC5C0_SET_SPARE03                                                                                 0x1a3c
-#define NVC5C0_SET_SPARE03_V                                                                                 31:0
-
-#define NVC5C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
-#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
-
-#define NVC5C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
-#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
-
-#define NVC5C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
-#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
-
-#define NVC5C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP                                                      19:19
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE                                           0x00000000
-#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE                                            0x00000001
-
-#define NVC5C0_SET_TRAP_HANDLER_A                                                                          0x25f8
-#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER                                                              16:0
-
-#define NVC5C0_SET_TRAP_HANDLER_B                                                                          0x25fc
-#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER                                                              31:0
-
-#define NVC5C0_SET_BINDLESS_TEXTURE                                                                        0x2608
-#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i)                                    (0x32f4+(i)*4)
-#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V                                               31:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i)                              (0x3314+(i)*4)
-#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V                                         31:0
-
-#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                  0x3334
-#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                   0:0
-
-#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                 0x3338
-#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                  0:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
-
-#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
-#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
-
-#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
-#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
-
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
-#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
-
-#define NVC5C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
-#define NVC5C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
-
-#endif /* _cl_turing_compute_a_h_ */
diff --git a/Compute-Class-Methods/index.html b/Compute-Class-Methods/index.html
deleted file mode 100644
index 4281791..0000000
--- a/Compute-Class-Methods/index.html
+++ /dev/null
@@ -1,18 +0,0 @@
-<html>
-    <head><title>Compute-Class-Methods</title></head>
-    <body>
-        <h1>Compute-Class-Methods</h1>
-        <a href="cl50c0.h">cl50c0.h</a><br/>
-        <a href="cl85c0.h">cl85c0.h</a><br/>
-        <a href="cl90c0.h">cl90c0.h</a><br/>
-        <a href="cl91c0.h">cl91c0.h</a><br/>
-        <a href="cla0c0.h">cla0c0.h</a><br/>
-        <a href="cla1c0.h">cla1c0.h</a><br/>
-        <a href="clb0c0.h">clb0c0.h</a><br/>
-        <a href="clb1c0.h">clb1c0.h</a><br/>
-        <a href="clc0c0.h">clc0c0.h</a><br/>
-        <a href="clc1c0.h">clc1c0.h</a><br/>
-        <a href="clc3c0.h">clc3c0.h</a><br/>
-        <a href="clc5c0.h">clc5c0.h</a><br/>
-    </body>
-</html>
diff --git a/Display-Class-Methods/README.txt b/Display-Class-Methods/README.txt
deleted file mode 100644
index ea97c6e..0000000
--- a/Display-Class-Methods/README.txt
+++ /dev/null
@@ -1,190 +0,0 @@
-EVO CLASSES
-
-The NVIDIA "EVO" Display Engine was introduced in NV50, and has been
-incrementally updated in GPUs since then.
-
-EVO consists of several channels:
-
-    "core": This channel is used to perform modesets, as well as things
-            such as manage the LUT, and cursor properties (other than
-            position).  It has GPU scope.
-    "base": This channel is intended to be used for OpenGL SwapBuffers
-            flipping.  There is one base channel per head.
-    "overlay": This channel is intended to be used for flipping the
-            overlay.  There is one overlay channel per head.
-    "overlay immediate": This channel is intended to be used to position
-            the overlay within the raster of the head.  There is one
-            overlay immediate channel per head.  Originally, it was
-            conceived that a display driver would position the overlay
-            in response to a window move, using the "overlay immediate"
-            channel, and a video driver would flip buffers using the
-            overlay channel.
-    "cursor": This channel is used to position the cursor.  There is
-            one cursor channel per head.  The cursor format and buffer
-            is specified through the core channel.  It was originally
-            conceived that the management of cursor would be distributed
-            between the core and cursor channels in the same way that
-            overlay management is distributed between overlay and overlay
-            immediate channels.  The cursor channel allows low-latency
-            cursor position updates, asynchronously to the core channel.
-
-The "NVDisplay" Engine is new in Volta, and is a major improvement upon EVO.
-The software interface consists of a set of channels as in EVO, but how those
-channels can be used is more flexible.
-
-    "core": This channel is similar to EVO's core channel, except it does not
-            support programming a surface as a base layer.
-    "window": This channel replaces EVO's base and overlay channels.  It is
-            designed support a superset of the capabilities of the earlier
-            channels, but in addition supports scaling, alpha blending, and
-            blend order, among other improvements.  Windows are not inherently
-            bound to a head and must be bound explicitly with core channel
-            methods.
-    "window immediate": Like EVO's overlay immediate, this can be used to
-            position the corresponding window channel on the raster.  Unlike
-            EVO's overlay immediate, this is a DMA channel to support
-            enqueuing more than one update at a time.
-    "cursor": This is similar to EVO's cursor channel.  There is one cursor
-            per head.
-
-There is a per-channel header file that defines the method interface to
-each channel.
-
-There are both a "class name" and a software class number that are
-used to describe the combination of channel versions used together.
-
-The table below describes which class name is used with which GPU,
-and which channel header files are used with that class.
-
-__________________________________________________________________________
-
-Class Name:                 DISP010X
-Software Class Number:      5070
-Cursor Channel:             cl507a.h
-Overlay Immediate Channel:  cl507b.h
-Base Channel:               cl507c.h
-Core Channel:               cl507d.h
-Overlay Channel:            cl507e.h
-GPUs:                       nv50
-__________________________________________________________________________
-
-Class Name:                 DISP011X
-Software Class Number:      8270
-Cursor Channel:             cl827a.h
-Overlay Immediate Channel:  cl827b.h
-Base Channel:               cl827c.h
-Core Channel:               cl827d.h
-Overlay Channel:            cl827e.h
-GPUs:                       g84, g86, g92
-__________________________________________________________________________
-
-Class Name:                 DISP012X
-Software Class Number:      8370
-Cursor Channel:             cl827a.h
-Overlay Immediate Channel:  cl827b.h
-Base Channel:               cl837c.h
-Core Channel:               cl837d.h
-Overlay Channel:            cl837e.h
-GPUs:                       gt200
-__________________________________________________________________________
-
-Class Name:                 DISP014X
-Software Class Number:      8870
-Cursor Channel:             cl827a.h
-Overlay Immediate Channel:  cl827b.h
-Base Channel:               cl837c.h
-Core Channel:               cl887d.h
-Overlay Channel:            cl837e.h
-GPUs:                       g94, g96, g98, mcp7x
-__________________________________________________________________________
-
-Class Name:                 DISP015X
-Software Class Number:      8570
-Cursor Channel:             cl857a.h
-Overlay Immediate Channel:  cl857b.h
-Base Channel:               cl857c.h
-Core Channel:               cl857d.h
-Overlay Channel:            cl857e.h
-GPUs:                       gt215, gt216, gt218, mcp89
-                            gf100, gf104, gf106, gf114, gf116, gf108
-__________________________________________________________________________
-
-Class Name:                 DISP020X
-Software Class Number:      9070
-Cursor Channel:             cl907a.h
-Overlay Immediate Channel:  cl907b.h
-Base Channel:               cl907c.h
-Core Channel:               cl907d.h
-Overlay Channel:            cl907e.h
-GPUs:                       gf119
-__________________________________________________________________________
-
-Class Name:                 DISP021X
-Software Class Number:      9170
-Cursor Channel:             cl917a.h
-Overlay Immediate Channel:  cl917b.h
-Base Channel:               cl917c.h
-Core Channel:               cl917d.h
-Overlay Channel:            cl917e.h
-GPUs:                       gk104, gk106, gk107
-__________________________________________________________________________
-
-Class Name:                 DISP022X
-Software Class Number:      9270
-Cursor Channel:             cl917a.h
-Overlay Immediate Channel:  cl917b.h
-Base Channel:               cl927c.h
-Core Channel:               cl927d.h
-Overlay Channel:            cl917e.h
-GPUs:                       gk110, gk208
-__________________________________________________________________________
-
-Class Name:                 DISP024X
-Software Class Number:      9470
-Cursor Channel:             cl917a.h
-Overlay Immediate Channel:  cl917b.h
-Base Channel:               cl927c.h
-Core Channel:               cl947d.h
-Overlay Channel:            cl917e.h
-GPUs:                       gm107, gm108
-__________________________________________________________________________
-
-Class Name:                 DISP025X
-Software Class Number:      9570
-Cursor Channel:             cl917a.h
-Overlay Immediate Channel:  cl917b.h
-Base Channel:               cl927c.h
-Core Channel:               cl957d.h
-Overlay Channel:            cl917e.h
-GPUs:                       gm200, gm204, gm206
-__________________________________________________________________________
-
-Class Name:                 DISP027X
-Software Class Number:      9770
-Cursor Channel:             cl917a.h
-Overlay Immediate Channel:  cl917b.h
-Base Channel:               cl927c.h
-Core Channel:               cl977d.h
-Overlay Channel:            cl917e.h
-GPUs:                       gp100
-__________________________________________________________________________
-
-Class Name:                 DISP028X
-Software Class Number:      9870
-Cursor Channel:             cl917a.h
-Overlay Immediate Channel:  cl917b.h
-Base Channel:               cl927c.h
-Core Channel:               cl987d.h
-Overlay Channel:            cl917e.h
-GPUs:                       gp102, gp104, gp106, gp107, gp108
-__________________________________________________________________________
-
-Class Name:                 NVD_20
-Software Class Number:      C370
-Cursor Channel:             clc37a.h
-Window Immediate Channel:   clc37b.h
-Core Channel:               clc37d.h
-Window Channel:             clc37e.h
-GPUs:                       gv100
-__________________________________________________________________________
-
diff --git a/Display-Class-Methods/cl507a.h b/Display-Class-Methods/cl507a.h
deleted file mode 100644
index d2c38f4..0000000
--- a/Display-Class-Methods/cl507a.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl507a_h_
-#define _cl507a_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV507A_CURSOR_CHANNEL_PIO                                               (0x0000507A)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
-    NvV32 Reserved02[0x3DE];
-} Nv50DispCursorControlPio;
-
-#define NV507A_FREE                                                             (0x00000008)
-#define NV507A_FREE_COUNT                                                       5:0
-#define NV507A_UPDATE                                                           (0x00000080)
-#define NV507A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV507A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV507A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
-#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
-#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl507a_h
-
diff --git a/Display-Class-Methods/cl507b.h b/Display-Class-Methods/cl507b.h
deleted file mode 100644
index 460bc27..0000000
--- a/Display-Class-Methods/cl507b.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl507b_h_
-#define _cl507b_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV507B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000507B)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
-    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
-    NvV32 Reserved02[0x3DD];
-} Nv50DispOverlayImmControlPio;
-
-#define NV507B_FREE                                                             (0x00000008)
-#define NV507B_FREE_COUNT                                                       5:0
-#define NV507B_UPDATE                                                           (0x00000080)
-#define NV507B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV507B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV507B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV507B_SET_POINT_OUT                                                    (0x00000084)
-#define NV507B_SET_POINT_OUT_X                                                  15:0
-#define NV507B_SET_POINT_OUT_Y                                                  31:16
-#define NV507B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
-#define NV507B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl507b_h
-
diff --git a/Display-Class-Methods/cl507c.h b/Display-Class-Methods/cl507c.h
deleted file mode 100644
index db9aba5..0000000
--- a/Display-Class-Methods/cl507c.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl507c_h_
-#define _cl507c_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV507C_BASE_CHANNEL_DMA                                                 (0x0000507C)
-
-#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
-#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
-#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
-
-
-// dma opcode instructions
-#define NV507C_DMA                                     0x00000000 
-#define NV507C_DMA_OPCODE                                   31:29 
-#define NV507C_DMA_OPCODE_METHOD                       0x00000000 
-#define NV507C_DMA_OPCODE_JUMP                         0x00000001 
-#define NV507C_DMA_OPCODE_NONINC_METHOD                0x00000002 
-#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
-#define NV507C_DMA_OPCODE                                   31:29 
-#define NV507C_DMA_OPCODE_METHOD                       0x00000000 
-#define NV507C_DMA_OPCODE_NONINC_METHOD                0x00000002 
-#define NV507C_DMA_METHOD_COUNT                             27:18 
-#define NV507C_DMA_METHOD_OFFSET                             11:2 
-#define NV507C_DMA_DATA                                      31:0 
-#define NV507C_DMA_NOP                                 0x00000000 
-#define NV507C_DMA_OPCODE                                   31:29 
-#define NV507C_DMA_OPCODE_JUMP                         0x00000001 
-#define NV507C_DMA_JUMP_OFFSET                               11:2 
-#define NV507C_DMA_OPCODE                                   31:29 
-#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
-#define NV507C_DMA_SET_SUBDEVICE_MASK_VALUE                  11:0 
-
-// class methods
-#define NV507C_PUT                                                              (0x00000000)
-#define NV507C_PUT_PTR                                                          11:2
-#define NV507C_GET                                                              (0x00000004)
-#define NV507C_GET_PTR                                                          11:2
-#define NV507C_GET_SCANLINE                                                     (0x00000010)
-#define NV507C_GET_SCANLINE_LINE                                                15:0
-#define NV507C_UPDATE                                                           (0x00000080)
-#define NV507C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV507C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV507C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV507C_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
-#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
-#define NV507C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV507C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
-#define NV507C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
-#define NV507C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
-#define NV507C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV507C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
-#define NV507C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV507C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
-#define NV507C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV507C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV507C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV507C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV507C_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV507C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV507C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV507C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV507C_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
-#define NV507C_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
-#define NV507C_SET_BASE_LUT_LO                                                  (0x000000E0)
-#define NV507C_SET_BASE_LUT_LO_ENABLE                                           31:30
-#define NV507C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
-#define NV507C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
-#define NV507C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
-#define NV507C_SET_BASE_LUT_LO_MODE                                             29:29
-#define NV507C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
-#define NV507C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
-#define NV507C_SET_BASE_LUT_LO_ORIGIN                                           7:2
-#define NV507C_SET_BASE_LUT_HI                                                  (0x000000E4)
-#define NV507C_SET_BASE_LUT_HI_ORIGIN                                           31:0
-#define NV507C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
-#define NV507C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
-#define NV507C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
-#define NV507C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
-#define NV507C_SET_OUTPUT_LUT_LO_MODE                                           30:30
-#define NV507C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
-#define NV507C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
-#define NV507C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
-#define NV507C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
-#define NV507C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
-#define NV507C_SET_PROCESSING                                                   (0x00000110)
-#define NV507C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV507C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV507C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV507C_SET_CONVERSION                                                   (0x00000114)
-#define NV507C_SET_CONVERSION_GAIN                                              15:0
-#define NV507C_SET_CONVERSION_OFS                                               31:16
-#define NV507C_SET_SPARE                                                        (0x000007BC)
-#define NV507C_SET_SPARE_UNUSED                                                 31:0
-#define NV507C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV507C_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV507C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
-#define NV507C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV507C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
-#define NV507C_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV507C_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV507C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
-#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV507C_SURFACE_SET_STORAGE_PITCH                                        17:8
-#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV507C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
-#define NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
-#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
-#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
-#define NV507C_SURFACE_SET_PARAMS_GAMMA                                         2:2
-#define NV507C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
-#define NV507C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
-#define NV507C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
-#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
-#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
-#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
-#define NV507C_SURFACE_SET_PARAMS_KIND                                          22:16
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_PITCH                               (0x00000000)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2                        (0x00000070)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ               (0x00000072)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1                       (0x00000074)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ              (0x00000076)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4                             (0x00000078)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8                             (0x00000079)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ                    (0x0000007A)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ                    (0x0000007B)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4                             (0x0000007C)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8                             (0x0000007D)
-#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4                            (0x0000007E)
-#define NV507C_SURFACE_SET_PARAMS_KIND_FROM_PTE                                 (0x0000007F)
-#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE                                   24:24
-#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256                    (0x00000000)
-#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024                   (0x00000001)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl507c_h
-
diff --git a/Display-Class-Methods/cl507d.h b/Display-Class-Methods/cl507d.h
deleted file mode 100644
index 675b9e4..0000000
--- a/Display-Class-Methods/cl507d.h
+++ /dev/null
@@ -1,676 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl507d_h_
-#define _cl507d_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV507D_CORE_CHANNEL_DMA                                                 (0x0000507D)
-
-#define NV_DISP_CORE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_SIZEOF                                               0x00000054
-#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0                                         0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE                                    0:0
-#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0                                      15:1
-#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP                               29:16
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1                                       0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE                                  0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE                            0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE                             0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO                         1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_R0                                    3:3
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_R1                                    31:22
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_2                                       0x00000002
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_2_R2                                    31:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_3                                       0x00000003
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_3_R3                                    31:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_4                                       0x00000004
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_4_R4                                    31:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5                              0x00000005
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE                   0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE             0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE              0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE                    1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE              0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE               0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE                 3:3
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE           0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE            0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6                              0x00000006
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE                   0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE             0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE              0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE                    1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE              0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE               0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE                 3:3
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE           0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE            0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7                              0x00000007
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE                   0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE             0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE              0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE                    1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE              0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE               0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE                 3:3
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE           0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE            0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8                              0x00000008
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18                0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24                1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18                  2:2
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE            0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE             0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24                  3:3
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE            0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE             0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A                4:4
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B                5:5
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS             6:6
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE       0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE        0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS                    7:7
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE              0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE               0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI                          9:9
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE                    0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE                     0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9                              0x00000009
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18                0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24                1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18                  2:2
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE            0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE             0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24                  3:3
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE            0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE             0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A                4:4
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B                5:5
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE          0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE           0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS             6:6
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE       0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE        0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS                    7:7
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE              0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE               0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI                          9:9
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE                    0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE                     0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10                            0x0000000A
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC               0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC                 1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE           0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE            0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11                            0x0000000B
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC               0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC                 1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE           0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE            0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12                            0x0000000C
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC               0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC                 1:1
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE           0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE            0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13                            0x0000000D
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE                     0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE               0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE                0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0                         31:2
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14                            0x0000000E
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444          14:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1                         15:15
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422          30:16
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2                         31:31
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15                            0x0000000F
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444          14:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3                         15:15
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422          30:16
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4                         31:31
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16                            0x00000010
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444          14:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5                         15:15
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422          30:16
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6                         31:31
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17                            0x00000011
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE                     0:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE               0x00000000
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE                0x00000001
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0                         31:2
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18                            0x00000012
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444          14:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1                         15:15
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422          30:16
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2                         31:31
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19                            0x00000013
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444          14:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3                         15:15
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422          30:16
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4                         31:31
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20                            0x00000014
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444          14:0
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5                         15:15
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422          30:16
-#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6                         31:31
-
-
-// dma opcode instructions
-#define NV507D_DMA                                     0x00000000 
-#define NV507D_DMA_OPCODE                                   31:29 
-#define NV507D_DMA_OPCODE_METHOD                       0x00000000 
-#define NV507D_DMA_OPCODE_JUMP                         0x00000001 
-#define NV507D_DMA_OPCODE_NONINC_METHOD                0x00000002 
-#define NV507D_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
-#define NV507D_DMA_OPCODE                                   31:29 
-#define NV507D_DMA_OPCODE_METHOD                       0x00000000 
-#define NV507D_DMA_OPCODE_NONINC_METHOD                0x00000002 
-#define NV507D_DMA_METHOD_COUNT                             27:18 
-#define NV507D_DMA_METHOD_OFFSET                             11:2 
-#define NV507D_DMA_DATA                                      31:0 
-#define NV507D_DMA_NOP                                 0x00000000 
-#define NV507D_DMA_OPCODE                                   31:29 
-#define NV507D_DMA_OPCODE_JUMP                         0x00000001 
-#define NV507D_DMA_JUMP_OFFSET                               11:2 
-#define NV507D_DMA_OPCODE                                   31:29 
-#define NV507D_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
-#define NV507D_DMA_SET_SUBDEVICE_MASK_VALUE                  11:0 
-
-// class methods
-#define NV507D_PUT                                                              (0x00000000)
-#define NV507D_PUT_PTR                                                          11:2
-#define NV507D_GET                                                              (0x00000004)
-#define NV507D_GET_PTR                                                          11:2
-#define NV507D_UPDATE                                                           (0x00000080)
-#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
-#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV507D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV507D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
-#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV507D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV507D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV507D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV507D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV507D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV507D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV507D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV507D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV507D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV507D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV507D_SET_SPARE                                                        (0x000003BC)
-#define NV507D_SET_SPARE_UNUSED                                                 31:0
-#define NV507D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV507D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV507D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
-#define NV507D_DAC_SET_CONTROL_OWNER                                            3:0
-#define NV507D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV507D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV507D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV507D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV507D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV507D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL                                         13:8
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
-#define NV507D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
-#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
-#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
-#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
-#define NV507D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
-#define NV507D_DAC_SET_POLARITY_HSYNC                                           0:0
-#define NV507D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV507D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV507D_DAC_SET_POLARITY_VSYNC                                           1:1
-#define NV507D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV507D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV507D_DAC_SET_POLARITY_RESERVED                                        31:2
-#define NV507D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
-#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
-#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
-#define NV507D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
-#define NV507D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
-#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
-
-#define NV507D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
-#define NV507D_SOR_SET_CONTROL_OWNER                                            3:0
-#define NV507D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV507D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV507D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV507D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV507D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV507D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
-#define NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
-#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
-#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-
-#define NV507D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
-#define NV507D_PIOR_SET_CONTROL_OWNER                                           3:0
-#define NV507D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
-#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
-#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
-#define NV507D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
-#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
-#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
-#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
-#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
-#define NV507D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
-#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
-#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-
-#define NV507D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
-#define NV507D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV507D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV507D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
-#define NV507D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
-#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
-#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
-#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
-#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
-#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
-#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
-#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
-#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
-#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
-#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
-#define NV507D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
-#define NV507D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
-#define NV507D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV507D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
-#define NV507D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV507D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV507D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV507D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
-#define NV507D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV507D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV507D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
-#define NV507D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV507D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV507D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
-#define NV507D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV507D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV507D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
-#define NV507D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV507D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV507D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
-#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
-#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
-#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
-#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV507D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
-#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV507D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
-#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV507D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
-#define NV507D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
-#define NV507D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
-#define NV507D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
-#define NV507D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV507D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
-#define NV507D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV507D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
-#define NV507D_HEAD_SET_SIZE_WIDTH                                              14:0
-#define NV507D_HEAD_SET_SIZE_HEIGHT                                             30:16
-#define NV507D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
-#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV507D_HEAD_SET_STORAGE_PITCH                                           17:8
-#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
-#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV507D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
-#define NV507D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV507D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV507D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV507D_HEAD_SET_PARAMS_KIND                                             22:16
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH                                  (0x00000000)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2                           (0x00000070)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ                  (0x00000072)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1                          (0x00000074)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ                 (0x00000076)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4                                (0x00000078)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8                                (0x00000079)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ                       (0x0000007A)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ                       (0x0000007B)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS4                                (0x0000007C)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS8                                (0x0000007D)
-#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C128_MS4                               (0x0000007E)
-#define NV507D_HEAD_SET_PARAMS_KIND_FROM_PTE                                    (0x0000007F)
-#define NV507D_HEAD_SET_PARAMS_PART_STRIDE                                      24:24
-#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256                       (0x00000000)
-#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024                      (0x00000001)
-#define NV507D_HEAD_SET_CONTEXT_DMA_ISO(a)                                      (0x00000874 + (a)*0x00000400)
-#define NV507D_HEAD_SET_CONTEXT_DMA_ISO_HANDLE                                  31:0
-#define NV507D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
-#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
-#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
-#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
-#define NV507D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
-#define NV507D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
-#define NV507D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
-#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV507D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV507D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV507D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV507D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
-#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV507D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV507D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV507D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
-#define NV507D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
-#define NV507D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
-#define NV507D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
-#define NV507D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
-#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
-#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV507D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
-#define NV507D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV507D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV507D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl507d_h
-
diff --git a/Display-Class-Methods/cl507e.h b/Display-Class-Methods/cl507e.h
deleted file mode 100644
index 1827276..0000000
--- a/Display-Class-Methods/cl507e.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl507e_h_
-#define _cl507e_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV507E_OVERLAY_CHANNEL_DMA                                              (0x0000507E)
-
-#define NV_DISP_OVERLAY_NOTIFIER_1                                                   0x00000000
-#define NV_DISP_OVERLAY_NOTIFIER_1_SIZEOF                                            0x00000008
-#define NV_DISP_OVERLAY_NOTIFIER_1__0                                                0x00000000
-#define NV_DISP_OVERLAY_NOTIFIER_1__0_PRESENT_COUNT                                  15:0
-#define NV_DISP_OVERLAY_NOTIFIER_1__0_TIMESTAMP                                      29:16
-#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS                                         31:30
-#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_NOT_BEGUN                               0x00000000
-#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_BEGUN                                   0x00000001
-#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_FINISHED                                0x00000002
-#define NV_DISP_OVERLAY_NOTIFIER_1__1                                                0x00000001
-#define NV_DISP_OVERLAY_NOTIFIER_1__1_PRESENT_START_TIME                             31:0
-
-
-// dma opcode instructions
-#define NV507E_DMA                                     0x00000000 
-#define NV507E_DMA_OPCODE                                   31:29 
-#define NV507E_DMA_OPCODE_METHOD                       0x00000000 
-#define NV507E_DMA_OPCODE_JUMP                         0x00000001 
-#define NV507E_DMA_OPCODE_NONINC_METHOD                0x00000002 
-#define NV507E_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
-#define NV507E_DMA_OPCODE                                   31:29 
-#define NV507E_DMA_OPCODE_METHOD                       0x00000000 
-#define NV507E_DMA_OPCODE_NONINC_METHOD                0x00000002 
-#define NV507E_DMA_METHOD_COUNT                             27:18 
-#define NV507E_DMA_METHOD_OFFSET                             11:2 
-#define NV507E_DMA_DATA                                      31:0 
-#define NV507E_DMA_NOP                                 0x00000000 
-#define NV507E_DMA_OPCODE                                   31:29 
-#define NV507E_DMA_OPCODE_JUMP                         0x00000001 
-#define NV507E_DMA_JUMP_OFFSET                               11:2 
-#define NV507E_DMA_OPCODE                                   31:29 
-#define NV507E_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
-#define NV507E_DMA_SET_SUBDEVICE_MASK_VALUE                  11:0 
-
-// class methods
-#define NV507E_PUT                                                              (0x00000000)
-#define NV507E_PUT_PTR                                                          11:2
-#define NV507E_GET                                                              (0x00000004)
-#define NV507E_GET_PTR                                                          11:2
-#define NV507E_UPDATE                                                           (0x00000080)
-#define NV507E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV507E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV507E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV507E_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
-#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
-#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
-#define NV507E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV507E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
-#define NV507E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV507E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
-#define NV507E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV507E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
-#define NV507E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV507E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV507E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV507E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV507E_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV507E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV507E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV507E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV507E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV507E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV507E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
-#define NV507E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
-#define NV507E_SET_POINT_IN                                                     (0x000000E0)
-#define NV507E_SET_POINT_IN_X                                                   14:0
-#define NV507E_SET_POINT_IN_Y                                                   30:16
-#define NV507E_SET_SIZE_IN                                                      (0x000000E4)
-#define NV507E_SET_SIZE_IN_WIDTH                                                14:0
-#define NV507E_SET_SIZE_IN_HEIGHT                                               30:16
-#define NV507E_SET_SIZE_OUT                                                     (0x000000E8)
-#define NV507E_SET_SIZE_OUT_WIDTH                                               14:0
-#define NV507E_SET_COMPOSITION_CONTROL                                          (0x00000100)
-#define NV507E_SET_COMPOSITION_CONTROL_MODE                                     3:0
-#define NV507E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
-#define NV507E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
-#define NV507E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
-#define NV507E_SET_KEY_COLOR                                                    (0x00000104)
-#define NV507E_SET_KEY_COLOR_COLOR                                              31:0
-#define NV507E_SET_KEY_MASK                                                     (0x00000108)
-#define NV507E_SET_KEY_MASK_MASK                                                31:0
-#define NV507E_SET_TIMESTAMP_VALUE                                              (0x00000120)
-#define NV507E_SET_TIMESTAMP_VALUE_TIMESTAMP                                    31:0
-#define NV507E_SET_UPDATE_TIMESTAMP                                             (0x00000124)
-#define NV507E_SET_UPDATE_TIMESTAMP_TIMESTAMP                                   31:0
-#define NV507E_SET_SPARE                                                        (0x000007BC)
-#define NV507E_SET_SPARE_UNUSED                                                 31:0
-#define NV507E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV507E_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV507E_SURFACE_SET_OFFSET                                               (0x00000800)
-#define NV507E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV507E_SURFACE_SET_SIZE                                                 (0x00000808)
-#define NV507E_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV507E_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV507E_SURFACE_SET_STORAGE                                              (0x0000080C)
-#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV507E_SURFACE_SET_STORAGE_PITCH                                        17:8
-#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV507E_SURFACE_SET_PARAMS                                               (0x00000810)
-#define NV507E_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
-#define NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
-#define NV507E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV507E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
-#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
-#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
-#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
-#define NV507E_SURFACE_SET_PARAMS_KIND                                          22:16
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_PITCH                               (0x00000000)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2                        (0x00000070)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ               (0x00000072)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1                       (0x00000074)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ              (0x00000076)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4                             (0x00000078)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8                             (0x00000079)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ                    (0x0000007A)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ                    (0x0000007B)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4                             (0x0000007C)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8                             (0x0000007D)
-#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4                            (0x0000007E)
-#define NV507E_SURFACE_SET_PARAMS_KIND_FROM_PTE                                 (0x0000007F)
-#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE                                   24:24
-#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256                    (0x00000000)
-#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024                   (0x00000001)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl507e_h
-
diff --git a/Display-Class-Methods/cl827a.h b/Display-Class-Methods/cl827a.h
deleted file mode 100644
index bd10ceb..0000000
--- a/Display-Class-Methods/cl827a.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl827a_h_
-#define _cl827a_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV827A_CURSOR_CHANNEL_PIO                                               (0x0000827A)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
-    NvV32 Reserved02[0x3DE];
-} G82DispCursorControlPio;
-
-#define NV827A_FREE                                                             (0x00000008)
-#define NV827A_FREE_COUNT                                                       5:0
-#define NV827A_UPDATE                                                           (0x00000080)
-#define NV827A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV827A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV827A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
-#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
-#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl827a_h
-
diff --git a/Display-Class-Methods/cl827b.h b/Display-Class-Methods/cl827b.h
deleted file mode 100644
index f85bfc2..0000000
--- a/Display-Class-Methods/cl827b.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl827b_h_
-#define _cl827b_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV827B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000827B)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
-    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
-    NvV32 Reserved02[0x3DD];
-} G82DispOverlayImmControlPio;
-
-#define NV827B_FREE                                                             (0x00000008)
-#define NV827B_FREE_COUNT                                                       5:0
-#define NV827B_UPDATE                                                           (0x00000080)
-#define NV827B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV827B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV827B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV827B_SET_POINT_OUT                                                    (0x00000084)
-#define NV827B_SET_POINT_OUT_X                                                  15:0
-#define NV827B_SET_POINT_OUT_Y                                                  31:16
-#define NV827B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
-#define NV827B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl827b_h
-
diff --git a/Display-Class-Methods/cl827c.h b/Display-Class-Methods/cl827c.h
deleted file mode 100644
index a92df84..0000000
--- a/Display-Class-Methods/cl827c.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl827c_h_
-#define _cl827c_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV827C_BASE_CHANNEL_DMA                                                 (0x0000827C)
-
-#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
-#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
-#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
-
-
-// dma opcode instructions
-#define NV827C_DMA                                                         0x00000000 
-#define NV827C_DMA_OPCODE                                                       31:29 
-#define NV827C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV827C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV827C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV827C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV827C_DMA_OPCODE                                                       31:29 
-#define NV827C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV827C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV827C_DMA_METHOD_COUNT                                                 27:18 
-#define NV827C_DMA_METHOD_OFFSET                                                 11:2 
-#define NV827C_DMA_DATA                                                          31:0 
-#define NV827C_DMA_NOP                                                     0x00000000 
-#define NV827C_DMA_OPCODE                                                       31:29 
-#define NV827C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV827C_DMA_JUMP_OFFSET                                                   11:2 
-#define NV827C_DMA_OPCODE                                                       31:29 
-#define NV827C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV827C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV827C_PUT                                                              (0x00000000)
-#define NV827C_PUT_PTR                                                          11:2
-#define NV827C_GET                                                              (0x00000004)
-#define NV827C_GET_PTR                                                          11:2
-#define NV827C_GET_SCANLINE                                                     (0x00000010)
-#define NV827C_GET_SCANLINE_LINE                                                15:0
-#define NV827C_UPDATE                                                           (0x00000080)
-#define NV827C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV827C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV827C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV827C_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
-#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
-#define NV827C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV827C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
-#define NV827C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
-#define NV827C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
-#define NV827C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV827C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
-#define NV827C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV827C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
-#define NV827C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV827C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV827C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV827C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV827C_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV827C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV827C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV827C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV827C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV827C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV827C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
-#define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
-#define NV827C_SET_BASE_LUT_LO                                                  (0x000000E0)
-#define NV827C_SET_BASE_LUT_LO_ENABLE                                           31:30
-#define NV827C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
-#define NV827C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
-#define NV827C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
-#define NV827C_SET_BASE_LUT_LO_MODE                                             29:29
-#define NV827C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
-#define NV827C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
-#define NV827C_SET_BASE_LUT_LO_ORIGIN                                           7:2
-#define NV827C_SET_BASE_LUT_HI                                                  (0x000000E4)
-#define NV827C_SET_BASE_LUT_HI_ORIGIN                                           31:0
-#define NV827C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
-#define NV827C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
-#define NV827C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
-#define NV827C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
-#define NV827C_SET_OUTPUT_LUT_LO_MODE                                           30:30
-#define NV827C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
-#define NV827C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
-#define NV827C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
-#define NV827C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
-#define NV827C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
-#define NV827C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
-#define NV827C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV827C_SET_PROCESSING                                                   (0x00000110)
-#define NV827C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV827C_SET_CONVERSION                                                   (0x00000114)
-#define NV827C_SET_CONVERSION_GAIN                                              15:0
-#define NV827C_SET_CONVERSION_OFS                                               31:16
-#define NV827C_SET_SPARE                                                        (0x000007BC)
-#define NV827C_SET_SPARE_UNUSED                                                 31:0
-#define NV827C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV827C_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV827C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
-#define NV827C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV827C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
-#define NV827C_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV827C_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV827C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
-#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV827C_SURFACE_SET_STORAGE_PITCH                                        17:8
-#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV827C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
-#define NV827C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
-#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
-#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
-#define NV827C_SURFACE_SET_PARAMS_GAMMA                                         2:2
-#define NV827C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
-#define NV827C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
-#define NV827C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
-#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
-#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
-#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
-#define NV827C_SURFACE_SET_PARAMS_RESERVED0                                     22:16
-#define NV827C_SURFACE_SET_PARAMS_RESERVED1                                     24:24
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl827c_h
-
diff --git a/Display-Class-Methods/cl827d.h b/Display-Class-Methods/cl827d.h
deleted file mode 100644
index 7294769..0000000
--- a/Display-Class-Methods/cl827d.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl827d_h_
-#define _cl827d_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV827D_CORE_CHANNEL_DMA                                                 (0x0000827D)
-
-#define NV827D_CORE_NOTIFIER_1                                                      0x00000000
-#define NV827D_CORE_NOTIFIER_1_SIZEOF                                               0x00000054
-#define NV827D_CORE_NOTIFIER_1_COMPLETION_0                                         0x00000000
-#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE                                    0:0
-#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_R0                                      15:1
-#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP                               29:16
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1                                       0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE                                  0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE                            0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE                             0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO                         1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_R0                                    3:3
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_R1                                    31:22
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_2                                       0x00000002
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_2_R2                                    31:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_3                                       0x00000003
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_3_R3                                    31:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_4                                       0x00000004
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_4_R4                                    31:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5                              0x00000005
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE                   0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE             0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE              0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE                    1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE              0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE               0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE                 3:3
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE           0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE            0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6                              0x00000006
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE                   0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE             0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE              0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE                    1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE              0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE               0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE                 3:3
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE           0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE            0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7                              0x00000007
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE                   0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE             0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE              0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE                    1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE              0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE               0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE                 3:3
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE           0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE            0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8                              0x00000008
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18                0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24                1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18                  2:2
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE            0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE             0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24                  3:3
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE            0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE             0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A                4:4
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B                5:5
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS             6:6
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE       0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE        0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS                    7:7
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE              0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE               0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI                          9:9
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE                    0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE                     0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9                              0x00000009
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18                0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24                1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18                  2:2
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE            0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE             0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24                  3:3
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE            0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE             0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A                4:4
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B                5:5
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE          0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE           0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS             6:6
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE       0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE        0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS                    7:7
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE              0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE               0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI                          9:9
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE                    0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE                     0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10                            0x0000000A
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC               0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC                 1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE           0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE            0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11                            0x0000000B
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC               0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC                 1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE           0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE            0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12                            0x0000000C
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC               0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC                 1:1
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE           0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE            0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13                            0x0000000D
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE                     0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE               0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE                0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0                         31:2
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14                            0x0000000E
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444          14:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1                         15:15
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422          30:16
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2                         31:31
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15                            0x0000000F
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444          14:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3                         15:15
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422          30:16
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4                         31:31
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16                            0x00000010
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444          14:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5                         15:15
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422          30:16
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6                         31:31
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17                            0x00000011
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE                     0:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE               0x00000000
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE                0x00000001
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0                         31:2
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18                            0x00000012
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444          14:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1                         15:15
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422          30:16
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2                         31:31
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19                            0x00000013
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444          14:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3                         15:15
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422          30:16
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4                         31:31
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20                            0x00000014
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444          14:0
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5                         15:15
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422          30:16
-#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6                         31:31
-
-
-// dma opcode instructions
-#define NV827D_DMA                                                         0x00000000 
-#define NV827D_DMA_OPCODE                                                       31:29 
-#define NV827D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV827D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV827D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV827D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV827D_DMA_OPCODE                                                       31:29 
-#define NV827D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV827D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV827D_DMA_METHOD_COUNT                                                 27:18 
-#define NV827D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV827D_DMA_DATA                                                          31:0 
-#define NV827D_DMA_NOP                                                     0x00000000 
-#define NV827D_DMA_OPCODE                                                       31:29 
-#define NV827D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV827D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV827D_DMA_OPCODE                                                       31:29 
-#define NV827D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV827D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV827D_PUT                                                              (0x00000000)
-#define NV827D_PUT_PTR                                                          11:2
-#define NV827D_GET                                                              (0x00000004)
-#define NV827D_GET_PTR                                                          11:2
-#define NV827D_UPDATE                                                           (0x00000080)
-#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
-#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV827D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV827D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV827D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
-#define NV827D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV827D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV827D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV827D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV827D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV827D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV827D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV827D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV827D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV827D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV827D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV827D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV827D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV827D_SET_SPARE                                                        (0x000003BC)
-#define NV827D_SET_SPARE_UNUSED                                                 31:0
-#define NV827D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV827D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV827D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
-#define NV827D_DAC_SET_CONTROL_OWNER                                            3:0
-#define NV827D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV827D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV827D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV827D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV827D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV827D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV827D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV827D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL                                         13:8
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
-#define NV827D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
-#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
-#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
-#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
-#define NV827D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
-#define NV827D_DAC_SET_POLARITY_HSYNC                                           0:0
-#define NV827D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV827D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV827D_DAC_SET_POLARITY_VSYNC                                           1:1
-#define NV827D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV827D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV827D_DAC_SET_POLARITY_RESERVED                                        31:2
-#define NV827D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
-#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
-#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
-#define NV827D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
-#define NV827D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
-#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
-
-#define NV827D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
-#define NV827D_SOR_SET_CONTROL_OWNER                                            3:0
-#define NV827D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV827D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV827D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV827D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV827D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV827D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV827D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV827D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
-#define NV827D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
-#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
-#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-
-#define NV827D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
-#define NV827D_PIOR_SET_CONTROL_OWNER                                           3:0
-#define NV827D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
-#define NV827D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
-#define NV827D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
-#define NV827D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
-#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
-#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
-#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
-#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
-#define NV827D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV827D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV827D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
-#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
-#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-
-#define NV827D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
-#define NV827D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV827D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV827D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
-#define NV827D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
-#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
-#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
-#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
-#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
-#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
-#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
-#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
-#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
-#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
-#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
-#define NV827D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
-#define NV827D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
-#define NV827D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV827D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
-#define NV827D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV827D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV827D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV827D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
-#define NV827D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV827D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV827D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
-#define NV827D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV827D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV827D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
-#define NV827D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV827D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV827D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
-#define NV827D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV827D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV827D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
-#define NV827D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV827D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV827D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
-#define NV827D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
-#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
-#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV827D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
-#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV827D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
-#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV827D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
-#define NV827D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
-#define NV827D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
-#define NV827D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
-#define NV827D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV827D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
-#define NV827D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV827D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
-#define NV827D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV827D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
-#define NV827D_HEAD_SET_SIZE_WIDTH                                              14:0
-#define NV827D_HEAD_SET_SIZE_HEIGHT                                             30:16
-#define NV827D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
-#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV827D_HEAD_SET_STORAGE_PITCH                                           17:8
-#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
-#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV827D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
-#define NV827D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV827D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV827D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV827D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV827D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV827D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV827D_HEAD_SET_PARAMS_RESERVED0                                        22:16
-#define NV827D_HEAD_SET_PARAMS_RESERVED1                                        24:24
-#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
-#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV827D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
-#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
-#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
-#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
-#define NV827D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
-#define NV827D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
-#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
-#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
-#define NV827D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
-#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV827D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV827D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV827D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV827D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV827D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV827D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
-#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV827D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV827D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV827D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
-#define NV827D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
-#define NV827D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
-#define NV827D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
-#define NV827D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
-#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
-#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV827D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
-#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV827D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
-#define NV827D_HEAD_SET_CONVERSION_GAIN                                         15:0
-#define NV827D_HEAD_SET_CONVERSION_OFS                                          31:16
-#define NV827D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
-#define NV827D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV827D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV827D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl827d_h
-
diff --git a/Display-Class-Methods/cl827e.h b/Display-Class-Methods/cl827e.h
deleted file mode 100644
index b142fd1..0000000
--- a/Display-Class-Methods/cl827e.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl827e_h_
-#define _cl827e_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV827E_OVERLAY_CHANNEL_DMA                                              (0x0000827E)
-
-#define NV_DISP_NOTIFICATION_1                                                       0x00000000
-#define NV_DISP_NOTIFICATION_1_SIZEOF                                                0x00000010
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0                                          0x00000000
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0                             31:0
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1                                          0x00000001
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1                             31:0
-#define NV_DISP_NOTIFICATION_1__2                                                    0x00000002
-#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP                                    31:0
-#define NV_DISP_NOTIFICATION_1__3                                                    0x00000003
-#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT                                      7:0
-#define NV_DISP_NOTIFICATION_1__3_R0                                                 15:8
-#define NV_DISP_NOTIFICATION_1__3_STATUS                                             31:16
-#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN                                   0x00008000
-#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN                                       0x0000FFFF
-#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED                                    0x00000000
-
-
-#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
-#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
-#define NV_DISP_NOTIFICATION_INFO16__0_R0                                            15:8
-
-
-#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
-#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
-
-
-// dma opcode instructions
-#define NV827E_DMA                                                         0x00000000 
-#define NV827E_DMA_OPCODE                                                       31:29 
-#define NV827E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV827E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV827E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV827E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV827E_DMA_OPCODE                                                       31:29 
-#define NV827E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV827E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV827E_DMA_METHOD_COUNT                                                 27:18 
-#define NV827E_DMA_METHOD_OFFSET                                                 11:2 
-#define NV827E_DMA_DATA                                                          31:0 
-#define NV827E_DMA_NOP                                                     0x00000000 
-#define NV827E_DMA_OPCODE                                                       31:29 
-#define NV827E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV827E_DMA_JUMP_OFFSET                                                   11:2 
-#define NV827E_DMA_OPCODE                                                       31:29 
-#define NV827E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV827E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV827E_PUT                                                              (0x00000000)
-#define NV827E_PUT_PTR                                                          11:2
-#define NV827E_GET                                                              (0x00000004)
-#define NV827E_GET_PTR                                                          11:2
-#define NV827E_UPDATE                                                           (0x00000080)
-#define NV827E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV827E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV827E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV827E_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
-#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
-#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
-#define NV827E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV827E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
-#define NV827E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV827E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
-#define NV827E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV827E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
-#define NV827E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV827E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV827E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV827E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV827E_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV827E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV827E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV827E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV827E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV827E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV827E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
-#define NV827E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
-#define NV827E_SET_POINT_IN                                                     (0x000000E0)
-#define NV827E_SET_POINT_IN_X                                                   14:0
-#define NV827E_SET_POINT_IN_Y                                                   30:16
-#define NV827E_SET_SIZE_IN                                                      (0x000000E4)
-#define NV827E_SET_SIZE_IN_WIDTH                                                14:0
-#define NV827E_SET_SIZE_IN_HEIGHT                                               30:16
-#define NV827E_SET_SIZE_OUT                                                     (0x000000E8)
-#define NV827E_SET_SIZE_OUT_WIDTH                                               14:0
-#define NV827E_SET_COMPOSITION_CONTROL                                          (0x00000100)
-#define NV827E_SET_COMPOSITION_CONTROL_MODE                                     3:0
-#define NV827E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
-#define NV827E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
-#define NV827E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
-#define NV827E_SET_KEY_COLOR                                                    (0x00000104)
-#define NV827E_SET_KEY_COLOR_COLOR                                              31:0
-#define NV827E_SET_KEY_MASK                                                     (0x00000108)
-#define NV827E_SET_KEY_MASK_MASK                                                31:0
-#define NV827E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV827E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV827E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV827E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV827E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV827E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV827E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV827E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV827E_SET_SPARE                                                        (0x000007BC)
-#define NV827E_SET_SPARE_UNUSED                                                 31:0
-#define NV827E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV827E_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV827E_SURFACE_SET_OFFSET                                               (0x00000800)
-#define NV827E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV827E_SURFACE_SET_SIZE                                                 (0x00000808)
-#define NV827E_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV827E_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV827E_SURFACE_SET_STORAGE                                              (0x0000080C)
-#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV827E_SURFACE_SET_STORAGE_PITCH                                        17:8
-#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV827E_SURFACE_SET_PARAMS                                               (0x00000810)
-#define NV827E_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV827E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
-#define NV827E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
-#define NV827E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV827E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV827E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
-#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
-#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
-#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
-#define NV827E_SURFACE_SET_PARAMS_RESERVED0                                     22:16
-#define NV827E_SURFACE_SET_PARAMS_RESERVED1                                     24:24
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl827e_h
-
diff --git a/Display-Class-Methods/cl837c.h b/Display-Class-Methods/cl837c.h
deleted file mode 100644
index a05d3f2..0000000
--- a/Display-Class-Methods/cl837c.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl837c_h_
-#define _cl837c_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV837C_BASE_CHANNEL_DMA                                                 (0x0000837C)
-
-#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
-#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
-#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
-
-
-// dma opcode instructions
-#define NV837C_DMA                                                         0x00000000 
-#define NV837C_DMA_OPCODE                                                       31:29 
-#define NV837C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV837C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV837C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV837C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV837C_DMA_OPCODE                                                       31:29 
-#define NV837C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV837C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV837C_DMA_METHOD_COUNT                                                 27:18 
-#define NV837C_DMA_METHOD_OFFSET                                                 11:2 
-#define NV837C_DMA_DATA                                                          31:0 
-#define NV837C_DMA_NOP                                                     0x00000000 
-#define NV837C_DMA_OPCODE                                                       31:29 
-#define NV837C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV837C_DMA_JUMP_OFFSET                                                   11:2 
-#define NV837C_DMA_OPCODE                                                       31:29 
-#define NV837C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV837C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV837C_PUT                                                              (0x00000000)
-#define NV837C_PUT_PTR                                                          11:2
-#define NV837C_GET                                                              (0x00000004)
-#define NV837C_GET_PTR                                                          11:2
-#define NV837C_GET_SCANLINE                                                     (0x00000010)
-#define NV837C_GET_SCANLINE_LINE                                                15:0
-#define NV837C_UPDATE                                                           (0x00000080)
-#define NV837C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV837C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV837C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV837C_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
-#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
-#define NV837C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV837C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
-#define NV837C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
-#define NV837C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
-#define NV837C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV837C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
-#define NV837C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV837C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
-#define NV837C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV837C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV837C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV837C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV837C_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV837C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV837C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV837C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV837C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV837C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV837C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
-#define NV837C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
-#define NV837C_SET_BASE_LUT_LO                                                  (0x000000E0)
-#define NV837C_SET_BASE_LUT_LO_ENABLE                                           31:30
-#define NV837C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
-#define NV837C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
-#define NV837C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
-#define NV837C_SET_BASE_LUT_LO_MODE                                             29:29
-#define NV837C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
-#define NV837C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
-#define NV837C_SET_BASE_LUT_LO_ORIGIN                                           7:2
-#define NV837C_SET_BASE_LUT_HI                                                  (0x000000E4)
-#define NV837C_SET_BASE_LUT_HI_ORIGIN                                           31:0
-#define NV837C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
-#define NV837C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
-#define NV837C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
-#define NV837C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
-#define NV837C_SET_OUTPUT_LUT_LO_MODE                                           30:30
-#define NV837C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
-#define NV837C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
-#define NV837C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
-#define NV837C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
-#define NV837C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
-#define NV837C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
-#define NV837C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV837C_SET_PROCESSING                                                   (0x00000110)
-#define NV837C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV837C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV837C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV837C_SET_CONVERSION                                                   (0x00000114)
-#define NV837C_SET_CONVERSION_GAIN                                              15:0
-#define NV837C_SET_CONVERSION_OFS                                               31:16
-#define NV837C_SET_SPARE                                                        (0x000007BC)
-#define NV837C_SET_SPARE_UNUSED                                                 31:0
-#define NV837C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV837C_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV837C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
-#define NV837C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV837C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
-#define NV837C_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV837C_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV837C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
-#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV837C_SURFACE_SET_STORAGE_PITCH                                        17:8
-#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV837C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
-#define NV837C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
-#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
-#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
-#define NV837C_SURFACE_SET_PARAMS_GAMMA                                         2:2
-#define NV837C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
-#define NV837C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
-#define NV837C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
-#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
-#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
-#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
-#define NV837C_SURFACE_SET_PARAMS_RESERVED0                                     22:16
-#define NV837C_SURFACE_SET_PARAMS_RESERVED1                                     24:24
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl837c_h
-
diff --git a/Display-Class-Methods/cl837d.h b/Display-Class-Methods/cl837d.h
deleted file mode 100644
index 57c04f2..0000000
--- a/Display-Class-Methods/cl837d.h
+++ /dev/null
@@ -1,709 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl837d_h_
-#define _cl837d_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV837D_CORE_CHANNEL_DMA                                                 (0x0000837D)
-
-#define NV837D_CORE_NOTIFIER_1                                                      0x00000000
-#define NV837D_CORE_NOTIFIER_1_SIZEOF                                               0x00000054
-#define NV837D_CORE_NOTIFIER_1_COMPLETION_0                                         0x00000000
-#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE                                    0:0
-#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_R0                                      15:1
-#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP                               29:16
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1                                       0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE                                  0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE                            0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE                             0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO                         1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_R0                                    3:3
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_R1                                    31:22
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_2                                       0x00000002
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_2_R2                                    31:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_3                                       0x00000003
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_3_R3                                    31:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_4                                       0x00000004
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_4_R4                                    31:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5                              0x00000005
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE                   0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE             0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE              0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE                    1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE              0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE               0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE                 3:3
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE           0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE            0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6                              0x00000006
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE                   0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE             0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE              0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE                    1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE              0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE               0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE                 3:3
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE           0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE            0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7                              0x00000007
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE                   0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE             0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE              0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE                    1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE              0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE               0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE                 3:3
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE           0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE            0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8                              0x00000008
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18                0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24                1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18                  2:2
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE            0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE             0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24                  3:3
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE            0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE             0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A                4:4
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B                5:5
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS             6:6
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE       0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE        0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS                    7:7
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE              0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE               0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI                          9:9
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE                    0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE                     0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9                              0x00000009
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18                0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24                1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18                  2:2
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE            0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE             0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24                  3:3
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE            0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE             0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A                4:4
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B                5:5
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE          0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE           0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS             6:6
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE       0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE        0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS                    7:7
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE              0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE               0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI                          9:9
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE                    0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE                     0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10                            0x0000000A
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC               0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC                 1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE           0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE            0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11                            0x0000000B
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC               0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC                 1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE           0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE            0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12                            0x0000000C
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC               0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC                 1:1
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE           0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE            0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13                            0x0000000D
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE                     0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE               0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE                0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0                         31:2
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14                            0x0000000E
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444          14:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1                         15:15
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422          30:16
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2                         31:31
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15                            0x0000000F
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444          14:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3                         15:15
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422          30:16
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4                         31:31
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16                            0x00000010
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444          14:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5                         15:15
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422          30:16
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6                         31:31
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17                            0x00000011
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE                     0:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE               0x00000000
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE                0x00000001
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0                         31:2
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18                            0x00000012
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444          14:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1                         15:15
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422          30:16
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2                         31:31
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19                            0x00000013
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444          14:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3                         15:15
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422          30:16
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4                         31:31
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20                            0x00000014
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444          14:0
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5                         15:15
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422          30:16
-#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6                         31:31
-
-
-// dma opcode instructions
-#define NV837D_DMA                                                         0x00000000 
-#define NV837D_DMA_OPCODE                                                       31:29 
-#define NV837D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV837D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV837D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV837D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV837D_DMA_OPCODE                                                       31:29 
-#define NV837D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV837D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV837D_DMA_METHOD_COUNT                                                 27:18 
-#define NV837D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV837D_DMA_DATA                                                          31:0 
-#define NV837D_DMA_NOP                                                     0x00000000 
-#define NV837D_DMA_OPCODE                                                       31:29 
-#define NV837D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV837D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV837D_DMA_OPCODE                                                       31:29 
-#define NV837D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV837D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV837D_PUT                                                              (0x00000000)
-#define NV837D_PUT_PTR                                                          11:2
-#define NV837D_GET                                                              (0x00000004)
-#define NV837D_GET_PTR                                                          11:2
-#define NV837D_UPDATE                                                           (0x00000080)
-#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
-#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV837D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV837D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV837D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
-#define NV837D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV837D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV837D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV837D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV837D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV837D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV837D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV837D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV837D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV837D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV837D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV837D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV837D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV837D_SET_SPARE                                                        (0x000003BC)
-#define NV837D_SET_SPARE_UNUSED                                                 31:0
-#define NV837D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV837D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV837D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
-#define NV837D_DAC_SET_CONTROL_OWNER                                            3:0
-#define NV837D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV837D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV837D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV837D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV837D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV837D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV837D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV837D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL                                         13:8
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
-#define NV837D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
-#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
-#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
-#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
-#define NV837D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
-#define NV837D_DAC_SET_POLARITY_HSYNC                                           0:0
-#define NV837D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV837D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV837D_DAC_SET_POLARITY_VSYNC                                           1:1
-#define NV837D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV837D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV837D_DAC_SET_POLARITY_RESERVED                                        31:2
-#define NV837D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
-#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
-#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
-#define NV837D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
-#define NV837D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
-#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
-
-#define NV837D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
-#define NV837D_SOR_SET_CONTROL_OWNER                                            3:0
-#define NV837D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV837D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV837D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV837D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
-#define NV837D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
-#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
-#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
-#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
-
-#define NV837D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
-#define NV837D_PIOR_SET_CONTROL_OWNER                                           3:0
-#define NV837D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
-#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
-#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
-#define NV837D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
-#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
-#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
-#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
-#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
-#define NV837D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
-#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
-#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH                                     19:16
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                             (0x00000000)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                          (0x00000001)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                          (0x00000002)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                          (0x00000003)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                          (0x00000004)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                          (0x00000005)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                          (0x00000006)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                          (0x00000007)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                          (0x00000008)
-#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                          (0x00000009)
-
-#define NV837D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
-#define NV837D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV837D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV837D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
-#define NV837D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
-#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
-#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
-#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
-#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
-#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
-#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
-#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
-#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
-#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
-#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
-#define NV837D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
-#define NV837D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
-#define NV837D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV837D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
-#define NV837D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV837D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV837D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV837D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
-#define NV837D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV837D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV837D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
-#define NV837D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV837D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV837D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
-#define NV837D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV837D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV837D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
-#define NV837D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV837D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV837D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
-#define NV837D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV837D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV837D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
-#define NV837D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
-#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
-#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV837D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
-#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV837D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
-#define NV837D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV837D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV837D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
-#define NV837D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
-#define NV837D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
-#define NV837D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
-#define NV837D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV837D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
-#define NV837D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV837D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
-#define NV837D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV837D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
-#define NV837D_HEAD_SET_SIZE_WIDTH                                              14:0
-#define NV837D_HEAD_SET_SIZE_HEIGHT                                             30:16
-#define NV837D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
-#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV837D_HEAD_SET_STORAGE_PITCH                                           17:8
-#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
-#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV837D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
-#define NV837D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV837D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV837D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV837D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV837D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV837D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV837D_HEAD_SET_PARAMS_RESERVED0                                        22:16
-#define NV837D_HEAD_SET_PARAMS_RESERVED1                                        24:24
-#define NV837D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
-#define NV837D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV837D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
-#define NV837D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
-#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
-#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
-#define NV837D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
-#define NV837D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
-#define NV837D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
-#define NV837D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
-#define NV837D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
-#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV837D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV837D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV837D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV837D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV837D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV837D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
-#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV837D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV837D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV837D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
-#define NV837D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
-#define NV837D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
-#define NV837D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
-#define NV837D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV837D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV837D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
-#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
-#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV837D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
-#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV837D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
-#define NV837D_HEAD_SET_CONVERSION_GAIN                                         15:0
-#define NV837D_HEAD_SET_CONVERSION_OFS                                          31:16
-#define NV837D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
-#define NV837D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV837D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV837D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl837d_h
-
diff --git a/Display-Class-Methods/cl837e.h b/Display-Class-Methods/cl837e.h
deleted file mode 100644
index 62cc069..0000000
--- a/Display-Class-Methods/cl837e.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl837e_h_
-#define _cl837e_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV837E_OVERLAY_CHANNEL_DMA                                              (0x0000837E)
-
-#define NV_DISP_NOTIFICATION_1                                                       0x00000000
-#define NV_DISP_NOTIFICATION_1_SIZEOF                                                0x00000010
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0                                          0x00000000
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0                             31:0
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1                                          0x00000001
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1                             31:0
-#define NV_DISP_NOTIFICATION_1__2                                                    0x00000002
-#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP                                    31:0
-#define NV_DISP_NOTIFICATION_1__3                                                    0x00000003
-#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT                                      7:0
-#define NV_DISP_NOTIFICATION_1__3_R0                                                 15:8
-#define NV_DISP_NOTIFICATION_1__3_STATUS                                             31:16
-#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN                                   0x00008000
-#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN                                       0x0000FFFF
-#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED                                    0x00000000
-
-
-#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
-#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
-#define NV_DISP_NOTIFICATION_INFO16__0_R0                                            15:8
-
-
-#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
-#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
-
-
-// dma opcode instructions
-#define NV837E_DMA                                                         0x00000000 
-#define NV837E_DMA_OPCODE                                                       31:29 
-#define NV837E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV837E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV837E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV837E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV837E_DMA_OPCODE                                                       31:29 
-#define NV837E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV837E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV837E_DMA_METHOD_COUNT                                                 27:18 
-#define NV837E_DMA_METHOD_OFFSET                                                 11:2 
-#define NV837E_DMA_DATA                                                          31:0 
-#define NV837E_DMA_NOP                                                     0x00000000 
-#define NV837E_DMA_OPCODE                                                       31:29 
-#define NV837E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV837E_DMA_JUMP_OFFSET                                                   11:2 
-#define NV837E_DMA_OPCODE                                                       31:29 
-#define NV837E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV837E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV837E_PUT                                                              (0x00000000)
-#define NV837E_PUT_PTR                                                          11:2
-#define NV837E_GET                                                              (0x00000004)
-#define NV837E_GET_PTR                                                          11:2
-#define NV837E_UPDATE                                                           (0x00000080)
-#define NV837E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV837E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV837E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV837E_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
-#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
-#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
-#define NV837E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV837E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
-#define NV837E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV837E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
-#define NV837E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV837E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
-#define NV837E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV837E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV837E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV837E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV837E_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV837E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV837E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV837E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV837E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV837E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV837E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
-#define NV837E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV837E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
-#define NV837E_SET_OVERLAY_LUT_LO_ENABLE                                        30:30
-#define NV837E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
-#define NV837E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
-#define NV837E_SET_OVERLAY_LUT_LO_MODE                                          29:29
-#define NV837E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
-#define NV837E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
-#define NV837E_SET_OVERLAY_LUT_LO_ORIGIN                                        7:2
-#define NV837E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
-#define NV837E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
-#define NV837E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
-#define NV837E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
-#define NV837E_SET_POINT_IN                                                     (0x000000E0)
-#define NV837E_SET_POINT_IN_X                                                   14:0
-#define NV837E_SET_POINT_IN_Y                                                   30:16
-#define NV837E_SET_SIZE_IN                                                      (0x000000E4)
-#define NV837E_SET_SIZE_IN_WIDTH                                                14:0
-#define NV837E_SET_SIZE_IN_HEIGHT                                               30:16
-#define NV837E_SET_SIZE_OUT                                                     (0x000000E8)
-#define NV837E_SET_SIZE_OUT_WIDTH                                               14:0
-#define NV837E_SET_COMPOSITION_CONTROL                                          (0x00000100)
-#define NV837E_SET_COMPOSITION_CONTROL_MODE                                     3:0
-#define NV837E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
-#define NV837E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
-#define NV837E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
-#define NV837E_SET_KEY_COLOR                                                    (0x00000104)
-#define NV837E_SET_KEY_COLOR_COLOR                                              31:0
-#define NV837E_SET_KEY_MASK                                                     (0x00000108)
-#define NV837E_SET_KEY_MASK_MASK                                                31:0
-#define NV837E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV837E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV837E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV837E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV837E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV837E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV837E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV837E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV837E_SET_SPARE                                                        (0x000007BC)
-#define NV837E_SET_SPARE_UNUSED                                                 31:0
-#define NV837E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV837E_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV837E_SURFACE_SET_OFFSET                                               (0x00000800)
-#define NV837E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV837E_SURFACE_SET_SIZE                                                 (0x00000808)
-#define NV837E_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV837E_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV837E_SURFACE_SET_STORAGE                                              (0x0000080C)
-#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV837E_SURFACE_SET_STORAGE_PITCH                                        17:8
-#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV837E_SURFACE_SET_PARAMS                                               (0x00000810)
-#define NV837E_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV837E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
-#define NV837E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
-#define NV837E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV837E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV837E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
-#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
-#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
-#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
-#define NV837E_SURFACE_SET_PARAMS_RESERVED0                                     22:16
-#define NV837E_SURFACE_SET_PARAMS_RESERVED1                                     24:24
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl837e_h
-
diff --git a/Display-Class-Methods/cl857a.h b/Display-Class-Methods/cl857a.h
deleted file mode 100644
index cc5fbca..0000000
--- a/Display-Class-Methods/cl857a.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl857a_h_
-#define _cl857a_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV857A_CURSOR_CHANNEL_PIO                                               (0x0000857A)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
-    NvV32 Reserved02[0x3DE];
-} GT214DispCursorControlPio;
-
-#define NV857A_FREE                                                             (0x00000008)
-#define NV857A_FREE_COUNT                                                       5:0
-#define NV857A_UPDATE                                                           (0x00000080)
-#define NV857A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV857A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV857A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
-#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
-#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl857a_h
-
diff --git a/Display-Class-Methods/cl857b.h b/Display-Class-Methods/cl857b.h
deleted file mode 100644
index a6c8c49..0000000
--- a/Display-Class-Methods/cl857b.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl857b_h_
-#define _cl857b_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV857B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000857B)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
-    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
-    NvV32 Reserved02[0x3DD];
-} GT214DispOverlayImmControlPio;
-
-#define NV857B_FREE                                                             (0x00000008)
-#define NV857B_FREE_COUNT                                                       5:0
-#define NV857B_UPDATE                                                           (0x00000080)
-#define NV857B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV857B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV857B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV857B_SET_POINT_OUT                                                    (0x00000084)
-#define NV857B_SET_POINT_OUT_X                                                  15:0
-#define NV857B_SET_POINT_OUT_Y                                                  31:16
-#define NV857B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
-#define NV857B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl857b_h
-
diff --git a/Display-Class-Methods/cl857c.h b/Display-Class-Methods/cl857c.h
deleted file mode 100644
index bfb610c..0000000
--- a/Display-Class-Methods/cl857c.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl857c_h_
-#define _cl857c_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV857C_BASE_CHANNEL_DMA                                                 (0x0000857C)
-
-#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
-#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
-#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
-
-
-// dma opcode instructions
-#define NV857C_DMA                                                                              0x00000000 
-#define NV857C_DMA_OPCODE                                                                            31:29 
-#define NV857C_DMA_OPCODE_METHOD                                                                0x00000000 
-#define NV857C_DMA_OPCODE_JUMP                                                                  0x00000001 
-#define NV857C_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
-#define NV857C_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
-#define NV857C_DMA_OPCODE                                                                            31:29 
-#define NV857C_DMA_OPCODE_METHOD                                                                0x00000000 
-#define NV857C_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
-#define NV857C_DMA_METHOD_COUNT                                                                      27:18 
-#define NV857C_DMA_METHOD_OFFSET                                                                      11:2 
-#define NV857C_DMA_DATA                                                                               31:0 
-#define NV857C_DMA_DATA_NOP                                                                     0x00000000 
-#define NV857C_DMA_OPCODE                                                                            31:29 
-#define NV857C_DMA_OPCODE_JUMP                                                                  0x00000001 
-#define NV857C_DMA_JUMP_OFFSET                                                                        11:2 
-#define NV857C_DMA_OPCODE                                                                            31:29 
-#define NV857C_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
-#define NV857C_DMA_SET_SUBDEVICE_MASK_VALUE                                                           11:0 
-
-// class methods
-#define NV857C_PUT                                                              (0x00000000)
-#define NV857C_PUT_PTR                                                          11:2
-#define NV857C_GET                                                              (0x00000004)
-#define NV857C_GET_PTR                                                          11:2
-#define NV857C_GET_SCANLINE                                                     (0x00000010)
-#define NV857C_GET_SCANLINE_LINE                                                15:0
-#define NV857C_UPDATE                                                           (0x00000080)
-#define NV857C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV857C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV857C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV857C_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
-#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
-#define NV857C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV857C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
-#define NV857C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
-#define NV857C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
-#define NV857C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV857C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
-#define NV857C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
-#define NV857C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
-#define NV857C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
-#define NV857C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV857C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
-#define NV857C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV857C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV857C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV857C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV857C_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV857C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV857C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV857C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV857C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
-#define NV857C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
-#define NV857C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
-#define NV857C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV857C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV857C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
-#define NV857C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
-#define NV857C_SET_BASE_LUT_LO                                                  (0x000000E0)
-#define NV857C_SET_BASE_LUT_LO_ENABLE                                           31:30
-#define NV857C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
-#define NV857C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
-#define NV857C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
-#define NV857C_SET_BASE_LUT_LO_MODE                                             29:29
-#define NV857C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
-#define NV857C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
-#define NV857C_SET_BASE_LUT_LO_ORIGIN                                           7:2
-#define NV857C_SET_BASE_LUT_HI                                                  (0x000000E4)
-#define NV857C_SET_BASE_LUT_HI_ORIGIN                                           31:0
-#define NV857C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
-#define NV857C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
-#define NV857C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
-#define NV857C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
-#define NV857C_SET_OUTPUT_LUT_LO_MODE                                           30:30
-#define NV857C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
-#define NV857C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
-#define NV857C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
-#define NV857C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
-#define NV857C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
-#define NV857C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
-#define NV857C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV857C_SET_PROCESSING                                                   (0x00000110)
-#define NV857C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV857C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV857C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV857C_SET_CONVERSION                                                   (0x00000114)
-#define NV857C_SET_CONVERSION_GAIN                                              15:0
-#define NV857C_SET_CONVERSION_OFS                                               31:16
-#define NV857C_SET_SPARE                                                        (0x000007BC)
-#define NV857C_SET_SPARE_UNUSED                                                 31:0
-#define NV857C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV857C_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV857C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
-#define NV857C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV857C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
-#define NV857C_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV857C_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV857C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
-#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV857C_SURFACE_SET_STORAGE_PITCH                                        19:8
-#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV857C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
-#define NV857C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
-#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
-#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
-#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X8_AA                            (0x00000003)
-#define NV857C_SURFACE_SET_PARAMS_GAMMA                                         2:2
-#define NV857C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
-#define NV857C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
-#define NV857C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
-#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
-#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
-#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
-#define NV857C_SURFACE_SET_PARAMS_RESERVED0                                     22:16
-#define NV857C_SURFACE_SET_PARAMS_RESERVED1                                     24:24
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl857c_h
-
diff --git a/Display-Class-Methods/cl857d.h b/Display-Class-Methods/cl857d.h
deleted file mode 100644
index 13ef79f..0000000
--- a/Display-Class-Methods/cl857d.h
+++ /dev/null
@@ -1,1121 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl857d_h_
-#define _cl857d_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV857D_CORE_CHANNEL_DMA                                                 (0x0000857D)
-
-#define NV857D_CORE_NOTIFIER_2                                                      0x00000000
-#define NV857D_CORE_NOTIFIER_2_SIZEOF                                               0x00000124
-#define NV857D_CORE_NOTIFIER_2_COMPLETION_0                                         0x00000000
-#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE                                    0:0
-#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_R0                                      15:1
-#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_TIMESTAMP                               29:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1                                       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE                                  0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_FALSE                            0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_TRUE                             0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO                         1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED              3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_FALSE        0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_TRUE         0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA                        22:22
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2                                       0x00000002
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED                    0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_FALSE              0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_TRUE               0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY                      1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_FALSE                0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_TRUE                 0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_R2                                    31:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3                                       0x00000003
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3_R3                                    31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4                                       0x00000004
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4_R4                                    31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5                                       0x00000005
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5_R5                                    31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6                                       0x00000006
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6_R6                                    31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7                                       0x00000007
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7_R7                                    31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8                                       0x00000008
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8_R8                                    31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9                              0x00000009
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE                   0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE                    1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_FALSE              0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_TRUE               0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_R0                           31:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10                             0x0000000A
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11                             0x0000000B
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE                  0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_FALSE            0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_TRUE             0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE                   1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE                3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_FALSE          0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_TRUE           0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_R0                          31:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12                             0x0000000C
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13                             0x0000000D
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE                  0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_FALSE            0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_TRUE             0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE                   1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE                3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_FALSE          0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_TRUE           0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_R0                          31:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14                             0x0000000E
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15                             0x0000000F
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE                  0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_FALSE            0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_TRUE             0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE                   1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE                3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_FALSE          0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_TRUE           0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_R0                          31:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16                             0x00000010
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17                             0x00000011
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18                             0x00000012
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19                             0x00000013
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20                             0x00000014
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21                             0x00000015
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22                             0x00000016
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23                             0x00000017
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24                             0x00000018
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25                             0x00000019
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26                             0x0000001A
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27                             0x0000001B
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28                             0x0000001C
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29                             0x0000001D
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30                             0x0000001E
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31                             0x0000001F
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24               1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18                 2:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24                 3:3
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A               4:4
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B               5:5
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS            6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS                   7:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_FALSE             0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_TRUE              0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI                         9:9
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_FALSE                   0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_TRUE                    0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A                        10:10
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B                        11:11
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_FALSE                  0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_TRUE                   0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ           12:12
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_FALSE     0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_TRUE      0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_R0                          31:14
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32                             0x00000020
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32_R1                          31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33                            0x00000021
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC                 1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_R0                         31:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34                            0x00000022
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34_R1                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35                            0x00000023
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC                 1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_R0                         31:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36                            0x00000024
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36_R1                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37                            0x00000025
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC                 1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_R0                         31:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38                            0x00000026
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38_R1                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39                            0x00000027
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC               0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC                 1:1
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_FALSE           0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_TRUE            0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_R0                         31:7
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40                            0x00000028
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40_R1                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41                            0x00000029
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE                     0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_FALSE               0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_TRUE                0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_R0                         31:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42                            0x0000002A
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R1                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R2                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43                            0x0000002B
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R3                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R4                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44                            0x0000002C
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R5                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R6                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45                            0x0000002D
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45_R7                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46                            0x0000002E
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46_R8                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47                            0x0000002F
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47_R9                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48                            0x00000030
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48_R10                        31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49                            0x00000031
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE                     0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_FALSE               0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_TRUE                0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_R0                         31:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50                            0x00000032
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R1                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R2                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51                            0x00000033
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R3                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R4                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52                            0x00000034
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R5                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R6                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53                            0x00000035
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53_R7                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54                            0x00000036
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54_R8                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55                            0x00000037
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55_R9                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56                            0x00000038
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56_R10                        31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57                            0x00000039
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE                     0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_FALSE               0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_TRUE                0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_R0                         31:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58                            0x0000003A
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R1                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R2                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59                            0x0000003B
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R3                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R4                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60                            0x0000003C
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R5                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R6                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61                            0x0000003D
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61_R7                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62                            0x0000003E
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62_R8                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63                            0x0000003F
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63_R9                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64                            0x00000040
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64_R10                        31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65                            0x00000041
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE                     0:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_FALSE               0x00000000
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_TRUE                0x00000001
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_R0                         31:2
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66                            0x00000042
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R1                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R2                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67                            0x00000043
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R3                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R4                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68                            0x00000044
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP444          14:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R5                         15:15
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP422          30:16
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R6                         31:31
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69                            0x00000045
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69_R7                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70                            0x00000046
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70_R8                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71                            0x00000047
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71_R9                         31:0
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72                            0x00000048
-#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72_R10                        31:0
-
-
-// dma opcode instructions
-#define NV857D_DMA                                                                              0x00000000 
-#define NV857D_DMA_OPCODE                                                                            31:29 
-#define NV857D_DMA_OPCODE_METHOD                                                                0x00000000 
-#define NV857D_DMA_OPCODE_JUMP                                                                  0x00000001 
-#define NV857D_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
-#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
-#define NV857D_DMA_OPCODE                                                                            31:29 
-#define NV857D_DMA_OPCODE_METHOD                                                                0x00000000 
-#define NV857D_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
-#define NV857D_DMA_METHOD_COUNT                                                                      27:18 
-#define NV857D_DMA_METHOD_OFFSET                                                                      11:2 
-#define NV857D_DMA_DATA                                                                               31:0 
-#define NV857D_DMA_DATA_NOP                                                                     0x00000000 
-#define NV857D_DMA_OPCODE                                                                            31:29 
-#define NV857D_DMA_OPCODE_JUMP                                                                  0x00000001 
-#define NV857D_DMA_JUMP_OFFSET                                                                        11:2 
-#define NV857D_DMA_OPCODE                                                                            31:29 
-#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
-#define NV857D_DMA_SET_SUBDEVICE_MASK_VALUE                                                           11:0 
-
-// class methods
-#define NV857D_PUT                                                              (0x00000000)
-#define NV857D_PUT_PTR                                                          11:2
-#define NV857D_GET                                                              (0x00000004)
-#define NV857D_GET_PTR                                                          11:2
-#define NV857D_UPDATE                                                           (0x00000080)
-#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
-#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV857D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV857D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
-#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV857D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV857D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV857D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV857D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV857D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV857D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV857D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV857D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV857D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV857D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV857D_SET_SPARE                                                        (0x000003BC)
-#define NV857D_SET_SPARE_UNUSED                                                 31:0
-#define NV857D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV857D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV857D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
-#define NV857D_DAC_SET_CONTROL_OWNER                                            3:0
-#define NV857D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV857D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV857D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV857D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV857D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV857D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL                                         13:8
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
-#define NV857D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
-#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
-#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
-#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
-#define NV857D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
-#define NV857D_DAC_SET_POLARITY_HSYNC                                           0:0
-#define NV857D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV857D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV857D_DAC_SET_POLARITY_VSYNC                                           1:1
-#define NV857D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV857D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV857D_DAC_SET_POLARITY_RESERVED                                        31:2
-#define NV857D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
-#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
-#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
-#define NV857D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
-#define NV857D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
-#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
-
-#define NV857D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
-#define NV857D_SOR_SET_CONTROL_OWNER                                            3:0
-#define NV857D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV857D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV857D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV857D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV857D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV857D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV857D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
-#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
-#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
-#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
-
-#define NV857D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
-#define NV857D_PIOR_SET_CONTROL_OWNER                                           3:0
-#define NV857D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
-#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
-#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
-#define NV857D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
-#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
-#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
-#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
-#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
-#define NV857D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
-#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
-#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH                                     19:16
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                             (0x00000000)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                          (0x00000001)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                          (0x00000002)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                          (0x00000003)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                          (0x00000004)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                          (0x00000005)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                          (0x00000006)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                          (0x00000007)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                          (0x00000008)
-#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                          (0x00000009)
-
-#define NV857D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
-#define NV857D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV857D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV857D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
-#define NV857D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
-#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
-#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
-#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
-#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
-#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
-#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
-#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
-#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
-#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
-#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
-#define NV857D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
-#define NV857D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
-#define NV857D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV857D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
-#define NV857D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV857D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV857D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV857D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
-#define NV857D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV857D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV857D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
-#define NV857D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV857D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV857D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
-#define NV857D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV857D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV857D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
-#define NV857D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV857D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV857D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
-#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
-#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
-#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
-#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV857D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
-#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV857D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
-#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV857D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
-#define NV857D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
-#define NV857D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
-#define NV857D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
-#define NV857D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV857D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
-#define NV857D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV857D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
-#define NV857D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV857D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
-#define NV857D_HEAD_SET_SIZE_WIDTH                                              14:0
-#define NV857D_HEAD_SET_SIZE_HEIGHT                                             30:16
-#define NV857D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
-#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV857D_HEAD_SET_STORAGE_PITCH                                           19:8
-#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
-#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV857D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
-#define NV857D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV857D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV857D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X8_AA                               (0x00000003)
-#define NV857D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV857D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV857D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV857D_HEAD_SET_PARAMS_RESERVED0                                        22:16
-#define NV857D_HEAD_SET_PARAMS_RESERVED1                                        24:24
-#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
-#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV857D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
-#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
-#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
-#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
-#define NV857D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
-#define NV857D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
-#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
-#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
-#define NV857D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
-#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV857D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV857D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV857D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV857D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
-#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV857D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV857D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV857D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
-#define NV857D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
-#define NV857D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
-#define NV857D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
-#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV857D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
-#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X8_AA            (0x00000003)
-#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
-#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV857D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
-#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV857D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
-#define NV857D_HEAD_SET_CONVERSION_GAIN                                         15:0
-#define NV857D_HEAD_SET_CONVERSION_OFS                                          31:16
-#define NV857D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
-#define NV857D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV857D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV857D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl857d_h
-
diff --git a/Display-Class-Methods/cl857e.h b/Display-Class-Methods/cl857e.h
deleted file mode 100644
index 045a134..0000000
--- a/Display-Class-Methods/cl857e.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl857e_h_
-#define _cl857e_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV857E_OVERLAY_CHANNEL_DMA                                              (0x0000857E)
-
-#define NV_DISP_NOTIFICATION_1                                                       0x00000000
-#define NV_DISP_NOTIFICATION_1_SIZEOF                                                0x00000010
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0                                          0x00000000
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0                             31:0
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1                                          0x00000001
-#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1                             31:0
-#define NV_DISP_NOTIFICATION_1__2                                                    0x00000002
-#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP                                    31:0
-#define NV_DISP_NOTIFICATION_1__3                                                    0x00000003
-#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT                                      7:0
-#define NV_DISP_NOTIFICATION_1__3_R0                                                 15:8
-#define NV_DISP_NOTIFICATION_1__3_STATUS                                             31:16
-#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN                                   0x00008000
-#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN                                       0x0000FFFF
-#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED                                    0x00000000
-
-
-#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
-#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
-#define NV_DISP_NOTIFICATION_INFO16__0_R0                                            15:8
-
-
-#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
-#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
-
-
-// dma opcode instructions
-#define NV857E_DMA                                                                              0x00000000 
-#define NV857E_DMA_OPCODE                                                                            31:29 
-#define NV857E_DMA_OPCODE_METHOD                                                                0x00000000 
-#define NV857E_DMA_OPCODE_JUMP                                                                  0x00000001 
-#define NV857E_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
-#define NV857E_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
-#define NV857E_DMA_OPCODE                                                                            31:29 
-#define NV857E_DMA_OPCODE_METHOD                                                                0x00000000 
-#define NV857E_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
-#define NV857E_DMA_METHOD_COUNT                                                                      27:18 
-#define NV857E_DMA_METHOD_OFFSET                                                                      11:2 
-#define NV857E_DMA_DATA                                                                               31:0 
-#define NV857E_DMA_DATA_NOP                                                                     0x00000000 
-#define NV857E_DMA_OPCODE                                                                            31:29 
-#define NV857E_DMA_OPCODE_JUMP                                                                  0x00000001 
-#define NV857E_DMA_JUMP_OFFSET                                                                        11:2 
-#define NV857E_DMA_OPCODE                                                                            31:29 
-#define NV857E_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
-#define NV857E_DMA_SET_SUBDEVICE_MASK_VALUE                                                           11:0 
-
-// class methods
-#define NV857E_PUT                                                              (0x00000000)
-#define NV857E_PUT_PTR                                                          11:2
-#define NV857E_GET                                                              (0x00000004)
-#define NV857E_GET_PTR                                                          11:2
-#define NV857E_UPDATE                                                           (0x00000080)
-#define NV857E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV857E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV857E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV857E_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
-#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
-#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
-#define NV857E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV857E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
-#define NV857E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV857E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
-#define NV857E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV857E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
-#define NV857E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV857E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV857E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV857E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV857E_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV857E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV857E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV857E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV857E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV857E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV857E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
-#define NV857E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV857E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
-#define NV857E_SET_OVERLAY_LUT_LO_ENABLE                                        30:30
-#define NV857E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
-#define NV857E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
-#define NV857E_SET_OVERLAY_LUT_LO_MODE                                          29:29
-#define NV857E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
-#define NV857E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
-#define NV857E_SET_OVERLAY_LUT_LO_ORIGIN                                        7:2
-#define NV857E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
-#define NV857E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
-#define NV857E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
-#define NV857E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
-#define NV857E_SET_POINT_IN                                                     (0x000000E0)
-#define NV857E_SET_POINT_IN_X                                                   14:0
-#define NV857E_SET_POINT_IN_Y                                                   30:16
-#define NV857E_SET_SIZE_IN                                                      (0x000000E4)
-#define NV857E_SET_SIZE_IN_WIDTH                                                14:0
-#define NV857E_SET_SIZE_IN_HEIGHT                                               30:16
-#define NV857E_SET_SIZE_OUT                                                     (0x000000E8)
-#define NV857E_SET_SIZE_OUT_WIDTH                                               14:0
-#define NV857E_SET_COMPOSITION_CONTROL                                          (0x00000100)
-#define NV857E_SET_COMPOSITION_CONTROL_MODE                                     3:0
-#define NV857E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
-#define NV857E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
-#define NV857E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
-#define NV857E_SET_KEY_COLOR                                                    (0x00000104)
-#define NV857E_SET_KEY_COLOR_COLOR                                              31:0
-#define NV857E_SET_KEY_MASK                                                     (0x00000108)
-#define NV857E_SET_KEY_MASK_MASK                                                31:0
-#define NV857E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV857E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV857E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV857E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV857E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV857E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV857E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV857E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV857E_SET_SPARE                                                        (0x000007BC)
-#define NV857E_SET_SPARE_UNUSED                                                 31:0
-#define NV857E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
-#define NV857E_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV857E_SURFACE_SET_OFFSET                                               (0x00000800)
-#define NV857E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV857E_SURFACE_SET_SIZE                                                 (0x00000808)
-#define NV857E_SURFACE_SET_SIZE_WIDTH                                           14:0
-#define NV857E_SURFACE_SET_SIZE_HEIGHT                                          30:16
-#define NV857E_SURFACE_SET_STORAGE                                              (0x0000080C)
-#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV857E_SURFACE_SET_STORAGE_PITCH                                        19:8
-#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
-#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV857E_SURFACE_SET_PARAMS                                               (0x00000810)
-#define NV857E_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV857E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
-#define NV857E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
-#define NV857E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV857E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV857E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
-#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
-#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
-#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
-#define NV857E_SURFACE_SET_PARAMS_RESERVED0                                     22:16
-#define NV857E_SURFACE_SET_PARAMS_RESERVED1                                     24:24
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl857e_h
-
diff --git a/Display-Class-Methods/cl887d.h b/Display-Class-Methods/cl887d.h
deleted file mode 100644
index fde2a4a..0000000
--- a/Display-Class-Methods/cl887d.h
+++ /dev/null
@@ -1,1078 +0,0 @@
-/* 
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl887d_h_
-#define _cl887d_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV887D_CORE_CHANNEL_DMA                                                 (0x0000887D)
-
-#define NV887D_CORE_NOTIFIER_2                                                      0x00000000
-#define NV887D_CORE_NOTIFIER_2_SIZEOF                                               0x00000124
-#define NV887D_CORE_NOTIFIER_2_COMPLETION_0                                         0x00000000
-#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE                                    0:0
-#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_R0                                      15:1
-#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_TIMESTAMP                               29:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1                                       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE                                  0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_FALSE                            0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_TRUE                             0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO                         1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_R0                                    3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_R1                                    31:22
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_2                                       0x00000002
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_2_R2                                    31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_3                                       0x00000003
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_3_R3                                    31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_4                                       0x00000004
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_4_R4                                    31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_5                                       0x00000005
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_5_R5                                    31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_6                                       0x00000006
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_6_R6                                    31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_7                                       0x00000007
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_7_R7                                    31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_8                                       0x00000008
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_8_R8                                    31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9                              0x00000009
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE                   0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE                    1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_FALSE              0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_TRUE               0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_R0                           31:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10                             0x0000000A
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11                             0x0000000B
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE                  0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_FALSE            0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_TRUE             0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE                   1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE                3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_FALSE          0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_TRUE           0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_R0                          31:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12                             0x0000000C
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13                             0x0000000D
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE                  0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_FALSE            0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_TRUE             0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE                   1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE                3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_FALSE          0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_TRUE           0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_R0                          31:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14                             0x0000000E
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15                             0x0000000F
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE                  0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_FALSE            0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_TRUE             0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE                   1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE                3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_FALSE          0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_TRUE           0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_R0                          31:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16                             0x00000010
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17                             0x00000011
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18                             0x00000012
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19                             0x00000013
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20                             0x00000014
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21                             0x00000015
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22                             0x00000016
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23                             0x00000017
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24                             0x00000018
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25                             0x00000019
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26                             0x0000001A
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27                             0x0000001B
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28                             0x0000001C
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29                             0x0000001D
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30                             0x0000001E
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31                             0x0000001F
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24               1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18                 2:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24                 3:3
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A               4:4
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B               5:5
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS            6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_FALSE      0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_TRUE       0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS                   7:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_FALSE             0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_TRUE              0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI                         9:9
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_FALSE                   0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_TRUE                    0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A                        10:10
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B                        11:11
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_FALSE                  0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_TRUE                   0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_R0                          31:12
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32                             0x00000020
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32_R1                          31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33                            0x00000021
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC                 1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_R0                         31:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34                            0x00000022
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34_R1                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35                            0x00000023
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC                 1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_R0                         31:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36                            0x00000024
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36_R1                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37                            0x00000025
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC                 1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_R0                         31:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38                            0x00000026
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38_R1                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39                            0x00000027
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC               0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC                 1:1
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_FALSE           0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_TRUE            0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_R0                         31:7
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40                            0x00000028
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40_R1                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41                            0x00000029
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE                     0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_FALSE               0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_TRUE                0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_R0                         31:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42                            0x0000002A
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R1                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R2                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43                            0x0000002B
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R3                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R4                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44                            0x0000002C
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R5                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R6                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45                            0x0000002D
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45_R7                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46                            0x0000002E
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46_R8                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47                            0x0000002F
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47_R9                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48                            0x00000030
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48_R10                        31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49                            0x00000031
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE                     0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_FALSE               0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_TRUE                0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_R0                         31:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50                            0x00000032
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R1                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R2                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51                            0x00000033
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R3                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R4                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52                            0x00000034
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R5                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R6                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53                            0x00000035
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53_R7                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54                            0x00000036
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54_R8                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55                            0x00000037
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55_R9                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56                            0x00000038
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56_R10                        31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57                            0x00000039
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE                     0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_FALSE               0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_TRUE                0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_R0                         31:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58                            0x0000003A
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R1                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R2                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59                            0x0000003B
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R3                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R4                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60                            0x0000003C
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R5                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R6                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61                            0x0000003D
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61_R7                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62                            0x0000003E
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62_R8                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63                            0x0000003F
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63_R9                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64                            0x00000040
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64_R10                        31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65                            0x00000041
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE                     0:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_FALSE               0x00000000
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_TRUE                0x00000001
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_R0                         31:2
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66                            0x00000042
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R1                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R2                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67                            0x00000043
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R3                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R4                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68                            0x00000044
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP444          14:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R5                         15:15
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP422          30:16
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R6                         31:31
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69                            0x00000045
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69_R7                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70                            0x00000046
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70_R8                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71                            0x00000047
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71_R9                         31:0
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72                            0x00000048
-#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72_R10                        31:0
-
-
-// dma opcode instructions
-#define NV887D_DMA                                                         0x00000000 
-#define NV887D_DMA_OPCODE                                                       31:29 
-#define NV887D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV887D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV887D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV887D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV887D_DMA_OPCODE                                                       31:29 
-#define NV887D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV887D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV887D_DMA_METHOD_COUNT                                                 27:18 
-#define NV887D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV887D_DMA_DATA                                                          31:0 
-#define NV887D_DMA_NOP                                                     0x00000000 
-#define NV887D_DMA_OPCODE                                                       31:29 
-#define NV887D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV887D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV887D_DMA_OPCODE                                                       31:29 
-#define NV887D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV887D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV887D_PUT                                                              (0x00000000)
-#define NV887D_PUT_PTR                                                          11:2
-#define NV887D_GET                                                              (0x00000004)
-#define NV887D_GET_PTR                                                          11:2
-#define NV887D_UPDATE                                                           (0x00000080)
-#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
-#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV887D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV887D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV887D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
-#define NV887D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV887D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV887D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV887D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV887D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV887D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV887D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV887D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV887D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV887D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV887D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV887D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV887D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV887D_SET_SPARE                                                        (0x000003BC)
-#define NV887D_SET_SPARE_UNUSED                                                 31:0
-#define NV887D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV887D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV887D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
-#define NV887D_DAC_SET_CONTROL_OWNER                                            3:0
-#define NV887D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV887D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV887D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV887D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV887D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV887D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV887D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV887D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL                                         13:8
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
-#define NV887D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
-#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
-#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
-#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
-#define NV887D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
-#define NV887D_DAC_SET_POLARITY_HSYNC                                           0:0
-#define NV887D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV887D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV887D_DAC_SET_POLARITY_VSYNC                                           1:1
-#define NV887D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
-#define NV887D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
-#define NV887D_DAC_SET_POLARITY_RESERVED                                        31:2
-#define NV887D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
-#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
-#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
-#define NV887D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
-#define NV887D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
-#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
-
-#define NV887D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
-#define NV887D_SOR_SET_CONTROL_OWNER                                            3:0
-#define NV887D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
-#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
-#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
-#define NV887D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
-#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
-#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
-#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
-#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
-#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
-#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
-#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
-#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
-#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
-
-#define NV887D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
-#define NV887D_PIOR_SET_CONTROL_OWNER                                           3:0
-#define NV887D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
-#define NV887D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
-#define NV887D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
-#define NV887D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
-#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
-#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
-#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
-#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
-#define NV887D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV887D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV887D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
-#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
-#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
-#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
-#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH                                     19:16
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                             (0x00000000)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                          (0x00000001)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                          (0x00000002)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                          (0x00000003)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                          (0x00000004)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                          (0x00000005)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                          (0x00000006)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                          (0x00000007)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                          (0x00000008)
-#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                          (0x00000009)
-
-#define NV887D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
-#define NV887D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV887D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV887D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
-#define NV887D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
-#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
-#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
-#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
-#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
-#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
-#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
-#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
-#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
-#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
-#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
-#define NV887D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
-#define NV887D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
-#define NV887D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV887D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
-#define NV887D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV887D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV887D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV887D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
-#define NV887D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV887D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV887D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
-#define NV887D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV887D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV887D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
-#define NV887D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV887D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV887D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
-#define NV887D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV887D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV887D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
-#define NV887D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV887D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV887D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
-#define NV887D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
-#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
-#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV887D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
-#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV887D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
-#define NV887D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV887D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV887D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
-#define NV887D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
-#define NV887D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
-#define NV887D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
-#define NV887D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV887D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
-#define NV887D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV887D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
-#define NV887D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV887D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
-#define NV887D_HEAD_SET_SIZE_WIDTH                                              14:0
-#define NV887D_HEAD_SET_SIZE_HEIGHT                                             30:16
-#define NV887D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
-#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV887D_HEAD_SET_STORAGE_PITCH                                           17:8
-#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
-#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV887D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
-#define NV887D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV887D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV887D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV887D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV887D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV887D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV887D_HEAD_SET_PARAMS_RESERVED0                                        22:16
-#define NV887D_HEAD_SET_PARAMS_RESERVED1                                        24:24
-#define NV887D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
-#define NV887D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV887D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
-#define NV887D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
-#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
-#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
-#define NV887D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
-#define NV887D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
-#define NV887D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
-#define NV887D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
-#define NV887D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
-#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV887D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV887D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV887D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV887D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV887D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV887D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
-#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV887D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV887D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV887D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
-#define NV887D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
-#define NV887D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
-#define NV887D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
-#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV887D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV887D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV887D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
-#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
-#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV887D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
-#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV887D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
-#define NV887D_HEAD_SET_CONVERSION_GAIN                                         15:0
-#define NV887D_HEAD_SET_CONVERSION_OFS                                          31:16
-#define NV887D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
-#define NV887D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV887D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
-#define NV887D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl887d_h
-
diff --git a/Display-Class-Methods/cl907a.h b/Display-Class-Methods/cl907a.h
deleted file mode 100644
index c1a23c0..0000000
--- a/Display-Class-Methods/cl907a.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl907a_h_
-#define _cl907a_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV907A_CURSOR_CHANNEL_PIO                                               (0x0000907A)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
-    NvV32 Reserved02[0x3DE];
-} GF110DispCursorControlPio;
-
-#define NV907A_FREE                                                             (0x00000008)
-#define NV907A_FREE_COUNT                                                       5:0
-#define NV907A_UPDATE                                                           (0x00000080)
-#define NV907A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV907A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV907A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
-#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
-#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl907a_h
-
diff --git a/Display-Class-Methods/cl907b.h b/Display-Class-Methods/cl907b.h
deleted file mode 100644
index 7450c59..0000000
--- a/Display-Class-Methods/cl907b.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl907b_h_
-#define _cl907b_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV907B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000907B)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
-    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
-    NvV32 Reserved02[0x3DD];
-} GF110DispOverlayImmControlPio;
-
-#define NV907B_FREE                                                             (0x00000008)
-#define NV907B_FREE_COUNT                                                       5:0
-#define NV907B_UPDATE                                                           (0x00000080)
-#define NV907B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV907B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV907B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV907B_SET_POINT_OUT                                                    (0x00000084)
-#define NV907B_SET_POINT_OUT_X                                                  15:0
-#define NV907B_SET_POINT_OUT_Y                                                  31:16
-#define NV907B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
-#define NV907B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl907b_h
-
diff --git a/Display-Class-Methods/cl907c.h b/Display-Class-Methods/cl907c.h
deleted file mode 100644
index 9f280db..0000000
--- a/Display-Class-Methods/cl907c.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl907c_h_
-#define _cl907c_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV907C_BASE_CHANNEL_DMA                                                 (0x0000907C)
-
-#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
-#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
-#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
-
-
-// dma opcode instructions
-#define NV907C_DMA                                                         0x00000000 
-#define NV907C_DMA_OPCODE                                                       31:29 
-#define NV907C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV907C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV907C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV907C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV907C_DMA_OPCODE                                                       31:29 
-#define NV907C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV907C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV907C_DMA_METHOD_COUNT                                                 27:18 
-#define NV907C_DMA_METHOD_OFFSET                                                 11:2 
-#define NV907C_DMA_DATA                                                          31:0 
-#define NV907C_DMA_DATA_NOP                                                0x00000000 
-#define NV907C_DMA_OPCODE                                                       31:29 
-#define NV907C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV907C_DMA_JUMP_OFFSET                                                   11:2 
-#define NV907C_DMA_OPCODE                                                       31:29 
-#define NV907C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV907C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV907C_PUT                                                              (0x00000000)
-#define NV907C_PUT_PTR                                                          11:2
-#define NV907C_GET                                                              (0x00000004)
-#define NV907C_GET_PTR                                                          11:2
-#define NV907C_GET_SCANLINE                                                     (0x00000010)
-#define NV907C_GET_SCANLINE_LINE                                                15:0
-#define NV907C_UPDATE                                                           (0x00000080)
-#define NV907C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV907C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV907C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV907C_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV907C_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV907C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV907C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV907C_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV907C_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
-#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
-#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_AT_FRAME                          (0x00000003)
-#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               2:2
-#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
-#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
-#define NV907C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV907C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
-#define NV907C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
-#define NV907C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
-#define NV907C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV907C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
-#define NV907C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
-#define NV907C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
-#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
-#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
-#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
-#define NV907C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
-#define NV907C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV907C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
-#define NV907C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV907C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV907C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV907C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV907C_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV907C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV907C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV907C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV907C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
-#define NV907C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
-#define NV907C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
-#define NV907C_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV907C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV907C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV907C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV907C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV907C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
-#define NV907C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
-#define NV907C_SET_BASE_LUT_LO                                                  (0x000000E0)
-#define NV907C_SET_BASE_LUT_LO_ENABLE                                           31:30
-#define NV907C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
-#define NV907C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
-#define NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000002)
-#define NV907C_SET_BASE_LUT_LO_MODE                                             27:24
-#define NV907C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
-#define NV907C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
-#define NV907C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                      (0x00000003)
-#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE                (0x00000004)
-#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE               (0x00000005)
-#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE                (0x00000006)
-#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE                 (0x00000007)
-#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE                (0x00000008)
-#define NV907C_SET_BASE_LUT_HI                                                  (0x000000E4)
-#define NV907C_SET_BASE_LUT_HI_ORIGIN                                           31:0
-#define NV907C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
-#define NV907C_SET_OUTPUT_LUT_LO_ENABLE                                         31:30
-#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
-#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT                            (0x00000001)
-#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000002)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE                                           27:24
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                    (0x00000003)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE              (0x00000004)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE             (0x00000005)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE              (0x00000006)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE               (0x00000007)
-#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE              (0x00000008)
-#define NV907C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
-#define NV907C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
-#define NV907C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
-#define NV907C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV907C_SET_PROCESSING                                                   (0x00000110)
-#define NV907C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV907C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV907C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV907C_SET_CONVERSION_RED                                               (0x00000114)
-#define NV907C_SET_CONVERSION_RED_GAIN                                          15:0
-#define NV907C_SET_CONVERSION_RED_OFS                                           31:16
-#define NV907C_SET_CONVERSION_GRN                                               (0x00000118)
-#define NV907C_SET_CONVERSION_GRN_GAIN                                          15:0
-#define NV907C_SET_CONVERSION_GRN_OFS                                           31:16
-#define NV907C_SET_CONVERSION_BLU                                               (0x0000011C)
-#define NV907C_SET_CONVERSION_BLU_GAIN                                          15:0
-#define NV907C_SET_CONVERSION_BLU_OFS                                           31:16
-#define NV907C_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV907C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV907C_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV907C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV907C_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV907C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV907C_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV907C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV907C_SET_CSC_RED2RED                                                  (0x00000140)
-#define NV907C_SET_CSC_RED2RED_OWNER                                            31:31
-#define NV907C_SET_CSC_RED2RED_OWNER_CORE                                       (0x00000000)
-#define NV907C_SET_CSC_RED2RED_OWNER_BASE                                       (0x00000001)
-#define NV907C_SET_CSC_RED2RED_COEFF                                            18:0
-#define NV907C_SET_CSC_GRN2RED                                                  (0x00000144)
-#define NV907C_SET_CSC_GRN2RED_COEFF                                            18:0
-#define NV907C_SET_CSC_BLU2RED                                                  (0x00000148)
-#define NV907C_SET_CSC_BLU2RED_COEFF                                            18:0
-#define NV907C_SET_CSC_CONSTANT2RED                                             (0x0000014C)
-#define NV907C_SET_CSC_CONSTANT2RED_COEFF                                       18:0
-#define NV907C_SET_CSC_RED2GRN                                                  (0x00000150)
-#define NV907C_SET_CSC_RED2GRN_COEFF                                            18:0
-#define NV907C_SET_CSC_GRN2GRN                                                  (0x00000154)
-#define NV907C_SET_CSC_GRN2GRN_COEFF                                            18:0
-#define NV907C_SET_CSC_BLU2GRN                                                  (0x00000158)
-#define NV907C_SET_CSC_BLU2GRN_COEFF                                            18:0
-#define NV907C_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
-#define NV907C_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
-#define NV907C_SET_CSC_RED2BLU                                                  (0x00000160)
-#define NV907C_SET_CSC_RED2BLU_COEFF                                            18:0
-#define NV907C_SET_CSC_GRN2BLU                                                  (0x00000164)
-#define NV907C_SET_CSC_GRN2BLU_COEFF                                            18:0
-#define NV907C_SET_CSC_BLU2BLU                                                  (0x00000168)
-#define NV907C_SET_CSC_BLU2BLU_COEFF                                            18:0
-#define NV907C_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
-#define NV907C_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
-#define NV907C_SET_SPARE                                                        (0x000003BC)
-#define NV907C_SET_SPARE_UNUSED                                                 31:0
-#define NV907C_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV907C_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV907C_SURFACE_SET_OFFSET(a,b)                                          (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
-#define NV907C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV907C_SURFACE_SET_SIZE(a)                                              (0x00000408 + (a)*0x00000020)
-#define NV907C_SURFACE_SET_SIZE_WIDTH                                           15:0
-#define NV907C_SURFACE_SET_SIZE_HEIGHT                                          31:16
-#define NV907C_SURFACE_SET_STORAGE(a)                                           (0x0000040C + (a)*0x00000020)
-#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV907C_SURFACE_SET_STORAGE_PITCH                                        20:8
-#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
-#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV907C_SURFACE_SET_PARAMS(a)                                            (0x00000410 + (a)*0x00000020)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
-#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
-#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
-#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
-#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
-#define NV907C_SURFACE_SET_PARAMS_GAMMA                                         2:2
-#define NV907C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
-#define NV907C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
-#define NV907C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
-#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
-#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
-#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl907c_h
diff --git a/Display-Class-Methods/cl907d.h b/Display-Class-Methods/cl907d.h
deleted file mode 100644
index d2bf4ab..0000000
--- a/Display-Class-Methods/cl907d.h
+++ /dev/null
@@ -1,1140 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl907d_h_
-#define _cl907d_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV907D_CORE_CHANNEL_DMA                                                 (0x0000907D)
-
-#define NV907D_CORE_NOTIFIER_3                                                      0x00000000
-#define NV907D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
-#define NV907D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
-#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
-#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
-#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
-#define NV907D_CORE_NOTIFIER_3__1                                                   0x00000001
-#define NV907D_CORE_NOTIFIER_3__1_R1                                                31:0
-#define NV907D_CORE_NOTIFIER_3__2                                                   0x00000002
-#define NV907D_CORE_NOTIFIER_3__2_R2                                                31:0
-#define NV907D_CORE_NOTIFIER_3__3                                                   0x00000003
-#define NV907D_CORE_NOTIFIER_3__3_R3                                                31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:27
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
-#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
-
-
-// dma opcode instructions
-#define NV907D_DMA                                                         0x00000000 
-#define NV907D_DMA_OPCODE                                                       31:29 
-#define NV907D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV907D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV907D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV907D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV907D_DMA_OPCODE                                                       31:29 
-#define NV907D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV907D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV907D_DMA_METHOD_COUNT                                                 27:18 
-#define NV907D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV907D_DMA_DATA                                                          31:0 
-#define NV907D_DMA_DATA_NOP                                                0x00000000 
-#define NV907D_DMA_OPCODE                                                       31:29 
-#define NV907D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV907D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV907D_DMA_OPCODE                                                       31:29 
-#define NV907D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV907D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV907D_PUT                                                              (0x00000000)
-#define NV907D_PUT_PTR                                                          11:2
-#define NV907D_GET                                                              (0x00000004)
-#define NV907D_GET_PTR                                                          11:2
-#define NV907D_UPDATE                                                           (0x00000080)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
-#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
-#define NV907D_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV907D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV907D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV907D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV907D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV907D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV907D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV907D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV907D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV907D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV907D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV907D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV907D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV907D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV907D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV907D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV907D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV907D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV907D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV907D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV907D_SET_SPARE                                                        (0x0000016C)
-#define NV907D_SET_SPARE_UNUSED                                                 31:0
-#define NV907D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
-#define NV907D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV907D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
-#define NV907D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV907D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV907D_DAC_SET_CONTROL_PROTOCOL                                         12:8
-#define NV907D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV907D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
-#define NV907D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
-#define NV907D_DAC_SET_SW_SPARE_A_CODE                                          31:0
-#define NV907D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
-#define NV907D_DAC_SET_SW_SPARE_B_CODE                                          31:0
-#define NV907D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
-#define NV907D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV907D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
-#define NV907D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV907D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV907D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV907D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV907D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV907D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV907D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
-#define NV907D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NV907D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
-#define NV907D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-#define NV907D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
-#define NV907D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV907D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
-#define NV907D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
-#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
-#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
-#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
-#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
-#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
-#define NV907D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV907D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV907D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV907D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
-#define NV907D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
-#define NV907D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
-#define NV907D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
-#define NV907D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
-#define NV907D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
-
-#define NV907D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
-#define NV907D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV907D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
-#define NV907D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
-#define NV907D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV907D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
-#define NV907D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV907D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV907D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV907D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
-#define NV907D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV907D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV907D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
-#define NV907D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV907D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV907D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
-#define NV907D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV907D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV907D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
-#define NV907D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV907D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV907D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
-#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
-#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV907D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
-#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
-#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
-#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
-#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
-#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
-#define NV907D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
-#define NV907D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
-#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
-#define NV907D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
-#define NV907D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NV907D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV907D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
-#define NV907D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV907D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
-#define NV907D_HEAD_SET_SIZE_WIDTH                                              15:0
-#define NV907D_HEAD_SET_SIZE_HEIGHT                                             31:16
-#define NV907D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
-#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV907D_HEAD_SET_STORAGE_PITCH                                           20:8
-#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
-#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV907D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
-#define NV907D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV907D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
-#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
-#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV907D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV907D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV907D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV907D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
-#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
-#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
-#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV907D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000484 + (a)*0x00000300)
-#define NV907D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
-#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000048C + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
-#define NV907D_HEAD_SET_DITHER_CONTROL(a)                                       (0x00000490 + (a)*0x00000300)
-#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV907D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
-#define NV907D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NV907D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV907D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
-#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV907D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV907D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV907D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
-#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
-#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
-#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
-#define NV907D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
-#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV907D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
-#define NV907D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
-#define NV907D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
-#define NV907D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
-#define NV907D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
-#define NV907D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
-#define NV907D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
-#define NV907D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
-#define NV907D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NV907D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
-#define NV907D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NV907D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
-#define NV907D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NV907D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
-#define NV907D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NV907D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
-#define NV907D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NV907D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
-#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
-#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
-#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
-#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
-#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
-#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
-#define NV907D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
-#define NV907D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV907D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
-#define NV907D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl907d_h
diff --git a/Display-Class-Methods/cl907e.h b/Display-Class-Methods/cl907e.h
deleted file mode 100644
index 631fe6d..0000000
--- a/Display-Class-Methods/cl907e.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl907e_h_
-#define _cl907e_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV907E_OVERLAY_CHANNEL_DMA                                              (0x0000907E)
-
-#define NV_DISP_NOTIFICATION_2                                                       0x00000000
-#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
-#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
-#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
-#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
-#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
-#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
-#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
-#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
-#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
-
-
-#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
-#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
-#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
-#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
-
-
-#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
-#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
-
-
-// dma opcode instructions
-#define NV907E_DMA                                                         0x00000000 
-#define NV907E_DMA_OPCODE                                                       31:29 
-#define NV907E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV907E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV907E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV907E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV907E_DMA_OPCODE                                                       31:29 
-#define NV907E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV907E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV907E_DMA_METHOD_COUNT                                                 27:18 
-#define NV907E_DMA_METHOD_OFFSET                                                 11:2 
-#define NV907E_DMA_DATA                                                          31:0 
-#define NV907E_DMA_DATA_NOP                                                0x00000000 
-#define NV907E_DMA_OPCODE                                                       31:29 
-#define NV907E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV907E_DMA_JUMP_OFFSET                                                   11:2 
-#define NV907E_DMA_OPCODE                                                       31:29 
-#define NV907E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV907E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV907E_PUT                                                              (0x00000000)
-#define NV907E_PUT_PTR                                                          11:2
-#define NV907E_GET                                                              (0x00000004)
-#define NV907E_GET_PTR                                                          11:2
-#define NV907E_UPDATE                                                           (0x00000080)
-#define NV907E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV907E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV907E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV907E_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV907E_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV907E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV907E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV907E_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV907E_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
-#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
-#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
-#define NV907E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV907E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
-#define NV907E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV907E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
-#define NV907E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV907E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
-#define NV907E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
-#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
-#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
-#define NV907E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV907E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV907E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV907E_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV907E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV907E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV907E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV907E_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV907E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV907E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV907E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV907E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV907E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
-#define NV907E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV907E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
-#define NV907E_SET_OVERLAY_LUT_LO_ENABLE                                        31:31
-#define NV907E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
-#define NV907E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE                                          27:24
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                   (0x00000003)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE             (0x00000004)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE            (0x00000005)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE             (0x00000006)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE              (0x00000007)
-#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE             (0x00000008)
-#define NV907E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
-#define NV907E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
-#define NV907E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
-#define NV907E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
-#define NV907E_SET_POINT_IN                                                     (0x000000E0)
-#define NV907E_SET_POINT_IN_X                                                   14:0
-#define NV907E_SET_POINT_IN_Y                                                   30:16
-#define NV907E_SET_SIZE_IN                                                      (0x000000E4)
-#define NV907E_SET_SIZE_IN_WIDTH                                                14:0
-#define NV907E_SET_SIZE_IN_HEIGHT                                               30:16
-#define NV907E_SET_SIZE_OUT                                                     (0x000000E8)
-#define NV907E_SET_SIZE_OUT_WIDTH                                               14:0
-#define NV907E_SET_COMPOSITION_CONTROL                                          (0x00000100)
-#define NV907E_SET_COMPOSITION_CONTROL_MODE                                     3:0
-#define NV907E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
-#define NV907E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
-#define NV907E_SET_COMPOSITION_CONTROL_MODE_OPAQUE                              (0x00000002)
-#define NV907E_SET_KEY_COLOR_LO                                                 (0x00000104)
-#define NV907E_SET_KEY_COLOR_LO_COLOR                                           31:0
-#define NV907E_SET_KEY_COLOR_HI                                                 (0x00000108)
-#define NV907E_SET_KEY_COLOR_HI_COLOR                                           31:0
-#define NV907E_SET_KEY_MASK_LO                                                  (0x0000010C)
-#define NV907E_SET_KEY_MASK_LO_MASK                                             31:0
-#define NV907E_SET_KEY_MASK_HI                                                  (0x00000110)
-#define NV907E_SET_KEY_MASK_HI_MASK                                             31:0
-#define NV907E_SET_PROCESSING                                                   (0x00000118)
-#define NV907E_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV907E_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV907E_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV907E_SET_CONVERSION_RED                                               (0x0000011C)
-#define NV907E_SET_CONVERSION_RED_GAIN                                          15:0
-#define NV907E_SET_CONVERSION_RED_OFS                                           31:16
-#define NV907E_SET_CONVERSION_GRN                                               (0x00000120)
-#define NV907E_SET_CONVERSION_GRN_GAIN                                          15:0
-#define NV907E_SET_CONVERSION_GRN_OFS                                           31:16
-#define NV907E_SET_CONVERSION_BLU                                               (0x00000124)
-#define NV907E_SET_CONVERSION_BLU_GAIN                                          15:0
-#define NV907E_SET_CONVERSION_BLU_OFS                                           31:16
-#define NV907E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV907E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV907E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV907E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV907E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV907E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV907E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV907E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV907E_SET_CSC_RED2RED                                                  (0x00000140)
-#define NV907E_SET_CSC_RED2RED_COEFF                                            18:0
-#define NV907E_SET_CSC_GRN2RED                                                  (0x00000144)
-#define NV907E_SET_CSC_GRN2RED_COEFF                                            18:0
-#define NV907E_SET_CSC_BLU2RED                                                  (0x00000148)
-#define NV907E_SET_CSC_BLU2RED_COEFF                                            18:0
-#define NV907E_SET_CSC_CONSTANT2RED                                             (0x0000014C)
-#define NV907E_SET_CSC_CONSTANT2RED_COEFF                                       18:0
-#define NV907E_SET_CSC_RED2GRN                                                  (0x00000150)
-#define NV907E_SET_CSC_RED2GRN_COEFF                                            18:0
-#define NV907E_SET_CSC_GRN2GRN                                                  (0x00000154)
-#define NV907E_SET_CSC_GRN2GRN_COEFF                                            18:0
-#define NV907E_SET_CSC_BLU2GRN                                                  (0x00000158)
-#define NV907E_SET_CSC_BLU2GRN_COEFF                                            18:0
-#define NV907E_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
-#define NV907E_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
-#define NV907E_SET_CSC_RED2BLU                                                  (0x00000160)
-#define NV907E_SET_CSC_RED2BLU_COEFF                                            18:0
-#define NV907E_SET_CSC_GRN2BLU                                                  (0x00000164)
-#define NV907E_SET_CSC_GRN2BLU_COEFF                                            18:0
-#define NV907E_SET_CSC_BLU2BLU                                                  (0x00000168)
-#define NV907E_SET_CSC_BLU2BLU_COEFF                                            18:0
-#define NV907E_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
-#define NV907E_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
-#define NV907E_SET_SPARE                                                        (0x000003BC)
-#define NV907E_SET_SPARE_UNUSED                                                 31:0
-#define NV907E_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV907E_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV907E_SURFACE_SET_OFFSET                                               (0x00000400)
-#define NV907E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV907E_SURFACE_SET_SIZE                                                 (0x00000408)
-#define NV907E_SURFACE_SET_SIZE_WIDTH                                           15:0
-#define NV907E_SURFACE_SET_SIZE_HEIGHT                                          31:16
-#define NV907E_SURFACE_SET_STORAGE                                              (0x0000040C)
-#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV907E_SURFACE_SET_STORAGE_PITCH                                        20:8
-#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
-#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV907E_SURFACE_SET_PARAMS                                               (0x00000410)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
-#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
-#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
-#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
-#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
-#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl907e_h
diff --git a/Display-Class-Methods/cl917a.h b/Display-Class-Methods/cl917a.h
deleted file mode 100644
index b6d6239..0000000
--- a/Display-Class-Methods/cl917a.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl917a_h_
-#define _cl917a_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV917A_CURSOR_CHANNEL_PIO                                               (0x0000917A)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetCursorHotSpotPointsOut[2];                                         // 0x00000084 - 0x0000008B
-    NvV32 Reserved02[0x3DD];
-} GK104DispCursorControlPio;
-
-#define NV917A_FREE                                                             (0x00000008)
-#define NV917A_FREE_COUNT                                                       5:0
-#define NV917A_UPDATE                                                           (0x00000080)
-#define NV917A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV917A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV917A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT(b)                                (0x00000084 + (b)*0x00000004)
-#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_X                                 15:0
-#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_Y                                 31:16
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl917a_h
-
diff --git a/Display-Class-Methods/cl917b.h b/Display-Class-Methods/cl917b.h
deleted file mode 100644
index 05270e2..0000000
--- a/Display-Class-Methods/cl917b.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl917b_h_
-#define _cl917b_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV917B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000917B)
-
-typedef volatile struct {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x1D];
-    NvV32 Update;                                                               // 0x00000080 - 0x00000083
-    NvV32 SetPointsOut[2];                                                      // 0x00000084 - 0x0000008B
-    NvV32 Reserved02[0x1];
-    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000090 - 0x00000093
-    NvV32 Reserved03[0x3DB];
-} GK104DispOverlayImmControlPio;
-
-#define NV917B_FREE                                                             (0x00000008)
-#define NV917B_FREE_COUNT                                                       5:0
-#define NV917B_UPDATE                                                           (0x00000080)
-#define NV917B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV917B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV917B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV917B_SET_POINTS_OUT(b)                                                (0x00000084 + (b)*0x00000004)
-#define NV917B_SET_POINTS_OUT_X                                                 15:0
-#define NV917B_SET_POINTS_OUT_Y                                                 31:16
-#define NV917B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000090)
-#define NV917B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl917b_h
-
diff --git a/Display-Class-Methods/cl917c.h b/Display-Class-Methods/cl917c.h
deleted file mode 100644
index 9870f36..0000000
--- a/Display-Class-Methods/cl917c.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl917c_h_
-#define _cl917c_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV917C_BASE_CHANNEL_DMA                                                 (0x0000917C)
-
-#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
-#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
-#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
-
-
-#define NV_DISP_NOTIFICATION_2                                                       0x00000000
-#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
-#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
-#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
-#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
-#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
-#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
-#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
-#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
-#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
-
-
-#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
-#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
-#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
-#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
-
-
-#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
-#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
-
-
-// dma opcode instructions
-#define NV917C_DMA                                                         0x00000000 
-#define NV917C_DMA_OPCODE                                                       31:29 
-#define NV917C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV917C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV917C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV917C_DMA_OPCODE                                                       31:29 
-#define NV917C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV917C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV917C_DMA_METHOD_COUNT                                                 27:18 
-#define NV917C_DMA_METHOD_OFFSET                                                 11:2 
-#define NV917C_DMA_DATA                                                          31:0 
-#define NV917C_DMA_DATA_NOP                                                0x00000000 
-#define NV917C_DMA_OPCODE                                                       31:29 
-#define NV917C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV917C_DMA_JUMP_OFFSET                                                   11:2 
-#define NV917C_DMA_OPCODE                                                       31:29 
-#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV917C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV917C_PUT                                                              (0x00000000)
-#define NV917C_PUT_PTR                                                          11:2
-#define NV917C_GET                                                              (0x00000004)
-#define NV917C_GET_PTR                                                          11:2
-#define NV917C_GET_SCANLINE                                                     (0x00000010)
-#define NV917C_GET_SCANLINE_LINE                                                15:0
-#define NV917C_UPDATE                                                           (0x00000080)
-#define NV917C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV917C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV917C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV917C_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV917C_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV917C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV917C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV917C_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV917C_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
-#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
-#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               2:2
-#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
-#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
-#define NV917C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV917C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
-#define NV917C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
-#define NV917C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
-#define NV917C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV917C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
-#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
-#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
-#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
-#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
-#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
-#define NV917C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
-#define NV917C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV917C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
-#define NV917C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV917C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV917C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV917C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV917C_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV917C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV917C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
-#define NV917C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
-#define NV917C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
-#define NV917C_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV917C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV917C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV917C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
-#define NV917C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
-#define NV917C_SET_BASE_LUT_LO                                                  (0x000000E0)
-#define NV917C_SET_BASE_LUT_LO_ENABLE                                           31:30
-#define NV917C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
-#define NV917C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
-#define NV917C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000002)
-#define NV917C_SET_BASE_LUT_LO_MODE                                             27:24
-#define NV917C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
-#define NV917C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
-#define NV917C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                      (0x00000003)
-#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE                (0x00000004)
-#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE               (0x00000005)
-#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE                (0x00000006)
-#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE                 (0x00000007)
-#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE                (0x00000008)
-#define NV917C_SET_BASE_LUT_HI                                                  (0x000000E4)
-#define NV917C_SET_BASE_LUT_HI_ORIGIN                                           31:0
-#define NV917C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
-#define NV917C_SET_OUTPUT_LUT_LO_ENABLE                                         31:30
-#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
-#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT                            (0x00000001)
-#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000002)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE                                           27:24
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                    (0x00000003)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE              (0x00000004)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE             (0x00000005)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE              (0x00000006)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE               (0x00000007)
-#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE              (0x00000008)
-#define NV917C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
-#define NV917C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
-#define NV917C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
-#define NV917C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV917C_SET_PROCESSING                                                   (0x00000110)
-#define NV917C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV917C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV917C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV917C_SET_CONVERSION_RED                                               (0x00000114)
-#define NV917C_SET_CONVERSION_RED_GAIN                                          15:0
-#define NV917C_SET_CONVERSION_RED_OFS                                           31:16
-#define NV917C_SET_CONVERSION_GRN                                               (0x00000118)
-#define NV917C_SET_CONVERSION_GRN_GAIN                                          15:0
-#define NV917C_SET_CONVERSION_GRN_OFS                                           31:16
-#define NV917C_SET_CONVERSION_BLU                                               (0x0000011C)
-#define NV917C_SET_CONVERSION_BLU_GAIN                                          15:0
-#define NV917C_SET_CONVERSION_BLU_OFS                                           31:16
-#define NV917C_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV917C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV917C_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV917C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV917C_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV917C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV917C_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV917C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV917C_SET_CSC_RED2RED                                                  (0x00000140)
-#define NV917C_SET_CSC_RED2RED_OWNER                                            31:31
-#define NV917C_SET_CSC_RED2RED_OWNER_CORE                                       (0x00000000)
-#define NV917C_SET_CSC_RED2RED_OWNER_BASE                                       (0x00000001)
-#define NV917C_SET_CSC_RED2RED_COEFF                                            18:0
-#define NV917C_SET_CSC_GRN2RED                                                  (0x00000144)
-#define NV917C_SET_CSC_GRN2RED_COEFF                                            18:0
-#define NV917C_SET_CSC_BLU2RED                                                  (0x00000148)
-#define NV917C_SET_CSC_BLU2RED_COEFF                                            18:0
-#define NV917C_SET_CSC_CONSTANT2RED                                             (0x0000014C)
-#define NV917C_SET_CSC_CONSTANT2RED_COEFF                                       18:0
-#define NV917C_SET_CSC_RED2GRN                                                  (0x00000150)
-#define NV917C_SET_CSC_RED2GRN_COEFF                                            18:0
-#define NV917C_SET_CSC_GRN2GRN                                                  (0x00000154)
-#define NV917C_SET_CSC_GRN2GRN_COEFF                                            18:0
-#define NV917C_SET_CSC_BLU2GRN                                                  (0x00000158)
-#define NV917C_SET_CSC_BLU2GRN_COEFF                                            18:0
-#define NV917C_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
-#define NV917C_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
-#define NV917C_SET_CSC_RED2BLU                                                  (0x00000160)
-#define NV917C_SET_CSC_RED2BLU_COEFF                                            18:0
-#define NV917C_SET_CSC_GRN2BLU                                                  (0x00000164)
-#define NV917C_SET_CSC_GRN2BLU_COEFF                                            18:0
-#define NV917C_SET_CSC_BLU2BLU                                                  (0x00000168)
-#define NV917C_SET_CSC_BLU2BLU_COEFF                                            18:0
-#define NV917C_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
-#define NV917C_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
-#define NV917C_SET_SPARE                                                        (0x000003BC)
-#define NV917C_SET_SPARE_UNUSED                                                 31:0
-#define NV917C_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV917C_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV917C_SURFACE_SET_OFFSET(a,b)                                          (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
-#define NV917C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV917C_SURFACE_SET_SIZE(a)                                              (0x00000408 + (a)*0x00000020)
-#define NV917C_SURFACE_SET_SIZE_WIDTH                                           15:0
-#define NV917C_SURFACE_SET_SIZE_HEIGHT                                          31:16
-#define NV917C_SURFACE_SET_STORAGE(a)                                           (0x0000040C + (a)*0x00000020)
-#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV917C_SURFACE_SET_STORAGE_PITCH                                        20:8
-#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
-#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV917C_SURFACE_SET_PARAMS(a)                                            (0x00000410 + (a)*0x00000020)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
-#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10                            (0x000000DF)
-#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
-#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
-#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
-#define NV917C_SURFACE_SET_PARAMS_GAMMA                                         2:2
-#define NV917C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
-#define NV917C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
-#define NV917C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
-#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
-#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
-#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl917c_h
diff --git a/Display-Class-Methods/cl917d.h b/Display-Class-Methods/cl917d.h
deleted file mode 100644
index cf08d92..0000000
--- a/Display-Class-Methods/cl917d.h
+++ /dev/null
@@ -1,1176 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl917d_h_
-#define _cl917d_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV917D_CORE_CHANNEL_DMA                                                 (0x0000917D)
-
-#define NV917D_CORE_NOTIFIER_3                                                      0x00000000
-#define NV917D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
-#define NV917D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
-#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
-#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
-#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
-#define NV917D_CORE_NOTIFIER_3__1                                                   0x00000001
-#define NV917D_CORE_NOTIFIER_3__1_R1                                                31:0
-#define NV917D_CORE_NOTIFIER_3__2                                                   0x00000002
-#define NV917D_CORE_NOTIFIER_3__2_R2                                                31:0
-#define NV917D_CORE_NOTIFIER_3__3                                                   0x00000003
-#define NV917D_CORE_NOTIFIER_3__3_R3                                                31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:27
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
-#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
-
-
-// dma opcode instructions
-#define NV917D_DMA                                                         0x00000000 
-#define NV917D_DMA_OPCODE                                                       31:29 
-#define NV917D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV917D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV917D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV917D_DMA_OPCODE                                                       31:29 
-#define NV917D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV917D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV917D_DMA_METHOD_COUNT                                                 27:18 
-#define NV917D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV917D_DMA_DATA                                                          31:0 
-#define NV917D_DMA_DATA_NOP                                                0x00000000 
-#define NV917D_DMA_OPCODE                                                       31:29 
-#define NV917D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV917D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV917D_DMA_OPCODE                                                       31:29 
-#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV917D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV917D_PUT                                                              (0x00000000)
-#define NV917D_PUT_PTR                                                          11:2
-#define NV917D_GET                                                              (0x00000004)
-#define NV917D_GET_PTR                                                          11:2
-#define NV917D_UPDATE                                                           (0x00000080)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
-#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
-#define NV917D_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV917D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV917D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV917D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV917D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV917D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV917D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV917D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV917D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV917D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV917D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV917D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV917D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV917D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV917D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV917D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV917D_SET_SPARE                                                        (0x0000016C)
-#define NV917D_SET_SPARE_UNUSED                                                 31:0
-#define NV917D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
-#define NV917D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV917D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
-#define NV917D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV917D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV917D_DAC_SET_CONTROL_PROTOCOL                                         12:8
-#define NV917D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV917D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
-#define NV917D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
-#define NV917D_DAC_SET_SW_SPARE_A_CODE                                          31:0
-#define NV917D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
-#define NV917D_DAC_SET_SW_SPARE_B_CODE                                          31:0
-#define NV917D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
-#define NV917D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV917D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
-#define NV917D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV917D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV917D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
-#define NV917D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NV917D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
-#define NV917D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-#define NV917D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
-#define NV917D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV917D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
-#define NV917D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
-#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
-#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
-#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
-#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
-#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
-#define NV917D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV917D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
-#define NV917D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
-#define NV917D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
-#define NV917D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
-#define NV917D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
-#define NV917D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
-
-#define NV917D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
-#define NV917D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV917D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
-#define NV917D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
-#define NV917D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV917D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
-#define NV917D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV917D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV917D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV917D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
-#define NV917D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV917D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV917D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
-#define NV917D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV917D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV917D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
-#define NV917D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV917D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV917D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
-#define NV917D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV917D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV917D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
-#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
-#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV917D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
-#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
-#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
-#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
-#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
-#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
-#define NV917D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
-#define NV917D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
-#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
-#define NV917D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
-#define NV917D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NV917D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV917D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
-#define NV917D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV917D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
-#define NV917D_HEAD_SET_SIZE_WIDTH                                              15:0
-#define NV917D_HEAD_SET_SIZE_HEIGHT                                             31:16
-#define NV917D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
-#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV917D_HEAD_SET_STORAGE_PITCH                                           20:8
-#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
-#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV917D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
-#define NV917D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV917D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
-#define NV917D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
-#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV917D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV917D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV917D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV917D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
-#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
-#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
-#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV917D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
-#define NV917D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
-#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
-#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
-#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
-#define NV917D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
-#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV917D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV917D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV917D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
-#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV917D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
-#define NV917D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV917D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
-#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
-#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
-#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
-#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
-#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
-#define NV917D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
-#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV917D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
-#define NV917D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
-#define NV917D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
-#define NV917D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
-#define NV917D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
-#define NV917D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
-#define NV917D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
-#define NV917D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
-#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
-#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
-#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
-#define NV917D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
-#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
-#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
-#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
-#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
-#define NV917D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
-#define NV917D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NV917D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NV917D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NV917D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NV917D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NV917D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
-#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
-#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
-#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
-#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
-#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
-#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
-#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
-#define NV917D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
-#define NV917D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV917D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
-#define NV917D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl917d_h
diff --git a/Display-Class-Methods/cl917e.h b/Display-Class-Methods/cl917e.h
deleted file mode 100644
index ad6423c..0000000
--- a/Display-Class-Methods/cl917e.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl917e_h_
-#define _cl917e_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV917E_OVERLAY_CHANNEL_DMA                                              (0x0000917E)
-
-#define NV_DISP_NOTIFICATION_2                                                       0x00000000
-#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
-#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
-#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
-#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
-#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
-#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
-#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
-#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
-#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
-
-
-#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
-#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
-#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
-#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
-
-
-#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
-#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
-
-
-// dma opcode instructions
-#define NV917E_DMA                                                         0x00000000 
-#define NV917E_DMA_OPCODE                                                       31:29 
-#define NV917E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV917E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV917E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV917E_DMA_OPCODE                                                       31:29 
-#define NV917E_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV917E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV917E_DMA_METHOD_COUNT                                                 27:18 
-#define NV917E_DMA_METHOD_OFFSET                                                 11:2 
-#define NV917E_DMA_DATA                                                          31:0 
-#define NV917E_DMA_DATA_NOP                                                0x00000000 
-#define NV917E_DMA_OPCODE                                                       31:29 
-#define NV917E_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV917E_DMA_JUMP_OFFSET                                                   11:2 
-#define NV917E_DMA_OPCODE                                                       31:29 
-#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV917E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV917E_PUT                                                              (0x00000000)
-#define NV917E_PUT_PTR                                                          11:2
-#define NV917E_GET                                                              (0x00000004)
-#define NV917E_GET_PTR                                                          11:2
-#define NV917E_UPDATE                                                           (0x00000080)
-#define NV917E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV917E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV917E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV917E_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV917E_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV917E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV917E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV917E_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV917E_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
-#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
-#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
-#define NV917E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV917E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
-#define NV917E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV917E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
-#define NV917E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV917E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
-#define NV917E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
-#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
-#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
-#define NV917E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV917E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV917E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV917E_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV917E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV917E_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV917E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV917E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV917E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
-#define NV917E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV917E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
-#define NV917E_SET_OVERLAY_LUT_LO_ENABLE                                        31:31
-#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
-#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE                                          27:24
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                   (0x00000003)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE             (0x00000004)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE            (0x00000005)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE             (0x00000006)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE              (0x00000007)
-#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE             (0x00000008)
-#define NV917E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
-#define NV917E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
-#define NV917E_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
-#define NV917E_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
-#define NV917E_SET_POINT_IN                                                     (0x000000E0)
-#define NV917E_SET_POINT_IN_X                                                   14:0
-#define NV917E_SET_POINT_IN_Y                                                   30:16
-#define NV917E_SET_SIZE_IN                                                      (0x000000E4)
-#define NV917E_SET_SIZE_IN_WIDTH                                                14:0
-#define NV917E_SET_SIZE_IN_HEIGHT                                               30:16
-#define NV917E_SET_SIZE_OUT                                                     (0x000000E8)
-#define NV917E_SET_SIZE_OUT_WIDTH                                               14:0
-#define NV917E_SET_COMPOSITION_CONTROL                                          (0x00000100)
-#define NV917E_SET_COMPOSITION_CONTROL_MODE                                     3:0
-#define NV917E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
-#define NV917E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
-#define NV917E_SET_COMPOSITION_CONTROL_MODE_OPAQUE                              (0x00000002)
-#define NV917E_SET_KEY_COLOR_LO                                                 (0x00000104)
-#define NV917E_SET_KEY_COLOR_LO_COLOR                                           31:0
-#define NV917E_SET_KEY_COLOR_HI                                                 (0x00000108)
-#define NV917E_SET_KEY_COLOR_HI_COLOR                                           31:0
-#define NV917E_SET_KEY_MASK_LO                                                  (0x0000010C)
-#define NV917E_SET_KEY_MASK_LO_MASK                                             31:0
-#define NV917E_SET_KEY_MASK_HI                                                  (0x00000110)
-#define NV917E_SET_KEY_MASK_HI_MASK                                             31:0
-#define NV917E_SET_PROCESSING                                                   (0x00000118)
-#define NV917E_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV917E_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV917E_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV917E_SET_CONVERSION_RED                                               (0x0000011C)
-#define NV917E_SET_CONVERSION_RED_GAIN                                          15:0
-#define NV917E_SET_CONVERSION_RED_OFS                                           31:16
-#define NV917E_SET_CONVERSION_GRN                                               (0x00000120)
-#define NV917E_SET_CONVERSION_GRN_GAIN                                          15:0
-#define NV917E_SET_CONVERSION_GRN_OFS                                           31:16
-#define NV917E_SET_CONVERSION_BLU                                               (0x00000124)
-#define NV917E_SET_CONVERSION_BLU_GAIN                                          15:0
-#define NV917E_SET_CONVERSION_BLU_OFS                                           31:16
-#define NV917E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV917E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV917E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV917E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV917E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV917E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV917E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV917E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV917E_SET_CSC_RED2RED                                                  (0x00000140)
-#define NV917E_SET_CSC_RED2RED_COEFF                                            18:0
-#define NV917E_SET_CSC_GRN2RED                                                  (0x00000144)
-#define NV917E_SET_CSC_GRN2RED_COEFF                                            18:0
-#define NV917E_SET_CSC_BLU2RED                                                  (0x00000148)
-#define NV917E_SET_CSC_BLU2RED_COEFF                                            18:0
-#define NV917E_SET_CSC_CONSTANT2RED                                             (0x0000014C)
-#define NV917E_SET_CSC_CONSTANT2RED_COEFF                                       18:0
-#define NV917E_SET_CSC_RED2GRN                                                  (0x00000150)
-#define NV917E_SET_CSC_RED2GRN_COEFF                                            18:0
-#define NV917E_SET_CSC_GRN2GRN                                                  (0x00000154)
-#define NV917E_SET_CSC_GRN2GRN_COEFF                                            18:0
-#define NV917E_SET_CSC_BLU2GRN                                                  (0x00000158)
-#define NV917E_SET_CSC_BLU2GRN_COEFF                                            18:0
-#define NV917E_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
-#define NV917E_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
-#define NV917E_SET_CSC_RED2BLU                                                  (0x00000160)
-#define NV917E_SET_CSC_RED2BLU_COEFF                                            18:0
-#define NV917E_SET_CSC_GRN2BLU                                                  (0x00000164)
-#define NV917E_SET_CSC_GRN2BLU_COEFF                                            18:0
-#define NV917E_SET_CSC_BLU2BLU                                                  (0x00000168)
-#define NV917E_SET_CSC_BLU2BLU_COEFF                                            18:0
-#define NV917E_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
-#define NV917E_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
-#define NV917E_SET_SPARE                                                        (0x000003BC)
-#define NV917E_SET_SPARE_UNUSED                                                 31:0
-#define NV917E_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV917E_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV917E_SURFACE_SET_OFFSET(b)                                            (0x00000400 + (b)*0x00000004)
-#define NV917E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV917E_SURFACE_SET_SIZE                                                 (0x00000408)
-#define NV917E_SURFACE_SET_SIZE_WIDTH                                           15:0
-#define NV917E_SURFACE_SET_SIZE_HEIGHT                                          31:16
-#define NV917E_SURFACE_SET_STORAGE                                              (0x0000040C)
-#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV917E_SURFACE_SET_STORAGE_PITCH                                        20:8
-#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
-#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV917E_SURFACE_SET_PARAMS                                               (0x00000410)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
-#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10                            (0x000000DF)
-#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
-#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
-#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
-#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl917e_h
diff --git a/Display-Class-Methods/cl927c.h b/Display-Class-Methods/cl927c.h
deleted file mode 100644
index 2cd1e47..0000000
--- a/Display-Class-Methods/cl927c.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl927c_h_
-#define _cl927c_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV927C_BASE_CHANNEL_DMA                                                 (0x0000927C)
-
-#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
-#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
-#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
-#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
-#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
-
-
-#define NV_DISP_NOTIFICATION_2                                                       0x00000000
-#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
-#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
-#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
-#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
-#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
-#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
-#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
-#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
-#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
-#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
-#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
-
-
-#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
-#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
-#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
-#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
-
-
-#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
-#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
-#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
-#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
-
-
-// dma opcode instructions
-#define NV927C_DMA                                                         0x00000000 
-#define NV927C_DMA_OPCODE                                                       31:29 
-#define NV927C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV927C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV927C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV927C_DMA_OPCODE                                                       31:29 
-#define NV927C_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV927C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV927C_DMA_METHOD_COUNT                                                 27:18 
-#define NV927C_DMA_METHOD_OFFSET                                                 11:2 
-#define NV927C_DMA_DATA                                                          31:0 
-#define NV927C_DMA_DATA_NOP                                                0x00000000 
-#define NV927C_DMA_OPCODE                                                       31:29 
-#define NV927C_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV927C_DMA_JUMP_OFFSET                                                   11:2 
-#define NV927C_DMA_OPCODE                                                       31:29 
-#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV927C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV927C_PUT                                                              (0x00000000)
-#define NV927C_PUT_PTR                                                          11:2
-#define NV927C_GET                                                              (0x00000004)
-#define NV927C_GET_PTR                                                          11:2
-#define NV927C_GET_SCANLINE                                                     (0x00000010)
-#define NV927C_GET_SCANLINE_LINE                                                15:0
-#define NV927C_UPDATE                                                           (0x00000080)
-#define NV927C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
-#define NV927C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
-#define NV927C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
-#define NV927C_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV927C_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV927C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV927C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV927C_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV927C_SET_PRESENT_CONTROL                                              (0x00000084)
-#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
-#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
-#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               2:2
-#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
-#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
-#define NV927C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
-#define NV927C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
-#define NV927C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
-#define NV927C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
-#define NV927C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
-#define NV927C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
-#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
-#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
-#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
-#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
-#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
-#define NV927C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
-#define NV927C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NV927C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
-#define NV927C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NV927C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
-#define NV927C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NV927C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
-#define NV927C_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV927C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV927C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
-#define NV927C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
-#define NV927C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
-#define NV927C_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV927C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
-#define NV927C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV927C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
-#define NV927C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
-#define NV927C_SET_BASE_LUT_LO                                                  (0x000000E0)
-#define NV927C_SET_BASE_LUT_LO_ENABLE                                           31:30
-#define NV927C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
-#define NV927C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
-#define NV927C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000002)
-#define NV927C_SET_BASE_LUT_LO_MODE                                             27:24
-#define NV927C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
-#define NV927C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
-#define NV927C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                      (0x00000003)
-#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE                (0x00000004)
-#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE               (0x00000005)
-#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE                (0x00000006)
-#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE                 (0x00000007)
-#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE                (0x00000008)
-#define NV927C_SET_BASE_LUT_HI                                                  (0x000000E4)
-#define NV927C_SET_BASE_LUT_HI_ORIGIN                                           31:0
-#define NV927C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
-#define NV927C_SET_OUTPUT_LUT_LO_ENABLE                                         31:30
-#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
-#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT                            (0x00000001)
-#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000002)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE                                           27:24
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                    (0x00000003)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE              (0x00000004)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE             (0x00000005)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE              (0x00000006)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE               (0x00000007)
-#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE              (0x00000008)
-#define NV927C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
-#define NV927C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
-#define NV927C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
-#define NV927C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
-#define NV927C_SET_PROCESSING                                                   (0x00000110)
-#define NV927C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
-#define NV927C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
-#define NV927C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
-#define NV927C_SET_CONVERSION_RED                                               (0x00000114)
-#define NV927C_SET_CONVERSION_RED_GAIN                                          15:0
-#define NV927C_SET_CONVERSION_RED_OFS                                           31:16
-#define NV927C_SET_CONVERSION_GRN                                               (0x00000118)
-#define NV927C_SET_CONVERSION_GRN_GAIN                                          15:0
-#define NV927C_SET_CONVERSION_GRN_OFS                                           31:16
-#define NV927C_SET_CONVERSION_BLU                                               (0x0000011C)
-#define NV927C_SET_CONVERSION_BLU_GAIN                                          15:0
-#define NV927C_SET_CONVERSION_BLU_OFS                                           31:16
-#define NV927C_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
-#define NV927C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NV927C_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
-#define NV927C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NV927C_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
-#define NV927C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NV927C_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
-#define NV927C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NV927C_SET_CSC_RED2RED                                                  (0x00000140)
-#define NV927C_SET_CSC_RED2RED_OWNER                                            31:31
-#define NV927C_SET_CSC_RED2RED_OWNER_CORE                                       (0x00000000)
-#define NV927C_SET_CSC_RED2RED_OWNER_BASE                                       (0x00000001)
-#define NV927C_SET_CSC_RED2RED_COEFF                                            18:0
-#define NV927C_SET_CSC_GRN2RED                                                  (0x00000144)
-#define NV927C_SET_CSC_GRN2RED_COEFF                                            18:0
-#define NV927C_SET_CSC_BLU2RED                                                  (0x00000148)
-#define NV927C_SET_CSC_BLU2RED_COEFF                                            18:0
-#define NV927C_SET_CSC_CONSTANT2RED                                             (0x0000014C)
-#define NV927C_SET_CSC_CONSTANT2RED_COEFF                                       18:0
-#define NV927C_SET_CSC_RED2GRN                                                  (0x00000150)
-#define NV927C_SET_CSC_RED2GRN_COEFF                                            18:0
-#define NV927C_SET_CSC_GRN2GRN                                                  (0x00000154)
-#define NV927C_SET_CSC_GRN2GRN_COEFF                                            18:0
-#define NV927C_SET_CSC_BLU2GRN                                                  (0x00000158)
-#define NV927C_SET_CSC_BLU2GRN_COEFF                                            18:0
-#define NV927C_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
-#define NV927C_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
-#define NV927C_SET_CSC_RED2BLU                                                  (0x00000160)
-#define NV927C_SET_CSC_RED2BLU_COEFF                                            18:0
-#define NV927C_SET_CSC_GRN2BLU                                                  (0x00000164)
-#define NV927C_SET_CSC_GRN2BLU_COEFF                                            18:0
-#define NV927C_SET_CSC_BLU2BLU                                                  (0x00000168)
-#define NV927C_SET_CSC_BLU2BLU_COEFF                                            18:0
-#define NV927C_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
-#define NV927C_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
-#define NV927C_SET_SPARE                                                        (0x000003BC)
-#define NV927C_SET_SPARE_UNUSED                                                 31:0
-#define NV927C_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
-#define NV927C_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV927C_SURFACE_SET_OFFSET(a,b)                                          (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
-#define NV927C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
-#define NV927C_SURFACE_SET_SIZE(a)                                              (0x00000408 + (a)*0x00000020)
-#define NV927C_SURFACE_SET_SIZE_WIDTH                                           15:0
-#define NV927C_SURFACE_SET_SIZE_HEIGHT                                          31:16
-#define NV927C_SURFACE_SET_STORAGE(a)                                           (0x0000040C + (a)*0x00000020)
-#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
-#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
-#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
-#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
-#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
-#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
-#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
-#define NV927C_SURFACE_SET_STORAGE_PITCH                                        20:8
-#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
-#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
-#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
-#define NV927C_SURFACE_SET_PARAMS(a)                                            (0x00000410 + (a)*0x00000020)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT                                        15:8
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                   (0x00000024)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
-#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10                            (0x000000DF)
-#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
-#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
-#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
-#define NV927C_SURFACE_SET_PARAMS_GAMMA                                         2:2
-#define NV927C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
-#define NV927C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
-#define NV927C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
-#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
-#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
-#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl927c_h
diff --git a/Display-Class-Methods/cl927d.h b/Display-Class-Methods/cl927d.h
deleted file mode 100644
index 4363a79..0000000
--- a/Display-Class-Methods/cl927d.h
+++ /dev/null
@@ -1,1181 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl927d_h_
-#define _cl927d_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV927D_CORE_CHANNEL_DMA                                                 (0x0000927D)
-
-#define NV927D_CORE_NOTIFIER_3                                                      0x00000000
-#define NV927D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
-#define NV927D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
-#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
-#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
-#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
-#define NV927D_CORE_NOTIFIER_3__1                                                   0x00000001
-#define NV927D_CORE_NOTIFIER_3__1_R1                                                31:0
-#define NV927D_CORE_NOTIFIER_3__2                                                   0x00000002
-#define NV927D_CORE_NOTIFIER_3__2_R2                                                31:0
-#define NV927D_CORE_NOTIFIER_3__3                                                   0x00000003
-#define NV927D_CORE_NOTIFIER_3__3_R3                                                31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:27
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
-#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
-
-
-// dma opcode instructions
-#define NV927D_DMA                                                         0x00000000 
-#define NV927D_DMA_OPCODE                                                       31:29 
-#define NV927D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV927D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV927D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV927D_DMA_OPCODE                                                       31:29 
-#define NV927D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV927D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV927D_DMA_METHOD_COUNT                                                 27:18 
-#define NV927D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV927D_DMA_DATA                                                          31:0 
-#define NV927D_DMA_DATA_NOP                                                0x00000000 
-#define NV927D_DMA_OPCODE                                                       31:29 
-#define NV927D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV927D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV927D_DMA_OPCODE                                                       31:29 
-#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV927D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV927D_PUT                                                              (0x00000000)
-#define NV927D_PUT_PTR                                                          11:2
-#define NV927D_GET                                                              (0x00000004)
-#define NV927D_GET_PTR                                                          11:2
-#define NV927D_UPDATE                                                           (0x00000080)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
-#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
-#define NV927D_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV927D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV927D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV927D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV927D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV927D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV927D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV927D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV927D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV927D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV927D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV927D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV927D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV927D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV927D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV927D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV927D_SET_SPARE                                                        (0x0000016C)
-#define NV927D_SET_SPARE_UNUSED                                                 31:0
-#define NV927D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
-#define NV927D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV927D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
-#define NV927D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV927D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV927D_DAC_SET_CONTROL_PROTOCOL                                         12:8
-#define NV927D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV927D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
-#define NV927D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
-#define NV927D_DAC_SET_SW_SPARE_A_CODE                                          31:0
-#define NV927D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
-#define NV927D_DAC_SET_SW_SPARE_B_CODE                                          31:0
-#define NV927D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
-#define NV927D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV927D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
-#define NV927D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV927D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV927D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV927D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV927D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV927D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV927D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
-#define NV927D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NV927D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
-#define NV927D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-#define NV927D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
-#define NV927D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV927D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
-#define NV927D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
-#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
-#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
-#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
-#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
-#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
-#define NV927D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV927D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
-#define NV927D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
-#define NV927D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
-#define NV927D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
-#define NV927D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
-#define NV927D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
-
-#define NV927D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
-#define NV927D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV927D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                20:13
-#define NV927D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
-#define NV927D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV927D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
-#define NV927D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV927D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV927D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV927D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
-#define NV927D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV927D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV927D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
-#define NV927D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV927D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV927D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
-#define NV927D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV927D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV927D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
-#define NV927D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV927D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV927D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
-#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
-#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV927D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
-#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
-#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
-#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
-#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
-#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
-#define NV927D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
-#define NV927D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
-#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
-#define NV927D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
-#define NV927D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NV927D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV927D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
-#define NV927D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV927D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
-#define NV927D_HEAD_SET_SIZE_WIDTH                                              15:0
-#define NV927D_HEAD_SET_SIZE_HEIGHT                                             31:16
-#define NV927D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
-#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV927D_HEAD_SET_STORAGE_PITCH                                           20:8
-#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
-#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV927D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
-#define NV927D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV927D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
-#define NV927D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
-#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV927D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV927D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV927D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV927D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
-#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
-#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
-#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV927D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
-#define NV927D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
-#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
-#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
-#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
-#define NV927D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
-#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV927D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV927D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV927D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
-#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV927D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
-#define NV927D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NV927D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV927D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
-#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
-#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
-#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
-#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
-#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
-#define NV927D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
-#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV927D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
-#define NV927D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
-#define NV927D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
-#define NV927D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
-#define NV927D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
-#define NV927D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
-#define NV927D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
-#define NV927D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
-#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
-#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
-#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
-#define NV927D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
-#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
-#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
-#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
-#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
-#define NV927D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
-#define NV927D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NV927D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NV927D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NV927D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NV927D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NV927D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
-#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
-#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
-#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
-#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
-#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
-#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
-#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
-#define NV927D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
-#define NV927D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV927D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
-#define NV927D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl927d_h
diff --git a/Display-Class-Methods/cl947d.h b/Display-Class-Methods/cl947d.h
deleted file mode 100644
index 66ae39b..0000000
--- a/Display-Class-Methods/cl947d.h
+++ /dev/null
@@ -1,1189 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl947d_h_
-#define _cl947d_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV947D_CORE_CHANNEL_DMA                                                 (0x0000947D)
-
-#define NV947D_CORE_NOTIFIER_3                                                      0x00000000
-#define NV947D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
-#define NV947D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
-#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
-#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
-#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
-#define NV947D_CORE_NOTIFIER_3__1                                                   0x00000001
-#define NV947D_CORE_NOTIFIER_3__1_R1                                                31:0
-#define NV947D_CORE_NOTIFIER_3__2                                                   0x00000002
-#define NV947D_CORE_NOTIFIER_3__2_R2                                                31:0
-#define NV947D_CORE_NOTIFIER_3__3                                                   0x00000003
-#define NV947D_CORE_NOTIFIER_3__3_R3                                                31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_REORDER_BANK_WIDTH_SIZE_MAX 13:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_REORDER_BANK_WIDTH_SIZE_MAX 13:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_REORDER_BANK_WIDTH_SIZE_MAX 13:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_REORDER_BANK_WIDTH_SIZE_MAX 13:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
-#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
-
-
-// dma opcode instructions
-#define NV947D_DMA                                                         0x00000000 
-#define NV947D_DMA_OPCODE                                                       31:29 
-#define NV947D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV947D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV947D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV947D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV947D_DMA_METHOD_COUNT                                                 27:18 
-#define NV947D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV947D_DMA_DATA                                                          31:0 
-#define NV947D_DMA_DATA_NOP                                                0x00000000 
-#define NV947D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV947D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV947D_PUT                                                              (0x00000000)
-#define NV947D_PUT_PTR                                                          11:2
-#define NV947D_GET                                                              (0x00000004)
-#define NV947D_GET_PTR                                                          11:2
-#define NV947D_UPDATE                                                           (0x00000080)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
-#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
-#define NV947D_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV947D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV947D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV947D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV947D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV947D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV947D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV947D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV947D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV947D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV947D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV947D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV947D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV947D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV947D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV947D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV947D_SET_SPARE                                                        (0x0000016C)
-#define NV947D_SET_SPARE_UNUSED                                                 31:0
-#define NV947D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
-#define NV947D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV947D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
-#define NV947D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV947D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV947D_DAC_SET_CONTROL_PROTOCOL                                         12:8
-#define NV947D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV947D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
-#define NV947D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
-#define NV947D_DAC_SET_SW_SPARE_A_CODE                                          31:0
-#define NV947D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
-#define NV947D_DAC_SET_SW_SPARE_B_CODE                                          31:0
-#define NV947D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
-#define NV947D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV947D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
-#define NV947D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV947D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV947D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV947D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV947D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV947D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV947D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
-#define NV947D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NV947D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
-#define NV947D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-#define NV947D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
-#define NV947D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV947D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
-#define NV947D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
-#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
-#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
-#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
-#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
-#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
-#define NV947D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV947D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
-#define NV947D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
-#define NV947D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
-#define NV947D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
-#define NV947D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
-#define NV947D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
-
-#define NV947D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
-#define NV947D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV947D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                20:13
-#define NV947D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
-#define NV947D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV947D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
-#define NV947D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV947D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV947D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV947D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
-#define NV947D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV947D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV947D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
-#define NV947D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV947D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV947D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
-#define NV947D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV947D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV947D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
-#define NV947D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV947D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV947D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
-#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
-#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV947D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
-#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
-#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
-#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
-#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
-#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
-#define NV947D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
-#define NV947D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
-#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
-#define NV947D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
-#define NV947D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NV947D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV947D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
-#define NV947D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV947D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
-#define NV947D_HEAD_SET_SIZE_WIDTH                                              15:0
-#define NV947D_HEAD_SET_SIZE_HEIGHT                                             31:16
-#define NV947D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
-#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV947D_HEAD_SET_STORAGE_PITCH                                           20:8
-#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
-#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV947D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
-#define NV947D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV947D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
-#define NV947D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
-#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV947D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV947D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV947D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV947D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
-#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
-#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
-#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV947D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
-#define NV947D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
-#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
-#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
-#define NV947D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
-#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV947D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV947D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV947D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
-#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV947D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
-#define NV947D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NV947D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV947D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
-#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
-#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
-#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
-#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
-#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
-#define NV947D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
-#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV947D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
-#define NV947D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
-#define NV947D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
-#define NV947D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
-#define NV947D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
-#define NV947D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
-#define NV947D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
-#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
-#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
-#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
-#define NV947D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
-#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
-#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
-#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
-#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
-#define NV947D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
-#define NV947D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NV947D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NV947D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NV947D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NV947D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NV947D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
-#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
-#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
-#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
-#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
-#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
-#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
-#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
-#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
-#define NV947D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
-#define NV947D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV947D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
-#define NV947D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl947d_h
diff --git a/Display-Class-Methods/cl957d.h b/Display-Class-Methods/cl957d.h
deleted file mode 100644
index cc6452f..0000000
--- a/Display-Class-Methods/cl957d.h
+++ /dev/null
@@ -1,1185 +0,0 @@
-/*
- * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl957d_h_
-#define _cl957d_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV957D_CORE_CHANNEL_DMA                                                 (0x0000957D)
-
-#define NV957D_CORE_NOTIFIER_3                                                      0x00000000
-#define NV957D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
-#define NV957D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
-#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
-#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
-#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
-#define NV957D_CORE_NOTIFIER_3__1                                                   0x00000001
-#define NV957D_CORE_NOTIFIER_3__1_R1                                                31:0
-#define NV957D_CORE_NOTIFIER_3__2                                                   0x00000002
-#define NV957D_CORE_NOTIFIER_3__2_R2                                                31:0
-#define NV957D_CORE_NOTIFIER_3__3                                                   0x00000003
-#define NV957D_CORE_NOTIFIER_3__3_R3                                                31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          13:12
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          16:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX                23:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX                31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
-#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
-
-
-// dma opcode instructions
-#define NV957D_DMA                                                         0x00000000 
-#define NV957D_DMA_OPCODE                                                       31:29 
-#define NV957D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV957D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV957D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV957D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV957D_DMA_METHOD_COUNT                                                 27:18 
-#define NV957D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV957D_DMA_DATA                                                          31:0 
-#define NV957D_DMA_DATA_NOP                                                0x00000000 
-#define NV957D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV957D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV957D_PUT                                                              (0x00000000)
-#define NV957D_PUT_PTR                                                          11:2
-#define NV957D_GET                                                              (0x00000004)
-#define NV957D_GET_PTR                                                          11:2
-#define NV957D_UPDATE                                                           (0x00000080)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
-#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
-#define NV957D_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV957D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV957D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV957D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV957D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV957D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV957D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV957D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV957D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV957D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV957D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV957D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV957D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV957D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV957D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV957D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV957D_SET_SPARE                                                        (0x0000016C)
-#define NV957D_SET_SPARE_UNUSED                                                 31:0
-#define NV957D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
-#define NV957D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV957D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
-#define NV957D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV957D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV957D_DAC_SET_CONTROL_PROTOCOL                                         12:8
-#define NV957D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV957D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
-#define NV957D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
-#define NV957D_DAC_SET_SW_SPARE_A_CODE                                          31:0
-#define NV957D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
-#define NV957D_DAC_SET_SW_SPARE_B_CODE                                          31:0
-#define NV957D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
-#define NV957D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV957D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
-#define NV957D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV957D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV957D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV957D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV957D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV957D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV957D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
-#define NV957D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NV957D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
-#define NV957D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-#define NV957D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
-#define NV957D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV957D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
-#define NV957D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
-#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
-#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
-#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
-#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
-#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
-#define NV957D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV957D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
-#define NV957D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
-#define NV957D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
-#define NV957D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
-#define NV957D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
-#define NV957D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
-
-#define NV957D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
-#define NV957D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV957D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                20:13
-#define NV957D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
-#define NV957D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV957D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
-#define NV957D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV957D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV957D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV957D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
-#define NV957D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV957D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV957D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
-#define NV957D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV957D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV957D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
-#define NV957D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV957D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV957D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
-#define NV957D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV957D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV957D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
-#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
-#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV957D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
-#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
-#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
-#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
-#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
-#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
-#define NV957D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
-#define NV957D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
-#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
-#define NV957D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
-#define NV957D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NV957D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV957D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
-#define NV957D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV957D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
-#define NV957D_HEAD_SET_SIZE_WIDTH                                              15:0
-#define NV957D_HEAD_SET_SIZE_HEIGHT                                             31:16
-#define NV957D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
-#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV957D_HEAD_SET_STORAGE_PITCH                                           20:8
-#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
-#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV957D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
-#define NV957D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV957D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
-#define NV957D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
-#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV957D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV957D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV957D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV957D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
-#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
-#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
-#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV957D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
-#define NV957D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
-#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
-#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
-#define NV957D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
-#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV957D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV957D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV957D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
-#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV957D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
-#define NV957D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NV957D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV957D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
-#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
-#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
-#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
-#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
-#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
-#define NV957D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
-#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV957D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
-#define NV957D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
-#define NV957D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
-#define NV957D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
-#define NV957D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
-#define NV957D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
-#define NV957D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
-#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
-#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
-#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
-#define NV957D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
-#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
-#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
-#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
-#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
-#define NV957D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
-#define NV957D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NV957D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NV957D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NV957D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NV957D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NV957D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
-#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
-#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
-#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
-#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
-#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
-#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
-#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
-#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
-#define NV957D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
-#define NV957D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV957D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
-#define NV957D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl957d_h
diff --git a/Display-Class-Methods/cl977d.h b/Display-Class-Methods/cl977d.h
deleted file mode 100644
index b609c8d..0000000
--- a/Display-Class-Methods/cl977d.h
+++ /dev/null
@@ -1,1170 +0,0 @@
-/*
- * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl977d_h_
-#define _cl977d_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV977D_CORE_CHANNEL_DMA                                                 (0x0000977D)
-
-#define NV977D_CORE_NOTIFIER_3                                                      0x00000000
-#define NV977D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
-#define NV977D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
-#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
-#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
-#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
-#define NV977D_CORE_NOTIFIER_3__1                                                   0x00000001
-#define NV977D_CORE_NOTIFIER_3__1_R1                                                31:0
-#define NV977D_CORE_NOTIFIER_3__2                                                   0x00000002
-#define NV977D_CORE_NOTIFIER_3__2_R2                                                31:0
-#define NV977D_CORE_NOTIFIER_3__3                                                   0x00000003
-#define NV977D_CORE_NOTIFIER_3__3_R3                                                31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          13:12
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          16:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX                23:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX                31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
-#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
-
-
-// dma opcode instructions
-#define NV977D_DMA                                                         0x00000000 
-#define NV977D_DMA_OPCODE                                                       31:29 
-#define NV977D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV977D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV977D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV977D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV977D_DMA_METHOD_COUNT                                                 27:18 
-#define NV977D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV977D_DMA_DATA                                                          31:0 
-#define NV977D_DMA_DATA_NOP                                                0x00000000 
-#define NV977D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV977D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV977D_PUT                                                              (0x00000000)
-#define NV977D_PUT_PTR                                                          11:2
-#define NV977D_GET                                                              (0x00000004)
-#define NV977D_GET_PTR                                                          11:2
-#define NV977D_UPDATE                                                           (0x00000080)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
-#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
-#define NV977D_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV977D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV977D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV977D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV977D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV977D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV977D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV977D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV977D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV977D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV977D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV977D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV977D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV977D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV977D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV977D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV977D_SET_SPARE                                                        (0x0000016C)
-#define NV977D_SET_SPARE_UNUSED                                                 31:0
-#define NV977D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
-#define NV977D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV977D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
-#define NV977D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV977D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV977D_DAC_SET_CONTROL_PROTOCOL                                         12:8
-#define NV977D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV977D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
-#define NV977D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
-#define NV977D_DAC_SET_SW_SPARE_A_CODE                                          31:0
-#define NV977D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
-#define NV977D_DAC_SET_SW_SPARE_B_CODE                                          31:0
-#define NV977D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
-#define NV977D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV977D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
-#define NV977D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV977D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV977D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV977D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV977D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV977D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV977D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
-#define NV977D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NV977D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
-#define NV977D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-#define NV977D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
-#define NV977D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV977D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
-#define NV977D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
-#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
-#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
-#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
-#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
-#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
-#define NV977D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV977D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
-#define NV977D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
-#define NV977D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
-#define NV977D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
-#define NV977D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
-#define NV977D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
-
-#define NV977D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
-#define NV977D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV977D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                24:13
-#define NV977D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
-#define NV977D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV977D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
-#define NV977D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV977D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV977D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV977D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
-#define NV977D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV977D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV977D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
-#define NV977D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV977D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV977D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
-#define NV977D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV977D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV977D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
-#define NV977D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV977D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV977D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
-#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
-#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV977D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
-#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
-#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
-#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
-#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
-#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
-#define NV977D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
-#define NV977D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
-#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
-#define NV977D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
-#define NV977D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NV977D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV977D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
-#define NV977D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV977D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
-#define NV977D_HEAD_SET_SIZE_WIDTH                                              15:0
-#define NV977D_HEAD_SET_SIZE_HEIGHT                                             31:16
-#define NV977D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
-#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV977D_HEAD_SET_STORAGE_PITCH                                           20:8
-#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
-#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV977D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
-#define NV977D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV977D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
-#define NV977D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
-#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV977D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV977D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV977D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV977D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
-#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
-#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
-#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV977D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
-#define NV977D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
-#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
-#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
-#define NV977D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
-#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020                            (0x00000003)
-#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV977D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV977D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV977D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
-#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV977D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
-#define NV977D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NV977D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV977D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
-#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
-#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
-#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
-#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
-#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
-#define NV977D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
-#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV977D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
-#define NV977D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
-#define NV977D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
-#define NV977D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
-#define NV977D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
-#define NV977D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
-#define NV977D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
-#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
-#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
-#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
-#define NV977D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
-#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
-#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
-#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
-#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
-#define NV977D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
-#define NV977D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NV977D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NV977D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NV977D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NV977D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NV977D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
-#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
-#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
-#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
-#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
-#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
-#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
-#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
-#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
-#define NV977D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
-#define NV977D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV977D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
-#define NV977D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl977d_h
diff --git a/Display-Class-Methods/cl987d.h b/Display-Class-Methods/cl987d.h
deleted file mode 100644
index cbf4a7b..0000000
--- a/Display-Class-Methods/cl987d.h
+++ /dev/null
@@ -1,1173 +0,0 @@
-/*
- * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _cl987d_h_
-#define _cl987d_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NV987D_CORE_CHANNEL_DMA                                                 (0x0000987D)
-
-#define NV987D_CORE_NOTIFIER_3                                                      0x00000000
-#define NV987D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
-#define NV987D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
-#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
-#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
-#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
-#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
-#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
-#define NV987D_CORE_NOTIFIER_3__1                                                   0x00000001
-#define NV987D_CORE_NOTIFIER_3__1_R1                                                31:0
-#define NV987D_CORE_NOTIFIER_3__2                                                   0x00000002
-#define NV987D_CORE_NOTIFIER_3__2_R2                                                31:0
-#define NV987D_CORE_NOTIFIER_3__3                                                   0x00000003
-#define NV987D_CORE_NOTIFIER_3__3_R3                                                31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          13:12
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          16:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX                23:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX                31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:10
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
-#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
-
-
-// dma opcode instructions
-#define NV987D_DMA                                                         0x00000000 
-#define NV987D_DMA_OPCODE                                                       31:29 
-#define NV987D_DMA_OPCODE_METHOD                                           0x00000000 
-#define NV987D_DMA_OPCODE_JUMP                                             0x00000001 
-#define NV987D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
-#define NV987D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
-#define NV987D_DMA_METHOD_COUNT                                                 27:18 
-#define NV987D_DMA_METHOD_OFFSET                                                 11:2 
-#define NV987D_DMA_DATA                                                          31:0 
-#define NV987D_DMA_DATA_NOP                                                0x00000000 
-#define NV987D_DMA_JUMP_OFFSET                                                   11:2 
-#define NV987D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
-
-// class methods
-#define NV987D_PUT                                                              (0x00000000)
-#define NV987D_PUT_PTR                                                          11:2
-#define NV987D_GET                                                              (0x00000004)
-#define NV987D_GET_PTR                                                          11:2
-#define NV987D_UPDATE                                                           (0x00000080)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
-#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
-#define NV987D_UPDATE_SPECIAL_HANDLING                                          25:24
-#define NV987D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NV987D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NV987D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NV987D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
-#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
-#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
-#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
-#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
-#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
-#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
-#define NV987D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
-#define NV987D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NV987D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NV987D_SET_NOTIFIER_CONTROL                                             (0x00000084)
-#define NV987D_SET_NOTIFIER_CONTROL_MODE                                        30:30
-#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NV987D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
-#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
-#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NV987D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
-#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
-#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
-#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE                              0:0
-#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_FALSE                        (0x00000000)
-#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_TRUE                         (0x00000001)
-#define NV987D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
-#define NV987D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NV987D_GET_CAPABILITIES                                                 (0x0000008C)
-#define NV987D_GET_CAPABILITIES_DUMMY                                           31:0
-#define NV987D_SET_SPARE                                                        (0x0000016C)
-#define NV987D_SET_SPARE_UNUSED                                                 31:0
-#define NV987D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
-#define NV987D_SET_SPARE_NOOP_UNUSED                                            31:0
-
-#define NV987D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
-#define NV987D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV987D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV987D_DAC_SET_CONTROL_PROTOCOL                                         12:8
-#define NV987D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
-#define NV987D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
-#define NV987D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
-#define NV987D_DAC_SET_SW_SPARE_A_CODE                                          31:0
-#define NV987D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
-#define NV987D_DAC_SET_SW_SPARE_B_CODE                                          31:0
-#define NV987D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
-#define NV987D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV987D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
-#define NV987D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
-#define NV987D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NV987D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NV987D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NV987D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NV987D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
-#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NV987D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
-#define NV987D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NV987D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
-#define NV987D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-#define NV987D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
-#define NV987D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-
-#define NV987D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
-#define NV987D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
-#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
-#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
-#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
-#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
-#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
-#define NV987D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
-#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
-#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
-#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
-#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
-#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
-#define NV987D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
-#define NV987D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
-#define NV987D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
-#define NV987D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
-#define NV987D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
-#define NV987D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
-
-#define NV987D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
-#define NV987D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
-#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
-#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NV987D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                24:13
-#define NV987D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
-#define NV987D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
-#define NV987D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
-#define NV987D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
-#define NV987D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
-#define NV987D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
-#define NV987D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
-#define NV987D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NV987D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NV987D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
-#define NV987D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NV987D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NV987D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
-#define NV987D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NV987D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NV987D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
-#define NV987D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NV987D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NV987D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
-#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
-#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
-#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
-#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
-#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
-#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
-#define NV987D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
-#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
-#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
-#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
-#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
-#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
-#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
-#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
-#define NV987D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
-#define NV987D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
-#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
-#define NV987D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
-#define NV987D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NV987D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
-#define NV987D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
-#define NV987D_HEAD_SET_OFFSET_ORIGIN                                           31:0
-#define NV987D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
-#define NV987D_HEAD_SET_SIZE_WIDTH                                              15:0
-#define NV987D_HEAD_SET_SIZE_HEIGHT                                             31:16
-#define NV987D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
-#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
-#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
-#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
-#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
-#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
-#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
-#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
-#define NV987D_HEAD_SET_STORAGE_PITCH                                           20:8
-#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
-#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
-#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
-#define NV987D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
-#define NV987D_HEAD_SET_PARAMS_FORMAT                                           15:8
-#define NV987D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
-#define NV987D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
-#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
-#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
-#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
-#define NV987D_HEAD_SET_PARAMS_GAMMA                                            2:2
-#define NV987D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
-#define NV987D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
-#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
-#define NV987D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
-#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
-#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
-#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
-#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
-#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
-#define NV987D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
-#define NV987D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
-#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
-#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
-#define NV987D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
-#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020                            (0x00000003)
-#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
-#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
-#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
-#define NV987D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
-#define NV987D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
-#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
-#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
-#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NV987D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
-#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NV987D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
-#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
-#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
-#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
-#define NV987D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
-#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NV987D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
-#define NV987D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
-#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
-#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
-#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
-#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
-#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
-#define NV987D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
-#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
-#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
-#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
-#define NV987D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
-#define NV987D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
-#define NV987D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
-#define NV987D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
-#define NV987D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
-#define NV987D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
-#define NV987D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
-#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
-#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
-#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
-#define NV987D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
-#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
-#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
-#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
-#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
-#define NV987D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
-#define NV987D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NV987D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NV987D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NV987D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NV987D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NV987D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
-#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
-#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
-#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
-#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
-#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
-#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
-#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
-#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
-#define NV987D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
-#define NV987D_HEAD_SET_SPARE_UNUSED                                            31:0
-#define NV987D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
-#define NV987D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _cl987d_h
diff --git a/Display-Class-Methods/clc37a.h b/Display-Class-Methods/clc37a.h
deleted file mode 100644
index 3ea9e41..0000000
--- a/Display-Class-Methods/clc37a.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _clc37a__h_
-#define _clc37a__h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NVC37A_CURSOR_IMM_CHANNEL_PIO                                           (0x0000C37A)
-
-typedef volatile struct _clc37a_tag0 {
-    NvV32 Reserved00[0x2];
-    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
-    NvV32 Reserved01[0x7D];
-    NvV32 Update;                                                               // 0x00000200 - 0x00000203
-    NvV32 SetInterlockFlags;                                                    // 0x00000204 - 0x00000207
-    NvV32 SetCursorHotSpotPointOut[2];                                          // 0x00000208 - 0x0000020F
-    NvV32 SetWindowInterlockFlags;                                              // 0x00000210 - 0x00000213
-    NvV32 Reserved02[0x37B];
-} NVC37ADispCursorImmControlPio;
-
-#define NVC37A_FREE                                                             (0x00000008)
-#define NVC37A_FREE_COUNT                                                       5:0
-#define NVC37A_UPDATE                                                           (0x00000200)
-#define NVC37A_SET_INTERLOCK_FLAGS                                              (0x00000204)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0                       0:0
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1                       1:1
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2                       2:2
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3                       3:3
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4                       4:4
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5                       5:5
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6                       6:6
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7                       7:7
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE               (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE                (0x00000001)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE                          16:16
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE                  (0x00000000)
-#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE                   (0x00000001)
-#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT(b)                                 (0x00000208 + (b)*0x00000004)
-#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
-#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS                                       (0x00000210)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0                0:0
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1                1:1
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2                2:2
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3                3:3
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4                4:4
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5                5:5
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6                6:6
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7                7:7
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8                8:8
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9                9:9
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE        (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE         (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10               10:10
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11               11:11
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12               12:12
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13               13:13
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14               14:14
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15               15:15
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16               16:16
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17               17:17
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18               18:18
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19               19:19
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20               20:20
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21               21:21
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22               22:22
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23               23:23
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24               24:24
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25               25:25
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26               26:26
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27               27:27
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28               28:28
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29               29:29
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30               30:30
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE        (0x00000001)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31               31:31
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE       (0x00000000)
-#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE        (0x00000001)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _clc37a_h
-
diff --git a/Display-Class-Methods/clc37b.h b/Display-Class-Methods/clc37b.h
deleted file mode 100644
index b26e44d..0000000
--- a/Display-Class-Methods/clc37b.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _clC37b_h_
-#define _clC37b_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NVC37B_WINDOW_IMM_CHANNEL_DMA                                           (0x0000C37B)
-
-// dma opcode instructions
-#define NVC37B_DMA                                                                     
-#define NVC37B_DMA_OPCODE                                                        31:29 
-#define NVC37B_DMA_OPCODE_METHOD                                            0x00000000 
-#define NVC37B_DMA_OPCODE_JUMP                                              0x00000001 
-#define NVC37B_DMA_OPCODE_NONINC_METHOD                                     0x00000002 
-#define NVC37B_DMA_OPCODE_SET_SUBDEVICE_MASK                                0x00000003 
-#define NVC37B_DMA_METHOD_COUNT                                                  27:18 
-#define NVC37B_DMA_METHOD_OFFSET                                                  13:2 
-#define NVC37B_DMA_DATA                                                           31:0 
-#define NVC37B_DMA_DATA_NOP                                                 0x00000000 
-#define NVC37B_DMA_JUMP_OFFSET                                                    11:2 
-#define NVC37B_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 
-
-// class methods
-#define NVC37B_PUT                                                              (0x00000000)
-#define NVC37B_PUT_PTR                                                          9:0
-#define NVC37B_GET                                                              (0x00000004)
-#define NVC37B_GET_PTR                                                          9:0
-#define NVC37B_UPDATE                                                           (0x00000200)
-#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW                                     1:1
-#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE                             (0x00000000)
-#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE                              (0x00000001)
-#define NVC37B_SET_POINT_OUT(b)                                                 (0x00000208 + (b)*0x00000004)
-#define NVC37B_SET_POINT_OUT_X                                                  15:0
-#define NVC37B_SET_POINT_OUT_Y                                                  31:16
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _clC37b_h
diff --git a/Display-Class-Methods/clc37d.h b/Display-Class-Methods/clc37d.h
deleted file mode 100644
index 4b9e3ba..0000000
--- a/Display-Class-Methods/clc37d.h
+++ /dev/null
@@ -1,625 +0,0 @@
-/*
- * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _clC37d_h_
-#define _clC37d_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NVC37D_CORE_CHANNEL_DMA                                                 (0x0000C37D)
-
-#define NV_DISP_NOTIFIER                                                             0x00000000
-#define NV_DISP_NOTIFIER_SIZEOF                                                      0x00000010
-#define NV_DISP_NOTIFIER__0                                                          0x00000000
-#define NV_DISP_NOTIFIER__0_PRESENT_COUNT                                            7:0
-#define NV_DISP_NOTIFIER__0_FIELD                                                    8:8
-#define NV_DISP_NOTIFIER__0_FLIP_TYPE                                                9:9
-#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING                                    0x00000000
-#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE                                      0x00000001
-#define NV_DISP_NOTIFIER__0_R1                                                       15:10
-#define NV_DISP_NOTIFIER__0_R2                                                       23:16
-#define NV_DISP_NOTIFIER__0_R3                                                       29:24
-#define NV_DISP_NOTIFIER__0_STATUS                                                   31:30
-#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN                                         0x00000000
-#define NV_DISP_NOTIFIER__0_STATUS_BEGUN                                             0x00000001
-#define NV_DISP_NOTIFIER__0_STATUS_FINISHED                                          0x00000002
-#define NV_DISP_NOTIFIER__1                                                          0x00000001
-#define NV_DISP_NOTIFIER__1_R4                                                       31:0
-#define NV_DISP_NOTIFIER__2                                                          0x00000002
-#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO                                             31:0
-#define NV_DISP_NOTIFIER__3                                                          0x00000003
-#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI                                             31:0
-
-
-// dma opcode instructions
-#define NVC37D_DMA                                                                     
-#define NVC37D_DMA_OPCODE                                                        31:29 
-#define NVC37D_DMA_OPCODE_METHOD                                            0x00000000 
-#define NVC37D_DMA_OPCODE_JUMP                                              0x00000001 
-#define NVC37D_DMA_OPCODE_NONINC_METHOD                                     0x00000002 
-#define NVC37D_DMA_OPCODE_SET_SUBDEVICE_MASK                                0x00000003 
-#define NVC37D_DMA_METHOD_COUNT                                                  27:18 
-#define NVC37D_DMA_METHOD_OFFSET                                                  13:2 
-#define NVC37D_DMA_DATA                                                           31:0 
-#define NVC37D_DMA_DATA_NOP                                                 0x00000000 
-#define NVC37D_DMA_JUMP_OFFSET                                                    11:2 
-#define NVC37D_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 
-
-// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to
-#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1)
-#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1)))
-
-// class methods
-#define NVC37D_PUT                                                              (0x00000000)
-#define NVC37D_PUT_PTR                                                          9:0
-#define NVC37D_GET                                                              (0x00000004)
-#define NVC37D_GET_PTR                                                          9:0
-#define NVC37D_UPDATE                                                           (0x00000200)
-#define NVC37D_UPDATE_SPECIAL_HANDLING                                          21:20
-#define NVC37D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
-#define NVC37D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
-#define NVC37D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
-#define NVC37D_UPDATE_SPECIAL_HANDLING_REASON                                   19:12
-#define NVC37D_UPDATE_INHIBIT_INTERRUPTS                                        24:24
-#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
-#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
-#define NVC37D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000208)
-#define NVC37D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NVC37D_SET_NOTIFIER_CONTROL                                             (0x0000020C)
-#define NVC37D_SET_NOTIFIER_CONTROL_MODE                                        0:0
-#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NVC37D_SET_NOTIFIER_CONTROL_OFFSET                                      11:4
-#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY                                      12:12
-#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
-#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
-#define NVC37D_SET_CONTROL                                                      (0x00000210)
-#define NVC37D_SET_INTERLOCK_FLAGS                                              (0x00000218)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i)                     ((i)+0):((i)+0)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1                8
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE                (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE                 (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0                       0:0
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1                       1:1
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2                       2:2
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3                       3:3
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4                       4:4
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5                       5:5
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6                       6:6
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7                       7:7
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE               (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE                (0x00000001)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE                          16:16
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE                  (0x00000000)
-#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE                   (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS                                       (0x0000021C)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i)              ((i)+0):((i)+0)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1         32
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE         (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE          (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0                0:0
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1                1:1
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2                2:2
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3                3:3
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4                4:4
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5                5:5
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6                6:6
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7                7:7
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8                8:8
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9                9:9
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE        (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE         (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10               10:10
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11               11:11
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12               12:12
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13               13:13
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14               14:14
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15               15:15
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16               16:16
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17               17:17
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18               18:18
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19               19:19
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20               20:20
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21               21:21
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22               22:22
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23               23:23
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24               24:24
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25               25:25
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26               26:26
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27               27:27
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28               28:28
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29               29:29
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30               30:30
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE        (0x00000001)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31               31:31
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE       (0x00000000)
-#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE        (0x00000001)
-#define NVC37D_GET_RG_SCAN_LINE(b)                                              (0x00000220 + (b)*0x00000004)
-#define NVC37D_GET_RG_SCAN_LINE_LINE                                            15:0
-#define NVC37D_GET_RG_SCAN_LINE_VBLANK                                          16:16
-#define NVC37D_GET_RG_SCAN_LINE_VBLANK_FALSE                                    (0x00000000)
-#define NVC37D_GET_RG_SCAN_LINE_VBLANK_TRUE                                     (0x00000001)
-#define NVC37D_SET_GET_BLANKING_CTRL(b)                                         (0x00000240 + (b)*0x00000004)
-#define NVC37D_SET_GET_BLANKING_CTRL_BLANK                                      0:0
-#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                            (0x00000000)
-#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_ENABLE                               (0x00000001)
-#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK                                    1:1
-#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                          (0x00000000)
-#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                             (0x00000001)
-
-#define NVC37D_SOR_SET_CONTROL(a)                                               (0x00000300 + (a)*0x00000020)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK                                       7:0
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD4                                 (0x00000010)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD5                                 (0x00000020)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD6                                 (0x00000040)
-#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD7                                 (0x00000080)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL                                         11:8
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DSI                                     (0x0000000A)
-#define NVC37D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
-#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 16:16
-#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
-#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
-#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
-#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
-#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
-#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
-#define NVC37D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000304 + (a)*0x00000020)
-#define NVC37D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
-#define NVC37D_SOR_SET_SW_SPARE_A(a)                                            (0x00000308 + (a)*0x00000020)
-#define NVC37D_SOR_SET_SW_SPARE_A_CODE                                          31:0
-#define NVC37D_SOR_SET_SW_SPARE_B(a)                                            (0x0000030C + (a)*0x00000020)
-#define NVC37D_SOR_SET_SW_SPARE_B_CODE                                          31:0
-
-#define NVC37D_WINDOW_SET_CONTROL(a)                                            (0x00001000 + (a)*0x00000080)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER                                         3:0
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD(i)                                 (0x00000000 +(i))
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1                            8
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD0                                   (0x00000000)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD1                                   (0x00000001)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD2                                   (0x00000002)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD3                                   (0x00000003)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD4                                   (0x00000004)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD5                                   (0x00000005)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD6                                   (0x00000006)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD7                                   (0x00000007)
-#define NVC37D_WINDOW_SET_CONTROL_OWNER_NONE                                    (0x0000000F)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a)                         (0x00001004 + (a)*0x00000080)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP             0:0
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE       (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE        (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP             1:1
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE       (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE        (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP             2:2
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE       (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE        (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP             3:3
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE       (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE        (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422              4:4
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE        (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE         (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420              5:5
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE        (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE         (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444              6:6
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE        (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE         (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420         7:7
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE   (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE    (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422         8:8
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE   (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE    (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R        9:9
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE  (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE   (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444         10:10
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE   (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE    (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420          11:11
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE    (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE     (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444          12:12
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE    (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE     (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420     13:13
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422     14:14
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R    15:15
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444     16:16
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a)                 (0x00001008 + (a)*0x00000080)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP     0:0
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP     1:1
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP     2:2
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP     3:3
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422      4:4
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420      5:5
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444      6:6
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420  11:11
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444  12:12
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
-#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a)                             (0x0000100C + (a)*0x00000080)
-#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL                     15:0
-#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL                       31:16
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a)                                (0x00001010 + (a)*0x00000080)
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE       14:0
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT                         17:16
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_NONE              (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_257               (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_1025              (0x00000002)
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS                 22:20
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2          (0x00000001)
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5          (0x00000004)
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED                 24:24
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE           (0x00000000)
-#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE            (0x00000001)
-
-#define NVC37D_HEAD_SET_PROCAMP(a)                                              (0x00002000 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
-#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
-#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
-#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
-#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020                            (0x00000003)
-#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF                                      3:3
-#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE                              (0x00000000)
-#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE                               (0x00000001)
-#define NVC37D_HEAD_SET_PROCAMP_SAT_COS                                         15:4
-#define NVC37D_HEAD_SET_PROCAMP_SAT_SINE                                        27:16
-#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   28:28
-#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
-#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
-#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               29:29
-#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
-#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
-#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL                                     31:30
-#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_AUTO                                (0x00000000)
-#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_VIDEO                               (0x00000001)
-#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_GRAPHICS                            (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00002004 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  2:2
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  3:3
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     7:4
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000003)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000004)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000005)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000006)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000007)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000008)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            24:24
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                23:12
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x0000200C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
-#define NVC37D_HEAD_SET_DITHER_CONTROL(a)                                       (0x00002018 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
-#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS                                     5:4
-#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS                           (0x00000000)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS                           (0x00000001)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS                          (0x00000002)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS                          (0x00000003)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE                            2:2
-#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE                    (0x00000000)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE                     (0x00000001)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE                                     10:8
-#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
-#define NVC37D_HEAD_SET_DITHER_CONTROL_PHASE                                    13:12
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x0000201C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    0:0
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING                       4:4
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE               (0x00000000)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE                (0x00000001)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  9:8
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
-#define NVC37D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x00002020 + (a)*0x00000400 + (b)*0x00000004)
-#define NVC37D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00002028 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
-#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
-#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a)                              (0x0000202C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL                      15:0
-#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL                        31:16
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS(a)                                    (0x00002030 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR                                2:0
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE                     (0x00000000)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32                  (0x00000001)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64                  (0x00000002)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128                (0x00000003)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256                (0x00000004)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT                            5:4
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE                 (0x00000000)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257                  (0x00000001)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025                 (0x00000002)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED                     8:8
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE               (0x00000000)
-#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE                (0x00000001)
-#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x00002048 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
-#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
-#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x0000204C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
-#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
-#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x00002058 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
-#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
-#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x0000205C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
-#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
-#define NVC37D_HEAD_SET_DESKTOP_COLOR(a)                                        (0x00002060 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_DESKTOP_COLOR_ALPHA                                     7:0
-#define NVC37D_HEAD_SET_DESKTOP_COLOR_RED                                       15:8
-#define NVC37D_HEAD_SET_DESKTOP_COLOR_GREEN                                     23:16
-#define NVC37D_HEAD_SET_DESKTOP_COLOR_BLUE                                      31:24
-#define NVC37D_HEAD_SET_RASTER_SIZE(a)                                          (0x00002064 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
-#define NVC37D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
-#define NVC37D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00002068 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
-#define NVC37D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
-#define NVC37D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000206C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
-#define NVC37D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
-#define NVC37D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00002070 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
-#define NVC37D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
-#define NVC37D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00002078 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_OVERSCAN_COLOR_RED_CR                                   9:0
-#define NVC37D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y                                  19:10
-#define NVC37D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB                                  29:20
-#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a)                           (0x0000207C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR                       9:0
-#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y                      19:10
-#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB                      29:20
-#define NVC37D_HEAD_SET_HDMI_CTRL(a)                                            (0x00002080 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
-#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
-#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
-#define NVC37D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
-#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b)                                 (0x00002088 + (a)*0x00000400 + (b)*0x00000004)
-#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
-#define NVC37D_HEAD_SET_OFFSET_CURSOR(a,b)                                      (0x00002090 + (a)*0x00000400 + (b)*0x00000004)
-#define NVC37D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
-#define NVC37D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x0000209C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   7:0
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x000000E9)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x000000CF)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE                                     9:8
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               19:12
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               27:20
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA                                 29:28
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_NONE                            (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_SRGB                            (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV8_10                         (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV12                           (0x00000003)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a)                           (0x000020A0 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1                           7:0
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT   11:8
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE                         16:16
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND                   (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR                     (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT(a)                                   (0x000020A4 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE                                 1:0
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257                        (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025                       (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE                                5:4
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY                          (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XRBIAS                         (0x00000001)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XVYCC                          (0x00000002)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE                          9:8
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INDEX                    (0x00000000)
-#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE              (0x00000001)
-#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT(a)                                    (0x000020A8 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT_ORIGIN                                31:0
-#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(a)                               (0x000020AC + (a)*0x00000400)
-#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT_HANDLE                           31:0
-#define NVC37D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x0000218C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         0:0
-#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
-#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
-#define NVC37D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
-#define NVC37D_HEAD_SET_SW_SPARE_A(a)                                           (0x00002194 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
-#define NVC37D_HEAD_SET_SW_SPARE_B(a)                                           (0x00002198 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
-#define NVC37D_HEAD_SET_SW_SPARE_C(a)                                           (0x0000219C + (a)*0x00000400)
-#define NVC37D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
-#define NVC37D_HEAD_SET_SW_SPARE_D(a)                                           (0x000021A0 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
-#define NVC37D_HEAD_SET_MIN_FRAME_IDLE(a)                                       (0x00002218 + (a)*0x00000400)
-#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES                     14:0
-#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES                    30:16
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _clC37d_h
diff --git a/Display-Class-Methods/clc37e.h b/Display-Class-Methods/clc37e.h
deleted file mode 100644
index f5fec92..0000000
--- a/Display-Class-Methods/clc37e.h
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in 
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _clC37e_h_
-#define _clC37e_h_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NVC37E_WINDOW_CHANNEL_DMA                                               (0x0000C37E)
-
-// dma opcode instructions
-#define NVC37E_DMA                                                                     
-#define NVC37E_DMA_OPCODE                                                        31:29 
-#define NVC37E_DMA_OPCODE_METHOD                                            0x00000000 
-#define NVC37E_DMA_OPCODE_JUMP                                              0x00000001 
-#define NVC37E_DMA_OPCODE_NONINC_METHOD                                     0x00000002 
-#define NVC37E_DMA_OPCODE_SET_SUBDEVICE_MASK                                0x00000003 
-#define NVC37E_DMA_METHOD_COUNT                                                  27:18 
-#define NVC37E_DMA_METHOD_OFFSET                                                  13:2 
-#define NVC37E_DMA_DATA                                                           31:0 
-#define NVC37E_DMA_DATA_NOP                                                 0x00000000 
-#define NVC37E_DMA_JUMP_OFFSET                                                    11:2 
-#define NVC37E_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 
-
-// class methods
-#define NVC37E_PUT                                                              (0x00000000)
-#define NVC37E_PUT_PTR                                                          9:0
-#define NVC37E_GET                                                              (0x00000004)
-#define NVC37E_GET_PTR                                                          9:0
-#define NVC37E_UPDATE                                                           (0x00000200)
-#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM                                    12:12
-#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE                            (0x00000000)
-#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE                             (0x00000001)
-#define NVC37E_GET_LINE                                                         (0x00000208)
-#define NVC37E_GET_LINE_LINE                                                    15:0
-#define NVC37E_SET_SEMAPHORE_CONTROL                                            (0x0000020C)
-#define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET                                     7:0
-#define NVC37E_SET_SEMAPHORE_ACQUIRE                                            (0x00000210)
-#define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
-#define NVC37E_SET_SEMAPHORE_RELEASE                                            (0x00000214)
-#define NVC37E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
-#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000218)
-#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
-#define NVC37E_SET_CONTEXT_DMA_NOTIFIER                                         (0x0000021C)
-#define NVC37E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
-#define NVC37E_SET_NOTIFIER_CONTROL                                             (0x00000220)
-#define NVC37E_SET_NOTIFIER_CONTROL_MODE                                        0:0
-#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
-#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
-#define NVC37E_SET_NOTIFIER_CONTROL_OFFSET                                      11:4
-#define NVC37E_SET_SIZE                                                         (0x00000224)
-#define NVC37E_SET_SIZE_WIDTH                                                   15:0
-#define NVC37E_SET_SIZE_HEIGHT                                                  31:16
-#define NVC37E_SET_STORAGE                                                      (0x00000228)
-#define NVC37E_SET_STORAGE_BLOCK_HEIGHT                                         3:0
-#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB                (0x00000000)
-#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS               (0x00000001)
-#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS              (0x00000002)
-#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS             (0x00000003)
-#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS           (0x00000004)
-#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS         (0x00000005)
-#define NVC37E_SET_STORAGE_MEMORY_LAYOUT                                        4:4
-#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                            (0x00000000)
-#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_PITCH                                  (0x00000001)
-#define NVC37E_SET_PARAMS                                                       (0x0000022C)
-#define NVC37E_SET_PARAMS_FORMAT                                                7:0
-#define NVC37E_SET_PARAMS_FORMAT_I8                                             (0x0000001E)
-#define NVC37E_SET_PARAMS_FORMAT_R4G4B4A4                                       (0x0000002F)
-#define NVC37E_SET_PARAMS_FORMAT_R5G6B5                                         (0x000000E8)
-#define NVC37E_SET_PARAMS_FORMAT_A1R5G5B5                                       (0x000000E9)
-#define NVC37E_SET_PARAMS_FORMAT_R5G5B5A1                                       (0x0000002E)
-#define NVC37E_SET_PARAMS_FORMAT_A8R8G8B8                                       (0x000000CF)
-#define NVC37E_SET_PARAMS_FORMAT_X8R8G8B8                                       (0x000000E6)
-#define NVC37E_SET_PARAMS_FORMAT_A8B8G8R8                                       (0x000000D5)
-#define NVC37E_SET_PARAMS_FORMAT_X8B8G8R8                                       (0x000000F9)
-#define NVC37E_SET_PARAMS_FORMAT_A2R10G10B10                                    (0x000000DF)
-#define NVC37E_SET_PARAMS_FORMAT_A2B10G10R10                                    (0x000000D1)
-#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                          (0x00000022)
-#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                           (0x00000024)
-#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                         (0x00000023)
-#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16                                (0x000000C6)
-#define NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                            (0x000000CA)
-#define NVC37E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422                              (0x00000028)
-#define NVC37E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422                              (0x00000029)
-#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N444                                 (0x00000035)
-#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422                                 (0x00000036)
-#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422R                                (0x00000037)
-#define NVC37E_SET_PARAMS_FORMAT_Y8___V8U8_N420                                 (0x00000038)
-#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N444                              (0x0000003A)
-#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N420                              (0x0000003B)
-#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N444                              (0x00000055)
-#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422                              (0x00000056)
-#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422R                             (0x00000057)
-#define NVC37E_SET_PARAMS_FORMAT_Y10___V10U10_N420                              (0x00000058)
-#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N444                           (0x0000005A)
-#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N420                           (0x0000005B)
-#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N444                              (0x00000075)
-#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422                              (0x00000076)
-#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422R                             (0x00000077)
-#define NVC37E_SET_PARAMS_FORMAT_Y12___V12U12_N420                              (0x00000078)
-#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N444                           (0x0000007A)
-#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N420                           (0x0000007B)
-#define NVC37E_SET_PARAMS_COLOR_SPACE                                           9:8
-#define NVC37E_SET_PARAMS_COLOR_SPACE_RGB                                       (0x00000000)
-#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_601                                   (0x00000001)
-#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_709                                   (0x00000002)
-#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_2020                                  (0x00000003)
-#define NVC37E_SET_PARAMS_INPUT_RANGE                                           13:12
-#define NVC37E_SET_PARAMS_INPUT_RANGE_BYPASS                                    (0x00000000)
-#define NVC37E_SET_PARAMS_INPUT_RANGE_LIMITED                                   (0x00000001)
-#define NVC37E_SET_PARAMS_INPUT_RANGE_FULL                                      (0x00000002)
-#define NVC37E_SET_PARAMS_UNDERREPLICATE                                        16:16
-#define NVC37E_SET_PARAMS_UNDERREPLICATE_DISABLE                                (0x00000000)
-#define NVC37E_SET_PARAMS_UNDERREPLICATE_ENABLE                                 (0x00000001)
-#define NVC37E_SET_PARAMS_DE_GAMMA                                              21:20
-#define NVC37E_SET_PARAMS_DE_GAMMA_NONE                                         (0x00000000)
-#define NVC37E_SET_PARAMS_DE_GAMMA_SRGB                                         (0x00000001)
-#define NVC37E_SET_PARAMS_DE_GAMMA_YUV8_10                                      (0x00000002)
-#define NVC37E_SET_PARAMS_DE_GAMMA_YUV12                                        (0x00000003)
-#define NVC37E_SET_PARAMS_CSC                                                   17:17
-#define NVC37E_SET_PARAMS_CSC_DISABLE                                           (0x00000000)
-#define NVC37E_SET_PARAMS_CSC_ENABLE                                            (0x00000001)
-#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND                                    18:18
-#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE                            (0x00000000)
-#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE                             (0x00000001)
-#define NVC37E_SET_PARAMS_SWAP_UV                                               19:19
-#define NVC37E_SET_PARAMS_SWAP_UV_DISABLE                                       (0x00000000)
-#define NVC37E_SET_PARAMS_SWAP_UV_ENABLE                                        (0x00000001)
-#define NVC37E_SET_PLANAR_STORAGE(b)                                            (0x00000230 + (b)*0x00000004)
-#define NVC37E_SET_PLANAR_STORAGE_PITCH                                         12:0
-#define NVC37E_SET_CONTEXT_DMA_ISO(b)                                           (0x00000240 + (b)*0x00000004)
-#define NVC37E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
-#define NVC37E_SET_OFFSET(b)                                                    (0x00000260 + (b)*0x00000004)
-#define NVC37E_SET_OFFSET_ORIGIN                                                31:0
-#define NVC37E_SET_PROCESSING                                                   (0x00000280)
-#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS                                  0:0
-#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_DISABLE                          (0x00000000)
-#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_ENABLE                           (0x00000001)
-#define NVC37E_SET_CONVERSION_RED                                               (0x00000284)
-#define NVC37E_SET_CONVERSION_RED_GAIN                                          15:0
-#define NVC37E_SET_CONVERSION_RED_OFFSET                                        31:16
-#define NVC37E_SET_CONVERSION_GREEN                                             (0x00000288)
-#define NVC37E_SET_CONVERSION_GREEN_GAIN                                        15:0
-#define NVC37E_SET_CONVERSION_GREEN_OFFSET                                      31:16
-#define NVC37E_SET_CONVERSION_BLUE                                              (0x0000028C)
-#define NVC37E_SET_CONVERSION_BLUE_GAIN                                         15:0
-#define NVC37E_SET_CONVERSION_BLUE_OFFSET                                       31:16
-#define NVC37E_SET_POINT_IN(b)                                                  (0x00000290 + (b)*0x00000004)
-#define NVC37E_SET_POINT_IN_X                                                   15:0
-#define NVC37E_SET_POINT_IN_Y                                                   31:16
-#define NVC37E_SET_SIZE_IN                                                      (0x00000298)
-#define NVC37E_SET_SIZE_IN_WIDTH                                                14:0
-#define NVC37E_SET_SIZE_IN_HEIGHT                                               30:16
-#define NVC37E_SET_SIZE_OUT                                                     (0x000002A4)
-#define NVC37E_SET_SIZE_OUT_WIDTH                                               14:0
-#define NVC37E_SET_SIZE_OUT_HEIGHT                                              30:16
-#define NVC37E_SET_CONTROL_INPUT_LUT                                            (0x000002B0)
-#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE                                       1:0
-#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257                              (0x00000000)
-#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025                             (0x00000002)
-#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE                                      5:4
-#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY                                (0x00000000)
-#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XRBIAS                               (0x00000001)
-#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XVYCC                                (0x00000002)
-#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE                                9:8
-#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INDEX                          (0x00000000)
-#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE                    (0x00000001)
-#define NVC37E_SET_OFFSET_INPUT_LUT                                             (0x000002B4)
-#define NVC37E_SET_OFFSET_INPUT_LUT_ORIGIN                                      31:0
-#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT                                        (0x000002B8)
-#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT_HANDLE                                 31:0
-#define NVC37E_SET_CSC_RED2RED                                                  (0x000002BC)
-#define NVC37E_SET_CSC_RED2RED_COEFF                                            18:0
-#define NVC37E_SET_CSC_GREEN2RED                                                (0x000002C0)
-#define NVC37E_SET_CSC_GREEN2RED_COEFF                                          18:0
-#define NVC37E_SET_CSC_BLUE2RED                                                 (0x000002C4)
-#define NVC37E_SET_CSC_BLUE2RED_COEFF                                           18:0
-#define NVC37E_SET_CSC_CONSTANT2RED                                             (0x000002C8)
-#define NVC37E_SET_CSC_CONSTANT2RED_COEFF                                       18:0
-#define NVC37E_SET_CSC_RED2GREEN                                                (0x000002CC)
-#define NVC37E_SET_CSC_RED2GREEN_COEFF                                          18:0
-#define NVC37E_SET_CSC_GREEN2GREEN                                              (0x000002D0)
-#define NVC37E_SET_CSC_GREEN2GREEN_COEFF                                        18:0
-#define NVC37E_SET_CSC_BLUE2GREEN                                               (0x000002D4)
-#define NVC37E_SET_CSC_BLUE2GREEN_COEFF                                         18:0
-#define NVC37E_SET_CSC_CONSTANT2GREEN                                           (0x000002D8)
-#define NVC37E_SET_CSC_CONSTANT2GREEN_COEFF                                     18:0
-#define NVC37E_SET_CSC_RED2BLUE                                                 (0x000002DC)
-#define NVC37E_SET_CSC_RED2BLUE_COEFF                                           18:0
-#define NVC37E_SET_CSC_GREEN2BLUE                                               (0x000002E0)
-#define NVC37E_SET_CSC_GREEN2BLUE_COEFF                                         18:0
-#define NVC37E_SET_CSC_BLUE2BLUE                                                (0x000002E4)
-#define NVC37E_SET_CSC_BLUE2BLUE_COEFF                                          18:0
-#define NVC37E_SET_CSC_CONSTANT2BLUE                                            (0x000002E8)
-#define NVC37E_SET_CSC_CONSTANT2BLUE_COEFF                                      18:0
-#define NVC37E_SET_COMPOSITION_CONTROL                                          (0x000002EC)
-#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT                         1:0
-#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE                 (0x00000000)
-#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC                     (0x00000001)
-#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST                     (0x00000002)
-#define NVC37E_SET_COMPOSITION_CONTROL_DEPTH                                    11:4
-#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA                                   (0x000002F0)
-#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K1                                7:0
-#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K2                                15:8
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT                                    (0x000002F4)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT      3:0
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE  (0x00000001)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1   (0x00000002)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT   7:4
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT      11:8
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE  (0x00000001)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1   (0x00000002)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2   (0x00000003)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT   15:12
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT      19:16
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1   (0x00000002)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2   (0x00000003)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT   23:20
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT      27:24
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE  (0x00000001)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2   (0x00000003)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT   31:28
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
-#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
-#define NVC37E_SET_KEY_ALPHA                                                    (0x000002F8)
-#define NVC37E_SET_KEY_ALPHA_MIN                                                15:0
-#define NVC37E_SET_KEY_ALPHA_MAX                                                31:16
-#define NVC37E_SET_KEY_RED_CR                                                   (0x000002FC)
-#define NVC37E_SET_KEY_RED_CR_MIN                                               15:0
-#define NVC37E_SET_KEY_RED_CR_MAX                                               31:16
-#define NVC37E_SET_KEY_GREEN_Y                                                  (0x00000300)
-#define NVC37E_SET_KEY_GREEN_Y_MIN                                              15:0
-#define NVC37E_SET_KEY_GREEN_Y_MAX                                              31:16
-#define NVC37E_SET_KEY_BLUE_CB                                                  (0x00000304)
-#define NVC37E_SET_KEY_BLUE_CB_MIN                                              15:0
-#define NVC37E_SET_KEY_BLUE_CB_MAX                                              31:16
-#define NVC37E_SET_PRESENT_CONTROL                                              (0x00000308)
-#define NVC37E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         3:0
-#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE                                   6:4
-#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
-#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
-#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               8:8
-#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
-#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
-#define NVC37E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000340)
-#define NVC37E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
-#define NVC37E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000344)
-#define NVC37E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
-#define NVC37E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000348)
-#define NVC37E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
-#define NVC37E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000034C)
-#define NVC37E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
-#define NVC37E_SET_INTERLOCK_FLAGS                                              (0x00000370)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE                          0:0
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE                  (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE                   (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i)                     ((i)+1):((i)+1)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1                8
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE                (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE                 (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0                       1:1
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE                (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1                       2:2
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE                (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2                       3:3
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE                (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3                       4:4
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE                (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4                       5:5
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE                (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5                       6:6
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE                (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6                       7:7
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE                (0x00000001)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7                       8:8
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE               (0x00000000)
-#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE                (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS                                       (0x00000374)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i)              ((i)+0):((i)+0)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1         32
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE         (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE          (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0                0:0
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1                1:1
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2                2:2
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3                3:3
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4                4:4
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5                5:5
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6                6:6
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7                7:7
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8                8:8
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9                9:9
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE        (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE         (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10               10:10
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11               11:11
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12               12:12
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13               13:13
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14               14:14
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15               15:15
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16               16:16
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17               17:17
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18               18:18
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19               19:19
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20               20:20
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21               21:21
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22               22:22
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23               23:23
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24               24:24
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25               25:25
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26               26:26
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27               27:27
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28               28:28
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29               29:29
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30               30:30
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE        (0x00000001)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31               31:31
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE       (0x00000000)
-#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE        (0x00000001)
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _clC37e_h
diff --git a/Display-Class-Methods/index.html b/Display-Class-Methods/index.html
deleted file mode 100644
index 42f8268..0000000
--- a/Display-Class-Methods/index.html
+++ /dev/null
@@ -1,46 +0,0 @@
-<html>
-    <head><title>Display-Class-Methods</title></head>
-    <body>
-        <h1>Display-Class-Methods</h1>
-        <a href="README.txt">README.txt</a><br/>
-        <a href="cl507a.h">cl507a.h</a><br/>
-        <a href="cl507b.h">cl507b.h</a><br/>
-        <a href="cl507c.h">cl507c.h</a><br/>
-        <a href="cl507d.h">cl507d.h</a><br/>
-        <a href="cl507e.h">cl507e.h</a><br/>
-        <a href="cl827a.h">cl827a.h</a><br/>
-        <a href="cl827b.h">cl827b.h</a><br/>
-        <a href="cl827c.h">cl827c.h</a><br/>
-        <a href="cl827d.h">cl827d.h</a><br/>
-        <a href="cl827e.h">cl827e.h</a><br/>
-        <a href="cl837c.h">cl837c.h</a><br/>
-        <a href="cl837d.h">cl837d.h</a><br/>
-        <a href="cl837e.h">cl837e.h</a><br/>
-        <a href="cl857a.h">cl857a.h</a><br/>
-        <a href="cl857b.h">cl857b.h</a><br/>
-        <a href="cl857c.h">cl857c.h</a><br/>
-        <a href="cl857d.h">cl857d.h</a><br/>
-        <a href="cl857e.h">cl857e.h</a><br/>
-        <a href="cl887d.h">cl887d.h</a><br/>
-        <a href="cl907a.h">cl907a.h</a><br/>
-        <a href="cl907b.h">cl907b.h</a><br/>
-        <a href="cl907c.h">cl907c.h</a><br/>
-        <a href="cl907d.h">cl907d.h</a><br/>
-        <a href="cl907e.h">cl907e.h</a><br/>
-        <a href="cl917a.h">cl917a.h</a><br/>
-        <a href="cl917b.h">cl917b.h</a><br/>
-        <a href="cl917c.h">cl917c.h</a><br/>
-        <a href="cl917d.h">cl917d.h</a><br/>
-        <a href="cl917e.h">cl917e.h</a><br/>
-        <a href="cl927c.h">cl927c.h</a><br/>
-        <a href="cl927d.h">cl927d.h</a><br/>
-        <a href="cl947d.h">cl947d.h</a><br/>
-        <a href="cl957d.h">cl957d.h</a><br/>
-        <a href="cl977d.h">cl977d.h</a><br/>
-        <a href="cl987d.h">cl987d.h</a><br/>
-        <a href="clc37a.h">clc37a.h</a><br/>
-        <a href="clc37b.h">clc37b.h</a><br/>
-        <a href="clc37d.h">clc37d.h</a><br/>
-        <a href="clc37e.h">clc37e.h</a><br/>
-    </body>
-</html>
diff --git a/classes/compute/cl50c0.h b/classes/compute/cl50c0.h
new file mode 100644
index 0000000..e22fed8
--- /dev/null
+++ b/classes/compute/cl50c0.h
@@ -0,0 +1,741 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_nv50_compute_h_
+#define _cl_nv50_compute_h_
+
+/* This file is generated - do not edit. */
+
+#include "nvtypes.h"
+
+#define NV50_COMPUTE    0x50C0
+
+typedef volatile struct _cl50c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 Notify;
+    NvU32 Reserved_0x108[0x2];
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0xB];
+    NvU32 PmTrigger;
+    NvU32 Reserved_0x144[0xF];
+    NvU32 SetContextDmaNotify;
+    NvU32 Reserved_0x184[0x7];
+    NvU32 SetCtxDmaGlobalMem;
+    NvU32 SetCtxDmaSemaphore;
+    NvU32 Reserved_0x1A8[0x4];
+    NvU32 SetCtxDmaShaderThreadMemory;
+    NvU32 SetCtxDmaShaderThreadStack;
+    NvU32 SetCtxDmaShaderProgram;
+    NvU32 SetCtxDmaTextureSampler;
+    NvU32 SetCtxDmaTextureHeaders;
+    NvU32 SetCtxDmaTexture;
+    NvU32 Reserved_0x1D0[0xC];
+    struct {
+        NvU32 Control;
+        NvU32 QuerySessionKey;
+        NvU32 GetSessionKey;
+        NvU32 SetEncryption;
+    } Decryption[0x1];
+    NvU32 SetCtaProgramA;
+    NvU32 SetCtaProgramB;
+    NvU32 SetShaderThreadStackA;
+    NvU32 SetShaderThreadStackB;
+    NvU32 SetShaderThreadStackC;
+    NvU32 SetApiCallLimit;
+    NvU32 SetShaderL1CacheControl;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 LoadConstantSelector;
+    NvU32 LoadConstant[0x10];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 Reserved_0x284[0x1];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 TestForCompute;
+    NvU32 SetShaderScheduling;
+    NvU32 SetShaderThreadMemoryA;
+    NvU32 SetShaderThreadMemoryB;
+    NvU32 SetShaderThreadMemoryC;
+    NvU32 SetWorkDistribution;
+    NvU32 LoadConstantBufferTableA;
+    NvU32 LoadConstantBufferTableB;
+    NvU32 LoadConstantBufferTableC;
+    NvU32 SetShaderErrorTrapControl;
+    NvU32 SetCtaResourceAllocation;
+    NvU32 SetCtaThreadControl;
+    NvU32 SetPhaseIdControl;
+    NvU32 SetCtaRegisterCount;
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 SetShaderPerformanceCounterValue[0x4];
+    NvU32 SetShaderPerformanceCounterControl[0x4];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 ResetCtaTrackingRam;
+    NvU32 Initialize;
+    NvU32 SetShaderThreadMemoryThrottle;
+    NvU32 SetShaderThreadMemoryThrottleControl;
+    NvU32 SetShaderThreadStackThrottle;
+    NvU32 SetShaderThreadStackThrottleControl;
+    NvU32 PrefetchShaderInstructions;
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 SetLaunchEnableA;
+    NvU32 SetLaunchEnableB;
+    NvU32 SetLaunchEnableC;
+    NvU32 SetCubemapAddressModeOverride;
+    NvU32 PipeNop;
+    NvU32 Reserved_0x334[0x3];
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x350[0x2];
+    NvU32 SetGlobalColorKey;
+    NvU32 ResetRefCount;
+    NvU32 WaitRefCount;
+    NvU32 SetRefCountValue;
+    NvU32 Launch;
+    NvU32 SetLaunchId;
+    NvU32 SetLaunchControl;
+    NvU32 SetParameterSize;
+    NvU32 SetSamplerBinding;
+    NvU32 SetShaderControl;
+    NvU32 InvalidateShaderCache;
+    NvU32 SetRasterControl;
+    NvU32 SetCtaFlags;
+    NvU32 Reserved_0x38C[0x6];
+    NvU32 SetCtaRasterSize;
+    NvU32 SetCtaGrfSize;
+    NvU32 SetCtaThreadDimensionA;
+    NvU32 SetCtaThreadDimensionB;
+    NvU32 SetCtaProgramStart;
+    NvU32 SetCtaRegisterAllocation;
+    NvU32 SetCtaTexture;
+    NvU32 BindCtaTextureSampler;
+    NvU32 BindCtaTextureHeader;
+    NvU32 BindConstantBuffer;
+    NvU32 PrefetchTextureSampler;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x3D4[0x6];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x3F0[0x4];
+    struct {
+        NvU32 A;
+        NvU32 B;
+        NvU32 Size;
+        NvU32 Limit;
+        NvU32 Format;
+        NvU32 Reserved_0x14[0x3];
+    } SetGlobalMem[0x10];
+    NvU32 Parameter[0x40];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+} nv50_compute_t;
+
+
+#define NV50C0_SET_OBJECT                                                                                  0x0000
+#define NV50C0_SET_OBJECT_POINTER                                                                            15:0
+
+#define NV50C0_NO_OPERATION                                                                                0x0100
+#define NV50C0_NO_OPERATION_V                                                                                31:0
+
+#define NV50C0_NOTIFY                                                                                      0x0104
+#define NV50C0_NOTIFY_TYPE                                                                                   31:0
+#define NV50C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NV50C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NV50C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NV50C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NV50C0_PM_TRIGGER                                                                                  0x0140
+#define NV50C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NV50C0_SET_CONTEXT_DMA_NOTIFY                                                                      0x0180
+#define NV50C0_SET_CONTEXT_DMA_NOTIFY_HANDLE                                                                 31:0
+
+#define NV50C0_SET_CTX_DMA_GLOBAL_MEM                                                                      0x01a0
+#define NV50C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE                                                                 31:0
+
+#define NV50C0_SET_CTX_DMA_SEMAPHORE                                                                       0x01a4
+#define NV50C0_SET_CTX_DMA_SEMAPHORE_HANDLE                                                                  31:0
+
+#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY                                                            0x01b8
+#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE                                                       31:0
+
+#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK                                                             0x01bc
+#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE                                                        31:0
+
+#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM                                                                  0x01c0
+#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE                                                             31:0
+
+#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER                                                                 0x01c4
+#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE                                                            31:0
+
+#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS                                                                 0x01c8
+#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE                                                            31:0
+
+#define NV50C0_SET_CTX_DMA_TEXTURE                                                                         0x01cc
+#define NV50C0_SET_CTX_DMA_TEXTURE_HANDLE                                                                    31:0
+
+#define NV50C0_DECRYPTION_CONTROL(j)                                                              (0x0200+(j)*16)
+#define NV50C0_DECRYPTION_CONTROL_ALGORITHM                                                                  15:0
+#define NV50C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE                                            0x00000000
+#define NV50C0_DECRYPTION_CONTROL_KEY_COUNT                                                                 23:16
+
+#define NV50C0_DECRYPTION_QUERY_SESSION_KEY(j)                                                    (0x0204+(j)*16)
+#define NV50C0_DECRYPTION_QUERY_SESSION_KEY_V                                                                31:0
+
+#define NV50C0_DECRYPTION_GET_SESSION_KEY(j)                                                      (0x0208+(j)*16)
+#define NV50C0_DECRYPTION_GET_SESSION_KEY_V                                                                  31:0
+
+#define NV50C0_DECRYPTION_SET_ENCRYPTION(j)                                                       (0x020c+(j)*16)
+#define NV50C0_DECRYPTION_SET_ENCRYPTION_V                                                                   31:0
+
+#define NV50C0_SET_CTA_PROGRAM_A                                                                           0x0210
+#define NV50C0_SET_CTA_PROGRAM_A_OFFSET_UPPER                                                                 7:0
+
+#define NV50C0_SET_CTA_PROGRAM_B                                                                           0x0214
+#define NV50C0_SET_CTA_PROGRAM_B_OFFSET_LOWER                                                                31:0
+
+#define NV50C0_SET_SHADER_THREAD_STACK_A                                                                   0x0218
+#define NV50C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER                                                         7:0
+
+#define NV50C0_SET_SHADER_THREAD_STACK_B                                                                   0x021c
+#define NV50C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER                                                        31:0
+
+#define NV50C0_SET_SHADER_THREAD_STACK_C                                                                   0x0220
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE                                                                 3:0
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__0                                                       0x00000000
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1                                                       0x00000001
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2                                                       0x00000002
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4                                                       0x00000003
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__8                                                       0x00000004
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__16                                                      0x00000005
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__32                                                      0x00000006
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__64                                                      0x00000007
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__128                                                     0x00000008
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__256                                                     0x00000009
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__512                                                     0x0000000A
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1024                                                    0x0000000B
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2048                                                    0x0000000C
+#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4096                                                    0x0000000D
+
+#define NV50C0_SET_API_CALL_LIMIT                                                                          0x0224
+#define NV50C0_SET_API_CALL_LIMIT_CTA                                                                         3:0
+#define NV50C0_SET_API_CALL_LIMIT_CTA__0                                                               0x00000000
+#define NV50C0_SET_API_CALL_LIMIT_CTA__1                                                               0x00000001
+#define NV50C0_SET_API_CALL_LIMIT_CTA__2                                                               0x00000002
+#define NV50C0_SET_API_CALL_LIMIT_CTA__4                                                               0x00000003
+#define NV50C0_SET_API_CALL_LIMIT_CTA__8                                                               0x00000004
+#define NV50C0_SET_API_CALL_LIMIT_CTA__16                                                              0x00000005
+#define NV50C0_SET_API_CALL_LIMIT_CTA__32                                                              0x00000006
+#define NV50C0_SET_API_CALL_LIMIT_CTA__64                                                              0x00000007
+#define NV50C0_SET_API_CALL_LIMIT_CTA__128                                                             0x00000008
+#define NV50C0_SET_API_CALL_LIMIT_CTA_NO_CHECK                                                         0x0000000F
+
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL                                                                 0x0228
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                             0:0
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                0x00000000
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                 0x00000001
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY                                         7:4
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY                                     11:8
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY                                       15:12
+#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY                                    19:16
+
+#define NV50C0_SET_TEX_SAMPLER_POOL_A                                                                      0x022c
+#define NV50C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NV50C0_SET_TEX_SAMPLER_POOL_B                                                                      0x0230
+#define NV50C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NV50C0_SET_TEX_SAMPLER_POOL_C                                                                      0x0234
+#define NV50C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NV50C0_LOAD_CONSTANT_SELECTOR                                                                      0x0238
+#define NV50C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX                                                             7:0
+#define NV50C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX                                                         23:8
+
+#define NV50C0_LOAD_CONSTANT(i)                                                                    (0x023c+(i)*4)
+#define NV50C0_LOAD_CONSTANT_V                                                                               31:0
+
+#define NV50C0_INVALIDATE_SAMPLER_CACHE                                                                    0x027c
+#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NV50C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x0280
+#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NV50C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0288
+#define NV50C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NV50C0_TEST_FOR_COMPUTE                                                                            0x028c
+#define NV50C0_TEST_FOR_COMPUTE_V                                                                            31:0
+
+#define NV50C0_SET_SHADER_SCHEDULING                                                                       0x0290
+#define NV50C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
+#define NV50C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
+#define NV50C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
+
+#define NV50C0_SET_SHADER_THREAD_MEMORY_A                                                                  0x0294
+#define NV50C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER                                                        7:0
+
+#define NV50C0_SET_SHADER_THREAD_MEMORY_B                                                                  0x0298
+#define NV50C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER                                                       31:0
+
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C                                                                  0x029c
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE                                                                3:0
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0                                                      0x00000000
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1                                                      0x00000001
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2                                                      0x00000002
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4                                                      0x00000003
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8                                                      0x00000004
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16                                                     0x00000005
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32                                                     0x00000006
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64                                                     0x00000007
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128                                                    0x00000008
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256                                                    0x00000009
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512                                                    0x0000000A
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024                                                   0x0000000B
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048                                                   0x0000000C
+#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096                                                   0x0000000D
+
+#define NV50C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
+#define NV50C0_SET_WORK_DISTRIBUTION_V                                                                        3:0
+#define NV50C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY                                                 0x00000000
+#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC                                                    0x00000001
+#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC                                                    0x00000002
+#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED                                                      0x00000003
+#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED                                                      0x00000004
+#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC                                               0x00000005
+#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC                                               0x00000006
+#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED                                                 0x00000007
+#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED                                                 0x00000008
+
+#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A                                                                0x02a4
+#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER                                                      7:0
+
+#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B                                                                0x02a8
+#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER                                                     31:0
+
+#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C                                                                0x02ac
+#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE                                                             15:0
+#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY                                                           23:16
+
+#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL                                                               0x02b0
+#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK                                                      0:0
+#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE                                         0x00000000
+#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE                                          0x00000001
+#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK                                                     31:1
+
+#define NV50C0_SET_CTA_RESOURCE_ALLOCATION                                                                 0x02b4
+#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT                                                      15:0
+#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT                                                    23:16
+
+#define NV50C0_SET_CTA_THREAD_CONTROL                                                                      0x02b8
+#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH                                                     0:0
+#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE                                        0x00000000
+#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE                                         0x00000001
+
+#define NV50C0_SET_PHASE_ID_CONTROL                                                                        0x02bc
+#define NV50C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE                                                               2:0
+#define NV50C0_SET_PHASE_ID_CONTROL_LOCK_PHASE                                                                6:4
+
+#define NV50C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
+#define NV50C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
+
+#define NV50C0_SET_TEX_HEADER_POOL_A                                                                       0x02c4
+#define NV50C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NV50C0_SET_TEX_HEADER_POOL_B                                                                       0x02c8
+#define NV50C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NV50C0_SET_TEX_HEADER_POOL_C                                                                       0x02cc
+#define NV50C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x02d0+(i)*4)
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i)                                           (0x02e0+(i)*4)
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE                                                    0:0
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK                                                   6:4
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE                                        0x00000000
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS                                        0x00000001
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM                                        0x00000002
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC                                        0x00000003
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP                                        0x00000004
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU                                        0x00000005
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC                                                   23:8
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT                                                 31:24
+
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x02f0
+#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               3:0
+
+#define NV50C0_RESET_CTA_TRACKING_RAM                                                                      0x02f4
+#define NV50C0_RESET_CTA_TRACKING_RAM_V                                                                      31:0
+
+#define NV50C0_INITIALIZE                                                                                  0x02f8
+#define NV50C0_INITIALIZE_INIT_CTA_SHAPE                                                                      0:0
+#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_FALSE                                                         0x00000000
+#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_TRUE                                                          0x00000001
+
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE                                                           0x02fc
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM                                              2:0
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1                                    0x00000000
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2                                    0x00000001
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4                                    0x00000002
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8                                    0x00000003
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16                                   0x00000004
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                0x00000007
+
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL                                                   0x0300
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V                                                    2:0
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                            0x00000000
+#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX                                  0x00000001
+
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE                                                            0x0304
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM                                               2:0
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1                                     0x00000000
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2                                     0x00000001
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4                                     0x00000002
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8                                     0x00000003
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16                                    0x00000004
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                 0x00000007
+
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL                                                    0x0308
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V                                                     2:0
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                             0x00000000
+#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX                                   0x00000001
+
+#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS                                                                0x030c
+#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA                                                               0:0
+#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE                                                  0x00000000
+#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE                                                   0x00000001
+
+#define NV50C0_SET_REPORT_SEMAPHORE_A                                                                      0x0310
+#define NV50C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NV50C0_SET_REPORT_SEMAPHORE_B                                                                      0x0314
+#define NV50C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NV50C0_SET_REPORT_SEMAPHORE_C                                                                      0x0318
+#define NV50C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NV50C0_SET_REPORT_SEMAPHORE_D                                                                      0x031c
+#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED                                                 0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE                                                                 2:2
+#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED                                                   0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE                                                                 3:3
+#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED                                                   0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION                                                       7:4
+#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED                                         0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON                                                              8:8
+#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED                                                0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                           9:9
+#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT                                                                14:10
+#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED                                                    0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        15:15
+#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+
+#define NV50C0_SET_LAUNCH_ENABLE_A                                                                         0x0320
+#define NV50C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NV50C0_SET_LAUNCH_ENABLE_B                                                                         0x0324
+#define NV50C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NV50C0_SET_LAUNCH_ENABLE_C                                                                         0x0328
+#define NV50C0_SET_LAUNCH_ENABLE_C_MODE                                                                       2:0
+#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE                                                           0x032c
+#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE                                                      31:0
+#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE                                          0x00000000
+#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE                                           0x00000001
+
+#define NV50C0_PIPE_NOP                                                                                    0x0330
+#define NV50C0_PIPE_NOP_V                                                                                    31:0
+
+#define NV50C0_SET_SPARE00                                                                                 0x0340
+#define NV50C0_SET_SPARE00_V                                                                                 31:0
+
+#define NV50C0_SET_SPARE01                                                                                 0x0344
+#define NV50C0_SET_SPARE01_V                                                                                 31:0
+
+#define NV50C0_SET_SPARE02                                                                                 0x0348
+#define NV50C0_SET_SPARE02_V                                                                                 31:0
+
+#define NV50C0_SET_SPARE03                                                                                 0x034c
+#define NV50C0_SET_SPARE03_V                                                                                 31:0
+
+#define NV50C0_SET_GLOBAL_COLOR_KEY                                                                        0x0358
+#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                   31:0
+#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
+#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
+
+#define NV50C0_RESET_REF_COUNT                                                                             0x035c
+#define NV50C0_RESET_REF_COUNT_REF_CNT                                                                        3:0
+
+#define NV50C0_WAIT_REF_COUNT                                                                              0x0360
+#define NV50C0_WAIT_REF_COUNT_COMPARE                                                                         7:4
+#define NV50C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT                                                   0x00000000
+#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL                                                      0x00000001
+#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND                                                  0x00000002
+#define NV50C0_WAIT_REF_COUNT_REF_CNT                                                                        11:8
+
+#define NV50C0_SET_REF_COUNT_VALUE                                                                         0x0364
+#define NV50C0_SET_REF_COUNT_VALUE_V                                                                         31:0
+
+#define NV50C0_LAUNCH                                                                                      0x0368
+#define NV50C0_LAUNCH_V                                                                                      31:0
+
+#define NV50C0_SET_LAUNCH_ID                                                                               0x036c
+#define NV50C0_SET_LAUNCH_ID_REF_CNT                                                                          3:0
+
+#define NV50C0_SET_LAUNCH_CONTROL                                                                          0x0370
+#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH                                                                      7:0
+#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH                                                 0x00000000
+#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH                                                   0x00000001
+
+#define NV50C0_SET_PARAMETER_SIZE                                                                          0x0374
+#define NV50C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX                                                           7:0
+#define NV50C0_SET_PARAMETER_SIZE_COUNT                                                                      15:8
+
+#define NV50C0_SET_SAMPLER_BINDING                                                                         0x0378
+#define NV50C0_SET_SAMPLER_BINDING_V                                                                          0:0
+#define NV50C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
+#define NV50C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
+
+#define NV50C0_SET_SHADER_CONTROL                                                                          0x037c
+#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
+#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
+#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
+#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
+#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
+#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
+
+#define NV50C0_INVALIDATE_SHADER_CACHE                                                                     0x0380
+#define NV50C0_INVALIDATE_SHADER_CACHE_V                                                                      1:0
+#define NV50C0_INVALIDATE_SHADER_CACHE_V_ALL                                                           0x00000000
+#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1                                                            0x00000001
+#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_DATA                                                       0x00000002
+#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION                                                0x00000003
+
+#define NV50C0_SET_RASTER_CONTROL                                                                          0x0384
+#define NV50C0_SET_RASTER_CONTROL_PROGRAM                                                                     7:0
+#define NV50C0_SET_RASTER_CONTROL_PROGRAM_DISABLE                                                      0x00000000
+#define NV50C0_SET_RASTER_CONTROL_FIXED                                                                      15:8
+#define NV50C0_SET_RASTER_CONTROL_FIXED_DISABLE                                                        0x00000000
+#define NV50C0_SET_RASTER_CONTROL_FIXED_SIMPLE                                                         0x00000001
+#define NV50C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED                                                 0x00000002
+#define NV50C0_SET_RASTER_CONTROL_DECRYPTION                                                                23:16
+#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE                                                   0x00000000
+#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE                                                    0x00000001
+
+#define NV50C0_SET_CTA_FLAGS                                                                               0x0388
+#define NV50C0_SET_CTA_FLAGS_V                                                                               15:0
+
+#define NV50C0_SET_CTA_RASTER_SIZE                                                                         0x03a4
+#define NV50C0_SET_CTA_RASTER_SIZE_WIDTH                                                                     15:0
+#define NV50C0_SET_CTA_RASTER_SIZE_HEIGHT                                                                   31:16
+
+#define NV50C0_SET_CTA_GRF_SIZE                                                                            0x03a8
+#define NV50C0_SET_CTA_GRF_SIZE_V                                                                            31:0
+
+#define NV50C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
+#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
+#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
+
+#define NV50C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
+#define NV50C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
+
+#define NV50C0_SET_CTA_PROGRAM_START                                                                       0x03b4
+#define NV50C0_SET_CTA_PROGRAM_START_OFFSET                                                                  23:0
+
+#define NV50C0_SET_CTA_REGISTER_ALLOCATION                                                                 0x03b8
+#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V                                                                 31:0
+#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THICK                                                     0x00000001
+#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THIN                                                      0x00000002
+
+#define NV50C0_SET_CTA_TEXTURE                                                                             0x03bc
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS                                                            3:0
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                                  0x00000000
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                                  0x00000001
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                                  0x00000002
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                                  0x00000003
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                                 0x00000004
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS                                                             7:4
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1                                                   0x00000000
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2                                                   0x00000001
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4                                                   0x00000002
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8                                                   0x00000003
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16                                                  0x00000004
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32                                                  0x00000005
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64                                                  0x00000006
+#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128                                                 0x00000007
+
+#define NV50C0_BIND_CTA_TEXTURE_SAMPLER                                                                    0x03c0
+#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID                                                                 0:0
+#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE                                                    0x00000000
+#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE                                                     0x00000001
+#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                         11:4
+#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_INDEX                                                               24:12
+
+#define NV50C0_BIND_CTA_TEXTURE_HEADER                                                                     0x03c4
+#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID                                                                  0:0
+#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE                                                     0x00000000
+#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE                                                      0x00000001
+#define NV50C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT                                                           8:1
+#define NV50C0_BIND_CTA_TEXTURE_HEADER_INDEX                                                                 30:9
+
+#define NV50C0_BIND_CONSTANT_BUFFER                                                                        0x03c8
+#define NV50C0_BIND_CONSTANT_BUFFER_VALID                                                                     3:0
+#define NV50C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
+#define NV50C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
+#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE                                                               7:4
+#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA                                                    0x00000000
+#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              11:8
+#define NV50C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY                                                             19:12
+
+#define NV50C0_PREFETCH_TEXTURE_SAMPLER                                                                    0x03cc
+#define NV50C0_PREFETCH_TEXTURE_SAMPLER_INDEX                                                                21:0
+
+#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x03d0
+#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           5:4
+#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
+#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY                                            0x00000001
+#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2                                          0x00000002
+
+#define NV50C0_SET_SHADER_EXCEPTIONS                                                                       0x03ec
+#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NV50C0_SET_GLOBAL_MEM_A(j)                                                                (0x0400+(j)*32)
+#define NV50C0_SET_GLOBAL_MEM_A_OFFSET_UPPER                                                                  7:0
+
+#define NV50C0_SET_GLOBAL_MEM_B(j)                                                                (0x0404+(j)*32)
+#define NV50C0_SET_GLOBAL_MEM_B_OFFSET_LOWER                                                                 31:0
+
+#define NV50C0_SET_GLOBAL_MEM_SIZE(j)                                                             (0x0408+(j)*32)
+#define NV50C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH                                                               31:0
+
+#define NV50C0_SET_GLOBAL_MEM_LIMIT(j)                                                            (0x040c+(j)*32)
+#define NV50C0_SET_GLOBAL_MEM_LIMIT_MAX                                                                      31:0
+
+#define NV50C0_SET_GLOBAL_MEM_FORMAT(j)                                                           (0x0410+(j)*32)
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT                                                               0:0
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR                                            0x00000000
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH                                                  0x00000001
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH                                                       7:4
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB                                        0x00000000
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT                                                     11:8
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB                                       0x00000000
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS                                      0x00000001
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS                                     0x00000002
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS                                    0x00000003
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS                                  0x00000004
+#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS                                0x00000005
+
+#define NV50C0_PARAMETER(i)                                                                        (0x0600+(i)*4)
+#define NV50C0_PARAMETER_V                                                                                   31:0
+
+#define NV50C0_SET_SPARE_NOOP00                                                                            0x0700
+#define NV50C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP01                                                                            0x0704
+#define NV50C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP02                                                                            0x0708
+#define NV50C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP03                                                                            0x070c
+#define NV50C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP04                                                                            0x0710
+#define NV50C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP05                                                                            0x0714
+#define NV50C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP06                                                                            0x0718
+#define NV50C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP07                                                                            0x071c
+#define NV50C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP08                                                                            0x0720
+#define NV50C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP09                                                                            0x0724
+#define NV50C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP10                                                                            0x0728
+#define NV50C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP11                                                                            0x072c
+#define NV50C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP12                                                                            0x0730
+#define NV50C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP13                                                                            0x0734
+#define NV50C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP14                                                                            0x0738
+#define NV50C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NV50C0_SET_SPARE_NOOP15                                                                            0x073c
+#define NV50C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#endif /* _cl_nv50_compute_h_ */
diff --git a/classes/compute/cl85c0.h b/classes/compute/cl85c0.h
new file mode 100644
index 0000000..4234fd0
--- /dev/null
+++ b/classes/compute/cl85c0.h
@@ -0,0 +1,747 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_gt214_compute_h_
+#define _cl_gt214_compute_h_
+
+/* This file is generated - do not edit. */
+
+#include "nvtypes.h"
+
+#define GT214_COMPUTE    0x85C0
+
+typedef volatile struct _cl85c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 Notify;
+    NvU32 Reserved_0x108[0x2];
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0xB];
+    NvU32 PmTrigger;
+    NvU32 Reserved_0x144[0xF];
+    NvU32 SetContextDmaNotify;
+    NvU32 Reserved_0x184[0x7];
+    NvU32 SetCtxDmaGlobalMem;
+    NvU32 SetCtxDmaSemaphore;
+    NvU32 Reserved_0x1A8[0x4];
+    NvU32 SetCtxDmaShaderThreadMemory;
+    NvU32 SetCtxDmaShaderThreadStack;
+    NvU32 SetCtxDmaShaderProgram;
+    NvU32 SetCtxDmaTextureSampler;
+    NvU32 SetCtxDmaTextureHeaders;
+    NvU32 SetCtxDmaTexture;
+    NvU32 Reserved_0x1D0[0xC];
+    struct {
+        NvU32 Control;
+        NvU32 QuerySessionKey;
+        NvU32 GetSessionKey;
+        NvU32 SetEncryption;
+    } Decryption[0x1];
+    NvU32 SetCtaProgramA;
+    NvU32 SetCtaProgramB;
+    NvU32 SetShaderThreadStackA;
+    NvU32 SetShaderThreadStackB;
+    NvU32 SetShaderThreadStackC;
+    NvU32 SetApiCallLimit;
+    NvU32 SetShaderL1CacheControl;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 LoadConstantSelector;
+    NvU32 LoadConstant[0x10];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 Reserved_0x284[0x1];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 TestForCompute;
+    NvU32 SetShaderScheduling;
+    NvU32 SetShaderThreadMemoryA;
+    NvU32 SetShaderThreadMemoryB;
+    NvU32 SetShaderThreadMemoryC;
+    NvU32 SetWorkDistribution;
+    NvU32 LoadConstantBufferTableA;
+    NvU32 LoadConstantBufferTableB;
+    NvU32 LoadConstantBufferTableC;
+    NvU32 SetShaderErrorTrapControl;
+    NvU32 SetCtaResourceAllocation;
+    NvU32 SetCtaThreadControl;
+    NvU32 SetPhaseIdControl;
+    NvU32 SetCtaRegisterCount;
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 SetShaderPerformanceCounterValue[0x4];
+    NvU32 SetShaderPerformanceCounterControl[0x4];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 ResetCtaTrackingRam;
+    NvU32 Initialize;
+    NvU32 SetShaderThreadMemoryThrottle;
+    NvU32 SetShaderThreadMemoryThrottleControl;
+    NvU32 SetShaderThreadStackThrottle;
+    NvU32 SetShaderThreadStackThrottleControl;
+    NvU32 PrefetchShaderInstructions;
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 SetLaunchEnableA;
+    NvU32 SetLaunchEnableB;
+    NvU32 SetLaunchEnableC;
+    NvU32 SetCubemapAddressModeOverride;
+    NvU32 PipeNop;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop10;
+    NvU32 SetGlobalColorKey;
+    NvU32 ResetRefCount;
+    NvU32 WaitRefCount;
+    NvU32 SetRefCountValue;
+    NvU32 Launch;
+    NvU32 SetLaunchId;
+    NvU32 SetLaunchControl;
+    NvU32 SetParameterSize;
+    NvU32 SetSamplerBinding;
+    NvU32 SetShaderControl;
+    NvU32 InvalidateShaderCache;
+    NvU32 SetRasterControl;
+    NvU32 SetCtaFlags;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop15;
+    NvU32 SetSpareNoop11;
+    NvU32 SetSpare02;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpare03;
+    NvU32 SetCtaRasterSize;
+    NvU32 SetCtaGrfSize;
+    NvU32 SetCtaThreadDimensionA;
+    NvU32 SetCtaThreadDimensionB;
+    NvU32 SetCtaProgramStart;
+    NvU32 SetCtaRegisterAllocation;
+    NvU32 SetCtaTexture;
+    NvU32 BindCtaTextureSampler;
+    NvU32 BindCtaTextureHeader;
+    NvU32 BindConstantBuffer;
+    NvU32 PrefetchTextureSampler;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop12;
+    NvU32 SetCubemapInterFaceFiltering;
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x3F0[0x4];
+    struct {
+        NvU32 A;
+        NvU32 B;
+        NvU32 Size;
+        NvU32 Limit;
+        NvU32 Format;
+        NvU32 Reserved_0x14[0x3];
+    } SetGlobalMem[0x10];
+    NvU32 Parameter[0x40];
+} gt214_compute_t;
+
+
+#define NV85C0_SET_OBJECT                                                                                  0x0000
+#define NV85C0_SET_OBJECT_POINTER                                                                            15:0
+
+#define NV85C0_NO_OPERATION                                                                                0x0100
+#define NV85C0_NO_OPERATION_V                                                                                31:0
+
+#define NV85C0_NOTIFY                                                                                      0x0104
+#define NV85C0_NOTIFY_TYPE                                                                                   31:0
+#define NV85C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NV85C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NV85C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NV85C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NV85C0_PM_TRIGGER                                                                                  0x0140
+#define NV85C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NV85C0_SET_CONTEXT_DMA_NOTIFY                                                                      0x0180
+#define NV85C0_SET_CONTEXT_DMA_NOTIFY_HANDLE                                                                 31:0
+
+#define NV85C0_SET_CTX_DMA_GLOBAL_MEM                                                                      0x01a0
+#define NV85C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE                                                                 31:0
+
+#define NV85C0_SET_CTX_DMA_SEMAPHORE                                                                       0x01a4
+#define NV85C0_SET_CTX_DMA_SEMAPHORE_HANDLE                                                                  31:0
+
+#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY                                                            0x01b8
+#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE                                                       31:0
+
+#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK                                                             0x01bc
+#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE                                                        31:0
+
+#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM                                                                  0x01c0
+#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE                                                             31:0
+
+#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER                                                                 0x01c4
+#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE                                                            31:0
+
+#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS                                                                 0x01c8
+#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE                                                            31:0
+
+#define NV85C0_SET_CTX_DMA_TEXTURE                                                                         0x01cc
+#define NV85C0_SET_CTX_DMA_TEXTURE_HANDLE                                                                    31:0
+
+#define NV85C0_DECRYPTION_CONTROL(j)                                                              (0x0200+(j)*16)
+#define NV85C0_DECRYPTION_CONTROL_ALGORITHM                                                                  15:0
+#define NV85C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE                                            0x00000000
+#define NV85C0_DECRYPTION_CONTROL_KEY_COUNT                                                                 23:16
+
+#define NV85C0_DECRYPTION_QUERY_SESSION_KEY(j)                                                    (0x0204+(j)*16)
+#define NV85C0_DECRYPTION_QUERY_SESSION_KEY_V                                                                31:0
+
+#define NV85C0_DECRYPTION_GET_SESSION_KEY(j)                                                      (0x0208+(j)*16)
+#define NV85C0_DECRYPTION_GET_SESSION_KEY_V                                                                  31:0
+
+#define NV85C0_DECRYPTION_SET_ENCRYPTION(j)                                                       (0x020c+(j)*16)
+#define NV85C0_DECRYPTION_SET_ENCRYPTION_V                                                                   31:0
+
+#define NV85C0_SET_CTA_PROGRAM_A                                                                           0x0210
+#define NV85C0_SET_CTA_PROGRAM_A_OFFSET_UPPER                                                                 7:0
+
+#define NV85C0_SET_CTA_PROGRAM_B                                                                           0x0214
+#define NV85C0_SET_CTA_PROGRAM_B_OFFSET_LOWER                                                                31:0
+
+#define NV85C0_SET_SHADER_THREAD_STACK_A                                                                   0x0218
+#define NV85C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER                                                         7:0
+
+#define NV85C0_SET_SHADER_THREAD_STACK_B                                                                   0x021c
+#define NV85C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER                                                        31:0
+
+#define NV85C0_SET_SHADER_THREAD_STACK_C                                                                   0x0220
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE                                                                 3:0
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__0                                                       0x00000000
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1                                                       0x00000001
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2                                                       0x00000002
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4                                                       0x00000003
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__8                                                       0x00000004
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__16                                                      0x00000005
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__32                                                      0x00000006
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__64                                                      0x00000007
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__128                                                     0x00000008
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__256                                                     0x00000009
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__512                                                     0x0000000A
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1024                                                    0x0000000B
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2048                                                    0x0000000C
+#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4096                                                    0x0000000D
+
+#define NV85C0_SET_API_CALL_LIMIT                                                                          0x0224
+#define NV85C0_SET_API_CALL_LIMIT_CTA                                                                         3:0
+#define NV85C0_SET_API_CALL_LIMIT_CTA__0                                                               0x00000000
+#define NV85C0_SET_API_CALL_LIMIT_CTA__1                                                               0x00000001
+#define NV85C0_SET_API_CALL_LIMIT_CTA__2                                                               0x00000002
+#define NV85C0_SET_API_CALL_LIMIT_CTA__4                                                               0x00000003
+#define NV85C0_SET_API_CALL_LIMIT_CTA__8                                                               0x00000004
+#define NV85C0_SET_API_CALL_LIMIT_CTA__16                                                              0x00000005
+#define NV85C0_SET_API_CALL_LIMIT_CTA__32                                                              0x00000006
+#define NV85C0_SET_API_CALL_LIMIT_CTA__64                                                              0x00000007
+#define NV85C0_SET_API_CALL_LIMIT_CTA__128                                                             0x00000008
+#define NV85C0_SET_API_CALL_LIMIT_CTA_NO_CHECK                                                         0x0000000F
+
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL                                                                 0x0228
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                             0:0
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                0x00000000
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                 0x00000001
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY                                         7:4
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY                                     11:8
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY                                       15:12
+#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY                                    19:16
+
+#define NV85C0_SET_TEX_SAMPLER_POOL_A                                                                      0x022c
+#define NV85C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NV85C0_SET_TEX_SAMPLER_POOL_B                                                                      0x0230
+#define NV85C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NV85C0_SET_TEX_SAMPLER_POOL_C                                                                      0x0234
+#define NV85C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NV85C0_LOAD_CONSTANT_SELECTOR                                                                      0x0238
+#define NV85C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX                                                             7:0
+#define NV85C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX                                                         23:8
+
+#define NV85C0_LOAD_CONSTANT(i)                                                                    (0x023c+(i)*4)
+#define NV85C0_LOAD_CONSTANT_V                                                                               31:0
+
+#define NV85C0_INVALIDATE_SAMPLER_CACHE                                                                    0x027c
+#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NV85C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x0280
+#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NV85C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0288
+#define NV85C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NV85C0_TEST_FOR_COMPUTE                                                                            0x028c
+#define NV85C0_TEST_FOR_COMPUTE_V                                                                            31:0
+
+#define NV85C0_SET_SHADER_SCHEDULING                                                                       0x0290
+#define NV85C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
+#define NV85C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
+#define NV85C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
+
+#define NV85C0_SET_SHADER_THREAD_MEMORY_A                                                                  0x0294
+#define NV85C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER                                                        7:0
+
+#define NV85C0_SET_SHADER_THREAD_MEMORY_B                                                                  0x0298
+#define NV85C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER                                                       31:0
+
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C                                                                  0x029c
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE                                                                3:0
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0                                                      0x00000000
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1                                                      0x00000001
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2                                                      0x00000002
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4                                                      0x00000003
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8                                                      0x00000004
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16                                                     0x00000005
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32                                                     0x00000006
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64                                                     0x00000007
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128                                                    0x00000008
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256                                                    0x00000009
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512                                                    0x0000000A
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024                                                   0x0000000B
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048                                                   0x0000000C
+#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096                                                   0x0000000D
+
+#define NV85C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
+#define NV85C0_SET_WORK_DISTRIBUTION_V                                                                        3:0
+#define NV85C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY                                                 0x00000000
+#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC                                                    0x00000001
+#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC                                                    0x00000002
+#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED                                                      0x00000003
+#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED                                                      0x00000004
+#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC                                               0x00000005
+#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC                                               0x00000006
+#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED                                                 0x00000007
+#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED                                                 0x00000008
+
+#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A                                                                0x02a4
+#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER                                                      7:0
+
+#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B                                                                0x02a8
+#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER                                                     31:0
+
+#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C                                                                0x02ac
+#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE                                                             15:0
+#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY                                                           23:16
+
+#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL                                                               0x02b0
+#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK                                                      0:0
+#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE                                         0x00000000
+#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE                                          0x00000001
+#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK                                                     31:1
+
+#define NV85C0_SET_CTA_RESOURCE_ALLOCATION                                                                 0x02b4
+#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT                                                      15:0
+#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT                                                    23:16
+
+#define NV85C0_SET_CTA_THREAD_CONTROL                                                                      0x02b8
+#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH                                                     0:0
+#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE                                        0x00000000
+#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE                                         0x00000001
+
+#define NV85C0_SET_PHASE_ID_CONTROL                                                                        0x02bc
+#define NV85C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE                                                               2:0
+#define NV85C0_SET_PHASE_ID_CONTROL_LOCK_PHASE                                                                6:4
+
+#define NV85C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
+#define NV85C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
+
+#define NV85C0_SET_TEX_HEADER_POOL_A                                                                       0x02c4
+#define NV85C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NV85C0_SET_TEX_HEADER_POOL_B                                                                       0x02c8
+#define NV85C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NV85C0_SET_TEX_HEADER_POOL_C                                                                       0x02cc
+#define NV85C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x02d0+(i)*4)
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i)                                           (0x02e0+(i)*4)
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE                                                    0:0
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK                                                   6:4
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE                                        0x00000000
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS                                        0x00000001
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM                                        0x00000002
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC                                        0x00000003
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP                                        0x00000004
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU                                        0x00000005
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC                                                   23:8
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT                                                 31:24
+
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x02f0
+#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               3:0
+
+#define NV85C0_RESET_CTA_TRACKING_RAM                                                                      0x02f4
+#define NV85C0_RESET_CTA_TRACKING_RAM_V                                                                      31:0
+
+#define NV85C0_INITIALIZE                                                                                  0x02f8
+#define NV85C0_INITIALIZE_INIT_CTA_SHAPE                                                                      0:0
+#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_FALSE                                                         0x00000000
+#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_TRUE                                                          0x00000001
+
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE                                                           0x02fc
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM                                              2:0
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1                                    0x00000000
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2                                    0x00000001
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4                                    0x00000002
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8                                    0x00000003
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16                                   0x00000004
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__24                                   0x00000005
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                0x00000007
+
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL                                                   0x0300
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V                                                    2:0
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                            0x00000000
+#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX                                  0x00000001
+
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE                                                            0x0304
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM                                               2:0
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1                                     0x00000000
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2                                     0x00000001
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4                                     0x00000002
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8                                     0x00000003
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16                                    0x00000004
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__24                                    0x00000005
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX                                 0x00000007
+
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL                                                    0x0308
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V                                                     2:0
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX                             0x00000000
+#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX                                   0x00000001
+
+#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS                                                                0x030c
+#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA                                                               0:0
+#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE                                                  0x00000000
+#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE                                                   0x00000001
+
+#define NV85C0_SET_REPORT_SEMAPHORE_A                                                                      0x0310
+#define NV85C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NV85C0_SET_REPORT_SEMAPHORE_B                                                                      0x0314
+#define NV85C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NV85C0_SET_REPORT_SEMAPHORE_C                                                                      0x0318
+#define NV85C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NV85C0_SET_REPORT_SEMAPHORE_D                                                                      0x031c
+#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED                                                 0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE                                                                 2:2
+#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED                                                   0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE                                                                 3:3
+#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED                                                   0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION                                                       7:4
+#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED                                         0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON                                                              8:8
+#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED                                                0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                           9:9
+#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT                                                                14:10
+#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED                                                    0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        15:15
+#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+
+#define NV85C0_SET_LAUNCH_ENABLE_A                                                                         0x0320
+#define NV85C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NV85C0_SET_LAUNCH_ENABLE_B                                                                         0x0324
+#define NV85C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NV85C0_SET_LAUNCH_ENABLE_C                                                                         0x0328
+#define NV85C0_SET_LAUNCH_ENABLE_C_MODE                                                                       2:0
+#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE                                                           0x032c
+#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE                                                      31:0
+#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE                                          0x00000000
+#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE                                           0x00000001
+
+#define NV85C0_PIPE_NOP                                                                                    0x0330
+#define NV85C0_PIPE_NOP_V                                                                                    31:0
+
+#define NV85C0_SET_SPARE_NOOP13                                                                            0x0334
+#define NV85C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP09                                                                            0x0338
+#define NV85C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP14                                                                            0x033c
+#define NV85C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP00                                                                            0x0340
+#define NV85C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP01                                                                            0x0344
+#define NV85C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NV85C0_SET_SPARE00                                                                                 0x0348
+#define NV85C0_SET_SPARE00_V                                                                                 31:0
+
+#define NV85C0_SET_SPARE01                                                                                 0x034c
+#define NV85C0_SET_SPARE01_V                                                                                 31:0
+
+#define NV85C0_SET_SPARE_NOOP05                                                                            0x0350
+#define NV85C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP10                                                                            0x0354
+#define NV85C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NV85C0_SET_GLOBAL_COLOR_KEY                                                                        0x0358
+#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                   31:0
+#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
+#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
+
+#define NV85C0_RESET_REF_COUNT                                                                             0x035c
+#define NV85C0_RESET_REF_COUNT_REF_CNT                                                                        3:0
+
+#define NV85C0_WAIT_REF_COUNT                                                                              0x0360
+#define NV85C0_WAIT_REF_COUNT_COMPARE                                                                         7:4
+#define NV85C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT                                                   0x00000000
+#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL                                                      0x00000001
+#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND                                                  0x00000002
+#define NV85C0_WAIT_REF_COUNT_REF_CNT                                                                        11:8
+
+#define NV85C0_SET_REF_COUNT_VALUE                                                                         0x0364
+#define NV85C0_SET_REF_COUNT_VALUE_V                                                                         31:0
+
+#define NV85C0_LAUNCH                                                                                      0x0368
+#define NV85C0_LAUNCH_V                                                                                      31:0
+
+#define NV85C0_SET_LAUNCH_ID                                                                               0x036c
+#define NV85C0_SET_LAUNCH_ID_REF_CNT                                                                          3:0
+
+#define NV85C0_SET_LAUNCH_CONTROL                                                                          0x0370
+#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH                                                                      7:0
+#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH                                                 0x00000000
+#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH                                                   0x00000001
+
+#define NV85C0_SET_PARAMETER_SIZE                                                                          0x0374
+#define NV85C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX                                                           7:0
+#define NV85C0_SET_PARAMETER_SIZE_COUNT                                                                      15:8
+
+#define NV85C0_SET_SAMPLER_BINDING                                                                         0x0378
+#define NV85C0_SET_SAMPLER_BINDING_V                                                                          0:0
+#define NV85C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
+#define NV85C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
+
+#define NV85C0_SET_SHADER_CONTROL                                                                          0x037c
+#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
+#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
+#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
+#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
+#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
+#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
+
+#define NV85C0_INVALIDATE_SHADER_CACHE                                                                     0x0380
+#define NV85C0_INVALIDATE_SHADER_CACHE_V                                                                      1:0
+#define NV85C0_INVALIDATE_SHADER_CACHE_V_ALL                                                           0x00000000
+#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1                                                            0x00000001
+#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_DATA                                                       0x00000002
+#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION                                                0x00000003
+
+#define NV85C0_SET_RASTER_CONTROL                                                                          0x0384
+#define NV85C0_SET_RASTER_CONTROL_PROGRAM                                                                     7:0
+#define NV85C0_SET_RASTER_CONTROL_PROGRAM_DISABLE                                                      0x00000000
+#define NV85C0_SET_RASTER_CONTROL_FIXED                                                                      15:8
+#define NV85C0_SET_RASTER_CONTROL_FIXED_DISABLE                                                        0x00000000
+#define NV85C0_SET_RASTER_CONTROL_FIXED_SIMPLE                                                         0x00000001
+#define NV85C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED                                                 0x00000002
+#define NV85C0_SET_RASTER_CONTROL_DECRYPTION                                                                23:16
+#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE                                                   0x00000000
+#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE                                                    0x00000001
+
+#define NV85C0_SET_CTA_FLAGS                                                                               0x0388
+#define NV85C0_SET_CTA_FLAGS_V                                                                               15:0
+
+#define NV85C0_SET_SPARE_NOOP06                                                                            0x038c
+#define NV85C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP15                                                                            0x0390
+#define NV85C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP11                                                                            0x0394
+#define NV85C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NV85C0_SET_SPARE02                                                                                 0x0398
+#define NV85C0_SET_SPARE02_V                                                                                 31:0
+
+#define NV85C0_SET_SPARE_NOOP02                                                                            0x039c
+#define NV85C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NV85C0_SET_SPARE03                                                                                 0x03a0
+#define NV85C0_SET_SPARE03_V                                                                                 31:0
+
+#define NV85C0_SET_CTA_RASTER_SIZE                                                                         0x03a4
+#define NV85C0_SET_CTA_RASTER_SIZE_WIDTH                                                                     15:0
+#define NV85C0_SET_CTA_RASTER_SIZE_HEIGHT                                                                   31:16
+
+#define NV85C0_SET_CTA_GRF_SIZE                                                                            0x03a8
+#define NV85C0_SET_CTA_GRF_SIZE_V                                                                            31:0
+
+#define NV85C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
+#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
+#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
+
+#define NV85C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
+#define NV85C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
+
+#define NV85C0_SET_CTA_PROGRAM_START                                                                       0x03b4
+#define NV85C0_SET_CTA_PROGRAM_START_OFFSET                                                                  23:0
+
+#define NV85C0_SET_CTA_REGISTER_ALLOCATION                                                                 0x03b8
+#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V                                                                 31:0
+#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THICK                                                     0x00000001
+#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THIN                                                      0x00000002
+
+#define NV85C0_SET_CTA_TEXTURE                                                                             0x03bc
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS                                                            3:0
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                                  0x00000000
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                                  0x00000001
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                                  0x00000002
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                                  0x00000003
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                                 0x00000004
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS                                                             7:4
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1                                                   0x00000000
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2                                                   0x00000001
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4                                                   0x00000002
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8                                                   0x00000003
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16                                                  0x00000004
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32                                                  0x00000005
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64                                                  0x00000006
+#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128                                                 0x00000007
+
+#define NV85C0_BIND_CTA_TEXTURE_SAMPLER                                                                    0x03c0
+#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID                                                                 0:0
+#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE                                                    0x00000000
+#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE                                                     0x00000001
+#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                         11:4
+#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_INDEX                                                               24:12
+
+#define NV85C0_BIND_CTA_TEXTURE_HEADER                                                                     0x03c4
+#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID                                                                  0:0
+#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE                                                     0x00000000
+#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE                                                      0x00000001
+#define NV85C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT                                                           8:1
+#define NV85C0_BIND_CTA_TEXTURE_HEADER_INDEX                                                                 30:9
+
+#define NV85C0_BIND_CONSTANT_BUFFER                                                                        0x03c8
+#define NV85C0_BIND_CONSTANT_BUFFER_VALID                                                                     3:0
+#define NV85C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
+#define NV85C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
+#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE                                                               7:4
+#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA                                                    0x00000000
+#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              11:8
+#define NV85C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY                                                             19:12
+
+#define NV85C0_PREFETCH_TEXTURE_SAMPLER                                                                    0x03cc
+#define NV85C0_PREFETCH_TEXTURE_SAMPLER_INDEX                                                                21:0
+
+#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x03d0
+#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           5:4
+#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
+#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY                                            0x00000001
+#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2                                          0x00000002
+
+#define NV85C0_SET_SPARE_NOOP03                                                                            0x03d4
+#define NV85C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP07                                                                            0x03d8
+#define NV85C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP04                                                                            0x03dc
+#define NV85C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP08                                                                            0x03e0
+#define NV85C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NV85C0_SET_SPARE_NOOP12                                                                            0x03e4
+#define NV85C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING                                                            0x03e8
+#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE                                                          1:0
+#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP                                          0x00000000
+#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP                                     0x00000001
+#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM                                    0x00000002
+#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM                                   0x00000003
+
+#define NV85C0_SET_SHADER_EXCEPTIONS                                                                       0x03ec
+#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NV85C0_SET_GLOBAL_MEM_A(j)                                                                (0x0400+(j)*32)
+#define NV85C0_SET_GLOBAL_MEM_A_OFFSET_UPPER                                                                  7:0
+
+#define NV85C0_SET_GLOBAL_MEM_B(j)                                                                (0x0404+(j)*32)
+#define NV85C0_SET_GLOBAL_MEM_B_OFFSET_LOWER                                                                 31:0
+
+#define NV85C0_SET_GLOBAL_MEM_SIZE(j)                                                             (0x0408+(j)*32)
+#define NV85C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH                                                               31:0
+
+#define NV85C0_SET_GLOBAL_MEM_LIMIT(j)                                                            (0x040c+(j)*32)
+#define NV85C0_SET_GLOBAL_MEM_LIMIT_MAX                                                                      31:0
+
+#define NV85C0_SET_GLOBAL_MEM_FORMAT(j)                                                           (0x0410+(j)*32)
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT                                                               0:0
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR                                            0x00000000
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH                                                  0x00000001
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH                                                       7:4
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB                                        0x00000000
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT                                                     11:8
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB                                       0x00000000
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS                                      0x00000001
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS                                     0x00000002
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS                                    0x00000003
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS                                  0x00000004
+#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS                                0x00000005
+
+#define NV85C0_PARAMETER(i)                                                                        (0x0600+(i)*4)
+#define NV85C0_PARAMETER_V                                                                                   31:0
+
+#endif /* _cl_gt214_compute_h_ */
diff --git a/classes/compute/cl90c0.h b/classes/compute/cl90c0.h
new file mode 100644
index 0000000..d49ab75
--- /dev/null
+++ b/classes/compute/cl90c0.h
@@ -0,0 +1,1033 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_fermi_compute_a_h_
+#define _cl_fermi_compute_a_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../class/bin/sw_header.pl fermi_compute_a */
+
+#include "nvtypes.h"
+
+#define FERMI_COMPUTE_A    0x90C0
+
+typedef volatile struct _cl90c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 LoadMmeInstructionRamPointer;
+    NvU32 LoadMmeInstructionRam;
+    NvU32 LoadMmeStartAddressRamPointer;
+    NvU32 LoadMmeStartAddressRam;
+    NvU32 SetMmeShadowRamControl;
+    NvU32 Reserved_0x128[0x2];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 Reserved_0x144[0x3];
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0x2B];
+    NvU32 SetShaderLocalMemoryLowSize;
+    NvU32 SetShaderLocalMemoryHighSize;
+    NvU32 SetShaderLocalMemoryCrsSize;
+    NvU32 SetBindingControlTexture;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 Reserved_0x218[0x1];
+    NvU32 InvalidateShaderCaches;
+    NvU32 Reserved_0x220[0x2];
+    NvU32 BindTextureSampler;
+    NvU32 BindTextureHeader;
+    NvU32 BindExtraTextureSampler;
+    NvU32 BindExtraTextureHeader;
+    NvU32 SetCtaRasterSizeA;
+    NvU32 SetCtaRasterSizeB;
+    NvU32 Reserved_0x240[0x1];
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 Reserved_0x248[0x1];
+    NvU32 SetShaderSharedMemorySize;
+    NvU32 SetCtaThreadCount;
+    NvU32 SetCtaBarrierCount;
+    NvU32 Reserved_0x258[0xD];
+    NvU32 TestForCompute;
+    NvU32 Reserved_0x290[0x3];
+    NvU32 BeginGrid;
+    NvU32 SetWorkDistribution;
+    NvU32 Reserved_0x2A4[0x7];
+    NvU32 SetCtaRegisterCount;
+    NvU32 SetGaToVaMappingMode;
+    NvU32 LoadGaToVaMappingEntry;
+    NvU32 Reserved_0x2CC[0xF];
+    NvU32 SetL1Configuration;
+    NvU32 SetRenderEnableControl;
+    NvU32 Reserved_0x310[0x14];
+    NvU32 WaitRefCount;
+    NvU32 Reserved_0x364[0x1];
+    NvU32 Launch;
+    NvU32 SetLaunchId;
+    NvU32 Reserved_0x370[0xF];
+    NvU32 SetCtaThreadDimensionA;
+    NvU32 SetCtaThreadDimensionB;
+    NvU32 SetCtaProgramStart;
+    NvU32 Reserved_0x3B8[0x52];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x76];
+    NvU32 SetMaxSmCount;
+    NvU32 Reserved_0x75C[0x8];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 SetGridParam;
+    NvU32 Reserved_0x784[0x3];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 SetShaderLocalMemoryC;
+    NvU32 SetShaderLocalMemoryD;
+    NvU32 SetShaderLocalMemoryE;
+    NvU32 Reserved_0x7A4[0x98];
+    NvU32 EndGrid;
+    NvU32 SetLaunchSize;
+    NvU32 Reserved_0xA0C[0xD6];
+    NvU32 SetApiVisibleCallLimit;
+    NvU32 Reserved_0xD68[0xB];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x2C];
+    NvU32 SetForceOneTextureUnit;
+    NvU32 Reserved_0x1008[0xE];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x21];
+    NvU32 UnbindAll;
+    NvU32 Reserved_0x10F8[0x4F];
+    NvU32 SetSamplerBinding;
+    NvU32 Reserved_0x1238[0x14];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x8];
+    NvU32 SetShaderScheduling;
+    NvU32 Reserved_0x12B0[0x20];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x6];
+    NvU32 SetGlobalColorKey;
+    NvU32 Reserved_0x1358[0x33];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x3F];
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x15];
+    NvU32 SetCubemapInterFaceFiltering;
+    NvU32 Reserved_0x1668[0xA];
+    NvU32 SetShaderControl;
+    NvU32 BindConstantBuffer;
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xA5];
+    NvU32 InvalidateConstantBufferCache;
+    NvU32 Reserved_0x1934[0x4];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x21C];
+    NvU32 SetConstantBufferSelectorA;
+    NvU32 SetConstantBufferSelectorB;
+    NvU32 SetConstantBufferSelectorC;
+    NvU32 LoadConstantBufferOffset;
+    NvU32 LoadConstantBuffer[0x10];
+    NvU32 Reserved_0x23D0[0xCC];
+    struct {
+        NvU32 A;
+        NvU32 B;
+        NvU32 C;
+        NvU32 D;
+        NvU32 Format;
+        NvU32 BlockSize;
+        NvU32 Reserved_0x18[0x2];
+    } SetSuLdStTarget[0x8];
+    NvU32 Reserved_0x2800[0x2D7];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 Reserved_0x33E0[0x8];
+    NvU32 SetMmeShadowScratch[0x80];
+    NvU32 Reserved_0x3600[0x80];
+    struct {
+        NvU32 Macro;
+        NvU32 Data;
+    } CallMme[0x80];
+} fermi_compute_a_t;
+
+
+#define NV90C0_SET_OBJECT                                                                                  0x0000
+#define NV90C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NV90C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NV90C0_NO_OPERATION                                                                                0x0100
+#define NV90C0_NO_OPERATION_V                                                                                31:0
+
+#define NV90C0_SET_NOTIFY_A                                                                                0x0104
+#define NV90C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NV90C0_SET_NOTIFY_B                                                                                0x0108
+#define NV90C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NV90C0_NOTIFY                                                                                      0x010c
+#define NV90C0_NOTIFY_TYPE                                                                                   31:0
+#define NV90C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NV90C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NV90C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NV90C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER                                                            0x0114
+#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V                                                            31:0
+
+#define NV90C0_LOAD_MME_INSTRUCTION_RAM                                                                    0x0118
+#define NV90C0_LOAD_MME_INSTRUCTION_RAM_V                                                                    31:0
+
+#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER                                                          0x011c
+#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V                                                          31:0
+
+#define NV90C0_LOAD_MME_START_ADDRESS_RAM                                                                  0x0120
+#define NV90C0_LOAD_MME_START_ADDRESS_RAM_V                                                                  31:0
+
+#define NV90C0_SET_MME_SHADOW_RAM_CONTROL                                                                  0x0124
+#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE                                                                1:0
+#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK                                            0x00000000
+#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER                                0x00000001
+#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH                                      0x00000002
+#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY                                           0x00000003
+
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NV90C0_SEND_GO_IDLE                                                                                0x013c
+#define NV90C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NV90C0_PM_TRIGGER                                                                                  0x0140
+#define NV90C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE                                                            0x0204
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V                                                            23:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE                                                           0x0208
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V                                                           23:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE                                                            0x020c
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V                                                            20:0
+
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE                                                                 0x0210
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS                                                3:0
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                      0x00000000
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                      0x00000001
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                      0x00000002
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                      0x00000003
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                     0x00000004
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS                                                 7:4
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1                                       0x00000000
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2                                       0x00000001
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4                                       0x00000002
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8                                       0x00000003
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16                                      0x00000004
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32                                      0x00000005
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64                                      0x00000006
+#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128                                     0x00000007
+
+#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NV90C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM                                                               8:8
+#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE                                                  0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE                                                   0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NV90C0_BIND_TEXTURE_SAMPLER                                                                        0x0228
+#define NV90C0_BIND_TEXTURE_SAMPLER_VALID                                                                     0:0
+#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_FALSE                                                        0x00000000
+#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_TRUE                                                         0x00000001
+#define NV90C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT                                                             11:4
+#define NV90C0_BIND_TEXTURE_SAMPLER_INDEX                                                                   24:12
+
+#define NV90C0_BIND_TEXTURE_HEADER                                                                         0x022c
+#define NV90C0_BIND_TEXTURE_HEADER_VALID                                                                      0:0
+#define NV90C0_BIND_TEXTURE_HEADER_VALID_FALSE                                                         0x00000000
+#define NV90C0_BIND_TEXTURE_HEADER_VALID_TRUE                                                          0x00000001
+#define NV90C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT                                                               8:1
+#define NV90C0_BIND_TEXTURE_HEADER_INDEX                                                                     30:9
+
+#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER                                                                  0x0230
+#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID                                                               0:0
+#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE                                                  0x00000000
+#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE                                                   0x00000001
+#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                       11:4
+#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX                                                             24:12
+
+#define NV90C0_BIND_EXTRA_TEXTURE_HEADER                                                                   0x0234
+#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID                                                                0:0
+#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE                                                   0x00000000
+#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE                                                    0x00000001
+#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT                                                         8:1
+#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_INDEX                                                               30:9
+
+#define NV90C0_SET_CTA_RASTER_SIZE_A                                                                       0x0238
+#define NV90C0_SET_CTA_RASTER_SIZE_A_WIDTH                                                                   15:0
+#define NV90C0_SET_CTA_RASTER_SIZE_A_HEIGHT                                                                 31:16
+
+#define NV90C0_SET_CTA_RASTER_SIZE_B                                                                       0x023c
+#define NV90C0_SET_CTA_RASTER_SIZE_B_DEPTH                                                                   15:0
+
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE                                                               0x024c
+#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE_V                                                               17:0
+
+#define NV90C0_SET_CTA_THREAD_COUNT                                                                        0x0250
+#define NV90C0_SET_CTA_THREAD_COUNT_V                                                                        15:0
+
+#define NV90C0_SET_CTA_BARRIER_COUNT                                                                       0x0254
+#define NV90C0_SET_CTA_BARRIER_COUNT_V                                                                        7:0
+
+#define NV90C0_TEST_FOR_COMPUTE                                                                            0x028c
+#define NV90C0_TEST_FOR_COMPUTE_V                                                                            31:0
+
+#define NV90C0_BEGIN_GRID                                                                                  0x029c
+#define NV90C0_BEGIN_GRID_V                                                                                   0:0
+
+#define NV90C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
+#define NV90C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE                                                         16:13
+#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE                                                               4:4
+#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE                                                  0x00000000
+#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE                                                   0x00000001
+#define NV90C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS                                                        12:5
+
+#define NV90C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
+#define NV90C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
+
+#define NV90C0_SET_GA_TO_VA_MAPPING_MODE                                                                   0x02c4
+#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V                                                                    0:0
+#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE                                                     0x00000000
+#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE                                                      0x00000001
+
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY                                                                 0x02c8
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER                                              7:0
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER                                            23:16
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE                                                      30:30
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE                                           0x00000000
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE                                            0x00000001
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE                                                     31:31
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE                                          0x00000000
+#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE                                           0x00000001
+
+#define NV90C0_SET_L1_CONFIGURATION                                                                        0x0308
+#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY                                               2:0
+#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB                              0x00000001
+#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB                              0x00000003
+
+#define NV90C0_SET_RENDER_ENABLE_CONTROL                                                                   0x030c
+#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER                                     0:0
+#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE                        0x00000000
+#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE                         0x00000001
+
+#define NV90C0_WAIT_REF_COUNT                                                                              0x0360
+#define NV90C0_WAIT_REF_COUNT_REF_CNT                                                                         9:8
+#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM                                                                   0:0
+#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE                                                      0x00000000
+#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE                                                       0x00000001
+
+#define NV90C0_LAUNCH                                                                                      0x0368
+#define NV90C0_LAUNCHCTA_PARAM                                                                               31:0
+
+#define NV90C0_SET_LAUNCH_ID                                                                               0x036c
+#define NV90C0_SET_LAUNCH_ID_REF_CNT                                                                          1:0
+
+#define NV90C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
+#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
+#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
+
+#define NV90C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
+#define NV90C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
+
+#define NV90C0_SET_CTA_PROGRAM_START                                                                       0x03b4
+#define NV90C0_SET_CTA_PROGRAM_START_OFFSET                                                                  31:0
+
+#define NV90C0_SET_FALCON00                                                                                0x0500
+#define NV90C0_SET_FALCON00_V                                                                                31:0
+
+#define NV90C0_SET_FALCON01                                                                                0x0504
+#define NV90C0_SET_FALCON01_V                                                                                31:0
+
+#define NV90C0_SET_FALCON02                                                                                0x0508
+#define NV90C0_SET_FALCON02_V                                                                                31:0
+
+#define NV90C0_SET_FALCON03                                                                                0x050c
+#define NV90C0_SET_FALCON03_V                                                                                31:0
+
+#define NV90C0_SET_FALCON04                                                                                0x0510
+#define NV90C0_SET_FALCON04_V                                                                                31:0
+
+#define NV90C0_SET_FALCON05                                                                                0x0514
+#define NV90C0_SET_FALCON05_V                                                                                31:0
+
+#define NV90C0_SET_FALCON06                                                                                0x0518
+#define NV90C0_SET_FALCON06_V                                                                                31:0
+
+#define NV90C0_SET_FALCON07                                                                                0x051c
+#define NV90C0_SET_FALCON07_V                                                                                31:0
+
+#define NV90C0_SET_FALCON08                                                                                0x0520
+#define NV90C0_SET_FALCON08_V                                                                                31:0
+
+#define NV90C0_SET_FALCON09                                                                                0x0524
+#define NV90C0_SET_FALCON09_V                                                                                31:0
+
+#define NV90C0_SET_FALCON10                                                                                0x0528
+#define NV90C0_SET_FALCON10_V                                                                                31:0
+
+#define NV90C0_SET_FALCON11                                                                                0x052c
+#define NV90C0_SET_FALCON11_V                                                                                31:0
+
+#define NV90C0_SET_FALCON12                                                                                0x0530
+#define NV90C0_SET_FALCON12_V                                                                                31:0
+
+#define NV90C0_SET_FALCON13                                                                                0x0534
+#define NV90C0_SET_FALCON13_V                                                                                31:0
+
+#define NV90C0_SET_FALCON14                                                                                0x0538
+#define NV90C0_SET_FALCON14_V                                                                                31:0
+
+#define NV90C0_SET_FALCON15                                                                                0x053c
+#define NV90C0_SET_FALCON15_V                                                                                31:0
+
+#define NV90C0_SET_FALCON16                                                                                0x0540
+#define NV90C0_SET_FALCON16_V                                                                                31:0
+
+#define NV90C0_SET_FALCON17                                                                                0x0544
+#define NV90C0_SET_FALCON17_V                                                                                31:0
+
+#define NV90C0_SET_FALCON18                                                                                0x0548
+#define NV90C0_SET_FALCON18_V                                                                                31:0
+
+#define NV90C0_SET_FALCON19                                                                                0x054c
+#define NV90C0_SET_FALCON19_V                                                                                31:0
+
+#define NV90C0_SET_FALCON20                                                                                0x0550
+#define NV90C0_SET_FALCON20_V                                                                                31:0
+
+#define NV90C0_SET_FALCON21                                                                                0x0554
+#define NV90C0_SET_FALCON21_V                                                                                31:0
+
+#define NV90C0_SET_FALCON22                                                                                0x0558
+#define NV90C0_SET_FALCON22_V                                                                                31:0
+
+#define NV90C0_SET_FALCON23                                                                                0x055c
+#define NV90C0_SET_FALCON23_V                                                                                31:0
+
+#define NV90C0_SET_FALCON24                                                                                0x0560
+#define NV90C0_SET_FALCON24_V                                                                                31:0
+
+#define NV90C0_SET_FALCON25                                                                                0x0564
+#define NV90C0_SET_FALCON25_V                                                                                31:0
+
+#define NV90C0_SET_FALCON26                                                                                0x0568
+#define NV90C0_SET_FALCON26_V                                                                                31:0
+
+#define NV90C0_SET_FALCON27                                                                                0x056c
+#define NV90C0_SET_FALCON27_V                                                                                31:0
+
+#define NV90C0_SET_FALCON28                                                                                0x0570
+#define NV90C0_SET_FALCON28_V                                                                                31:0
+
+#define NV90C0_SET_FALCON29                                                                                0x0574
+#define NV90C0_SET_FALCON29_V                                                                                31:0
+
+#define NV90C0_SET_FALCON30                                                                                0x0578
+#define NV90C0_SET_FALCON30_V                                                                                31:0
+
+#define NV90C0_SET_FALCON31                                                                                0x057c
+#define NV90C0_SET_FALCON31_V                                                                                31:0
+
+#define NV90C0_SET_MAX_SM_COUNT                                                                            0x0758
+#define NV90C0_SET_MAX_SM_COUNT_V                                                                             8:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NV90C0_SET_GRID_PARAM                                                                              0x0780
+#define NV90C0_SET_GRID_PARAM_V                                                                              31:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_C                                                                   0x0798
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER                                                           5:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_D                                                                   0x079c
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER                                                          31:0
+
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_E                                                                   0x07a0
+#define NV90C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP                                               25:0
+
+#define NV90C0_END_GRID                                                                                    0x0a04
+#define NV90C0_END_GRID_V                                                                                     0:0
+
+#define NV90C0_SET_LAUNCH_SIZE                                                                             0x0a08
+#define NV90C0_SET_LAUNCH_SIZE_V                                                                             31:0
+
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT                                                                  0x0d64
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA                                                                 3:0
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0                                                       0x00000000
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1                                                       0x00000001
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2                                                       0x00000002
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4                                                       0x00000003
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8                                                       0x00000004
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16                                                      0x00000005
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32                                                      0x00000006
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64                                                      0x00000007
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128                                                     0x00000008
+#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK                                                 0x0000000F
+
+#define NV90C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NV90C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NV90C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NV90C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NV90C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NV90C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NV90C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NV90C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT                                                                  0x1004
+#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE                                                              0:0
+#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE                                                 0x00000000
+#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE                                                  0x00000001
+
+#define NV90C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NV90C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NV90C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NV90C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NV90C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NV90C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NV90C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NV90C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NV90C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NV90C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NV90C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NV90C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NV90C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NV90C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NV90C0_UNBIND_ALL                                                                                  0x10f4
+#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS                                                                     0:0
+#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE                                                        0x00000000
+#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE                                                         0x00000001
+#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS                                                                    4:4
+#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE                                                       0x00000000
+#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE                                                        0x00000001
+#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS                                                                    8:8
+#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE                                                       0x00000000
+#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE                                                        0x00000001
+
+#define NV90C0_SET_SAMPLER_BINDING                                                                         0x1234
+#define NV90C0_SET_SAMPLER_BINDING_V                                                                          0:0
+#define NV90C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
+#define NV90C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
+
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NV90C0_SET_SHADER_SCHEDULING                                                                       0x12ac
+#define NV90C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
+#define NV90C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
+#define NV90C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
+
+#define NV90C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           2:1
+#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
+
+#define NV90C0_SET_GLOBAL_COLOR_KEY                                                                        0x1354
+#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                    0:0
+#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
+#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
+
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NV90C0_PERFMON_TRANSFER                                                                            0x1524
+#define NV90C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NV90C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NV90C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NV90C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NV90C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NV90C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NV90C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NV90C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NV90C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NV90C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NV90C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NV90C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NV90C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NV90C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NV90C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NV90C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NV90C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NV90C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NV90C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NV90C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NV90C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NV90C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NV90C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NV90C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NV90C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
+
+#define NV90C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NV90C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING                                                            0x1664
+#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE                                                          1:0
+#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP                                          0x00000000
+#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP                                     0x00000001
+#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM                                    0x00000002
+#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM                                   0x00000003
+
+#define NV90C0_SET_SHADER_CONTROL                                                                          0x1690
+#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
+#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
+#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
+#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
+#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
+#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
+
+#define NV90C0_BIND_CONSTANT_BUFFER                                                                        0x1694
+#define NV90C0_BIND_CONSTANT_BUFFER_VALID                                                                     0:0
+#define NV90C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
+#define NV90C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
+#define NV90C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              12:8
+
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM                                                        8:8
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE                                           0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE                                            0x00000001
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE                                                            0x1930
+#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2                                                       0:0
+#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE                                          0x00000000
+#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE                                           0x00000001
+
+#define NV90C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NV90C0_PIPE_NOP                                                                                    0x1a2c
+#define NV90C0_PIPE_NOP_V                                                                                    31:0
+
+#define NV90C0_SET_SPARE00                                                                                 0x1a30
+#define NV90C0_SET_SPARE00_V                                                                                 31:0
+
+#define NV90C0_SET_SPARE01                                                                                 0x1a34
+#define NV90C0_SET_SPARE01_V                                                                                 31:0
+
+#define NV90C0_SET_SPARE02                                                                                 0x1a38
+#define NV90C0_SET_SPARE02_V                                                                                 31:0
+
+#define NV90C0_SET_SPARE03                                                                                 0x1a3c
+#define NV90C0_SET_SPARE03_V                                                                                 31:0
+
+#define NV90C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NV90C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NV90C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NV90C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NV90C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NV90C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NV90C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+
+#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A                                                              0x2380
+#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE                                                           16:0
+
+#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B                                                              0x2384
+#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER                                                   7:0
+
+#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C                                                              0x2388
+#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER                                                  31:0
+
+#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET                                                                 0x238c
+#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET_V                                                                 15:0
+
+#define NV90C0_LOAD_CONSTANT_BUFFER(i)                                                             (0x2390+(i)*4)
+#define NV90C0_LOAD_CONSTANT_BUFFER_V                                                                        31:0
+
+#define NV90C0_SET_SU_LD_ST_TARGET_A(j)                                                           (0x2700+(j)*32)
+#define NV90C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER                                                             7:0
+
+#define NV90C0_SET_SU_LD_ST_TARGET_B(j)                                                           (0x2704+(j)*32)
+#define NV90C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER                                                            31:0
+
+#define NV90C0_SET_SU_LD_ST_TARGET_C(j)                                                           (0x2708+(j)*32)
+#define NV90C0_SET_SU_LD_ST_TARGET_C_WIDTH                                                                   31:0
+
+#define NV90C0_SET_SU_LD_ST_TARGET_D(j)                                                           (0x270c+(j)*32)
+#define NV90C0_SET_SU_LD_ST_TARGET_D_HEIGHT                                                                  16:0
+#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY                                                       20:20
+#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR                                      0x00000000
+#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH                                            0x00000001
+
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT(j)                                                      (0x2710+(j)*32)
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE                                                                0:0
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR                                                   0x00000000
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA                                                    0x00000001
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR                                                              11:4
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED                                               0x00000000
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32                                    0x000000C0
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32                                    0x000000C1
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32                                    0x000000C2
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32                                     0x000000C3
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32                                     0x000000C4
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32                                     0x000000C5
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16                                        0x000000C6
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16                                    0x000000C7
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16                                    0x000000C8
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16                                    0x000000C9
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16                                    0x000000CA
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32                                              0x000000CB
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32                                              0x000000CC
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32                                              0x000000CD
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16                                     0x000000CE
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8                                               0x000000CF
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8                                            0x000000D0
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10                                            0x000000D1
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10                                        0x000000D2
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8                                               0x000000D5
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8                                            0x000000D6
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8                                           0x000000D7
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8                                           0x000000D8
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8                                           0x000000D9
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16                                                0x000000DA
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16                                              0x000000DB
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16                                              0x000000DC
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16                                              0x000000DD
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16                                              0x000000DE
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10                                            0x000000DF
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11                                           0x000000E0
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32                                                   0x000000E3
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32                                                   0x000000E4
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32                                                   0x000000E5
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8                                               0x000000E6
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8                                            0x000000E7
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5                                                 0x000000E8
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5                                               0x000000E9
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8                                                   0x000000EA
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8                                                 0x000000EB
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8                                                 0x000000EC
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8                                                 0x000000ED
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16                                                    0x000000EE
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16                                                   0x000000EF
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16                                                   0x000000F0
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16                                                   0x000000F1
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16                                                   0x000000F2
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8                                                     0x000000F3
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8                                                    0x000000F4
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8                                                    0x000000F5
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8                                                    0x000000F6
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8                                                     0x000000F7
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5                                               0x000000F8
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8                                               0x000000F9
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8                                            0x000000FA
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5                                               0x000000FB
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5                                               0x000000FC
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8                                               0x000000FD
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8                                               0x000000FE
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32                                                    0x000000FF
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16                                                    0x00000040
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16                                                   0x00000041
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32                                                   0x00000042
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8                                                   0x00000043
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16                                                0x00000044
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16                                              0x00000045
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32                                              0x00000046
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA                                                              16:12
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16                                                     0x00000013
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8                                                   0x00000014
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24                                                   0x00000015
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24                                                   0x00000016
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24                                                   0x00000018
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32                                                    0x0000000A
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8                                              0x00000019
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8                                           0x0000001D
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8                                            0x0000001E
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8                                            0x0000001F
+#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT                                                        25:17
+
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j)                                                  (0x2714+(j)*32)
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH                                                           3:0
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB                                            0x00000000
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT                                                          7:4
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB                                           0x00000000
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS                                          0x00000001
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                         0x00000002
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                        0x00000003
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                      0x00000004
+#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                    0x00000005
+
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                2:0
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           6:4
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                               10:8
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                         14:12
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              18:16
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         22:20
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              26:24
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         30:28
+
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NV90C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NV90C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#define NV90C0_CALL_MME_MACRO(j)                                                                   (0x3800+(j)*8)
+#define NV90C0_CALL_MME_MACRO_V                                                                              31:0
+
+#define NV90C0_CALL_MME_DATA(j)                                                                    (0x3804+(j)*8)
+#define NV90C0_CALL_MME_DATA_V                                                                               31:0
+
+#endif /* _cl_fermi_compute_a_h_ */
diff --git a/classes/compute/cl91c0.h b/classes/compute/cl91c0.h
new file mode 100644
index 0000000..b83f4aa
--- /dev/null
+++ b/classes/compute/cl91c0.h
@@ -0,0 +1,1049 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_fermi_compute_b_h_
+#define _cl_fermi_compute_b_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../class/bin/sw_header.pl fermi_compute_b */
+
+#include "nvtypes.h"
+
+#define FERMI_COMPUTE_B    0x91C0
+
+typedef volatile struct _cl91c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 LoadMmeInstructionRamPointer;
+    NvU32 LoadMmeInstructionRam;
+    NvU32 LoadMmeStartAddressRamPointer;
+    NvU32 LoadMmeStartAddressRam;
+    NvU32 SetMmeShadowRamControl;
+    NvU32 Reserved_0x128[0x2];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 Reserved_0x144[0x3];
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0x2B];
+    NvU32 SetShaderLocalMemoryLowSize;
+    NvU32 SetShaderLocalMemoryHighSize;
+    NvU32 SetShaderLocalMemoryCrsSize;
+    NvU32 SetBindingControlTexture;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 Reserved_0x218[0x1];
+    NvU32 InvalidateShaderCaches;
+    NvU32 Reserved_0x220[0x2];
+    NvU32 BindTextureSampler;
+    NvU32 BindTextureHeader;
+    NvU32 BindExtraTextureSampler;
+    NvU32 BindExtraTextureHeader;
+    NvU32 SetCtaRasterSizeA;
+    NvU32 SetCtaRasterSizeB;
+    NvU32 Reserved_0x240[0x1];
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 Reserved_0x248[0x1];
+    NvU32 SetShaderSharedMemorySize;
+    NvU32 SetCtaThreadCount;
+    NvU32 SetCtaBarrierCount;
+    NvU32 Reserved_0x258[0xD];
+    NvU32 TestForCompute;
+    NvU32 Reserved_0x290[0x3];
+    NvU32 BeginGrid;
+    NvU32 SetWorkDistribution;
+    NvU32 Reserved_0x2A4[0x7];
+    NvU32 SetCtaRegisterCount;
+    NvU32 SetGaToVaMappingMode;
+    NvU32 LoadGaToVaMappingEntry;
+    NvU32 Reserved_0x2CC[0x5];
+    NvU32 SetTexHeaderExtendedDimensions;
+    NvU32 Reserved_0x2E4[0x9];
+    NvU32 SetL1Configuration;
+    NvU32 SetRenderEnableControl;
+    NvU32 Reserved_0x310[0x14];
+    NvU32 WaitRefCount;
+    NvU32 Reserved_0x364[0x1];
+    NvU32 Launch;
+    NvU32 SetLaunchId;
+    NvU32 Reserved_0x370[0xF];
+    NvU32 SetCtaThreadDimensionA;
+    NvU32 SetCtaThreadDimensionB;
+    NvU32 SetCtaProgramStart;
+    NvU32 Reserved_0x3B8[0x52];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x76];
+    NvU32 SetMaxSmCount;
+    NvU32 Reserved_0x75C[0x8];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 SetGridParam;
+    NvU32 Reserved_0x784[0x3];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 SetShaderLocalMemoryC;
+    NvU32 SetShaderLocalMemoryD;
+    NvU32 SetShaderLocalMemoryE;
+    NvU32 Reserved_0x7A4[0x98];
+    NvU32 EndGrid;
+    NvU32 SetLaunchSize;
+    NvU32 Reserved_0xA0C[0xD6];
+    NvU32 SetApiVisibleCallLimit;
+    NvU32 Reserved_0xD68[0xB];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x2C];
+    NvU32 SetForceOneTextureUnit;
+    NvU32 Reserved_0x1008[0xE];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x21];
+    NvU32 UnbindAll;
+    NvU32 Reserved_0x10F8[0x4F];
+    NvU32 SetSamplerBinding;
+    NvU32 Reserved_0x1238[0x14];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x8];
+    NvU32 SetShaderScheduling;
+    NvU32 Reserved_0x12B0[0x20];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x6];
+    NvU32 SetGlobalColorKey;
+    NvU32 Reserved_0x1358[0x33];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x3F];
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x15];
+    NvU32 SetCubemapInterFaceFiltering;
+    NvU32 Reserved_0x1668[0xA];
+    NvU32 SetShaderControl;
+    NvU32 BindConstantBuffer;
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xA5];
+    NvU32 InvalidateConstantBufferCache;
+    NvU32 Reserved_0x1934[0x4];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x21C];
+    NvU32 SetConstantBufferSelectorA;
+    NvU32 SetConstantBufferSelectorB;
+    NvU32 SetConstantBufferSelectorC;
+    NvU32 LoadConstantBufferOffset;
+    NvU32 LoadConstantBuffer[0x10];
+    NvU32 Reserved_0x23D0[0xCC];
+    struct {
+        NvU32 A;
+        NvU32 B;
+        NvU32 C;
+        NvU32 D;
+        NvU32 Format;
+        NvU32 BlockSize;
+        NvU32 Reserved_0x18[0x2];
+    } SetSuLdStTarget[0x8];
+    NvU32 Reserved_0x2800[0x2D7];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 Reserved_0x33E0[0x8];
+    NvU32 SetMmeShadowScratch[0x80];
+    NvU32 Reserved_0x3600[0x80];
+    struct {
+        NvU32 Macro;
+        NvU32 Data;
+    } CallMme[0x80];
+} fermi_compute_b_t;
+
+
+#define NV91C0_SET_OBJECT                                                                                  0x0000
+#define NV91C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NV91C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NV91C0_NO_OPERATION                                                                                0x0100
+#define NV91C0_NO_OPERATION_V                                                                                31:0
+
+#define NV91C0_SET_NOTIFY_A                                                                                0x0104
+#define NV91C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NV91C0_SET_NOTIFY_B                                                                                0x0108
+#define NV91C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NV91C0_NOTIFY                                                                                      0x010c
+#define NV91C0_NOTIFY_TYPE                                                                                   31:0
+#define NV91C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NV91C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NV91C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NV91C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER                                                            0x0114
+#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V                                                            31:0
+
+#define NV91C0_LOAD_MME_INSTRUCTION_RAM                                                                    0x0118
+#define NV91C0_LOAD_MME_INSTRUCTION_RAM_V                                                                    31:0
+
+#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER                                                          0x011c
+#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V                                                          31:0
+
+#define NV91C0_LOAD_MME_START_ADDRESS_RAM                                                                  0x0120
+#define NV91C0_LOAD_MME_START_ADDRESS_RAM_V                                                                  31:0
+
+#define NV91C0_SET_MME_SHADOW_RAM_CONTROL                                                                  0x0124
+#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE                                                                1:0
+#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK                                            0x00000000
+#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER                                0x00000001
+#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH                                      0x00000002
+#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY                                           0x00000003
+
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NV91C0_SEND_GO_IDLE                                                                                0x013c
+#define NV91C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NV91C0_PM_TRIGGER                                                                                  0x0140
+#define NV91C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE                                                            0x0204
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V                                                            23:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE                                                           0x0208
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V                                                           23:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE                                                            0x020c
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V                                                            20:0
+
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE                                                                 0x0210
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS                                                3:0
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1                                      0x00000000
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2                                      0x00000001
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4                                      0x00000002
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8                                      0x00000003
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16                                     0x00000004
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS                                                 7:4
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1                                       0x00000000
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2                                       0x00000001
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4                                       0x00000002
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8                                       0x00000003
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16                                      0x00000004
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32                                      0x00000005
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64                                      0x00000006
+#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128                                     0x00000007
+
+#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NV91C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM                                                               8:8
+#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE                                                  0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE                                                   0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NV91C0_BIND_TEXTURE_SAMPLER                                                                        0x0228
+#define NV91C0_BIND_TEXTURE_SAMPLER_VALID                                                                     0:0
+#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_FALSE                                                        0x00000000
+#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_TRUE                                                         0x00000001
+#define NV91C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT                                                             11:4
+#define NV91C0_BIND_TEXTURE_SAMPLER_INDEX                                                                   24:12
+
+#define NV91C0_BIND_TEXTURE_HEADER                                                                         0x022c
+#define NV91C0_BIND_TEXTURE_HEADER_VALID                                                                      0:0
+#define NV91C0_BIND_TEXTURE_HEADER_VALID_FALSE                                                         0x00000000
+#define NV91C0_BIND_TEXTURE_HEADER_VALID_TRUE                                                          0x00000001
+#define NV91C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT                                                               8:1
+#define NV91C0_BIND_TEXTURE_HEADER_INDEX                                                                     30:9
+
+#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER                                                                  0x0230
+#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID                                                               0:0
+#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE                                                  0x00000000
+#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE                                                   0x00000001
+#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT                                                       11:4
+#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX                                                             24:12
+
+#define NV91C0_BIND_EXTRA_TEXTURE_HEADER                                                                   0x0234
+#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID                                                                0:0
+#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE                                                   0x00000000
+#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE                                                    0x00000001
+#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT                                                         8:1
+#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_INDEX                                                               30:9
+
+#define NV91C0_SET_CTA_RASTER_SIZE_A                                                                       0x0238
+#define NV91C0_SET_CTA_RASTER_SIZE_A_WIDTH                                                                   15:0
+#define NV91C0_SET_CTA_RASTER_SIZE_A_HEIGHT                                                                 31:16
+
+#define NV91C0_SET_CTA_RASTER_SIZE_B                                                                       0x023c
+#define NV91C0_SET_CTA_RASTER_SIZE_B_DEPTH                                                                   15:0
+#define NV91C0_SET_CTA_RASTER_SIZE_B_WIDTH_UPPER                                                            31:16
+
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE                                                               0x024c
+#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE_V                                                               17:0
+
+#define NV91C0_SET_CTA_THREAD_COUNT                                                                        0x0250
+#define NV91C0_SET_CTA_THREAD_COUNT_V                                                                        15:0
+
+#define NV91C0_SET_CTA_BARRIER_COUNT                                                                       0x0254
+#define NV91C0_SET_CTA_BARRIER_COUNT_V                                                                        7:0
+
+#define NV91C0_TEST_FOR_COMPUTE                                                                            0x028c
+#define NV91C0_TEST_FOR_COMPUTE_V                                                                            31:0
+
+#define NV91C0_BEGIN_GRID                                                                                  0x029c
+#define NV91C0_BEGIN_GRID_V                                                                                   0:0
+
+#define NV91C0_SET_WORK_DISTRIBUTION                                                                       0x02a0
+#define NV91C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE                                                         16:13
+#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE                                                               4:4
+#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE                                                  0x00000000
+#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE                                                   0x00000001
+#define NV91C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS                                                        12:5
+
+#define NV91C0_SET_CTA_REGISTER_COUNT                                                                      0x02c0
+#define NV91C0_SET_CTA_REGISTER_COUNT_V                                                                       7:0
+
+#define NV91C0_SET_GA_TO_VA_MAPPING_MODE                                                                   0x02c4
+#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V                                                                    0:0
+#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE                                                     0x00000000
+#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE                                                      0x00000001
+
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY                                                                 0x02c8
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER                                              7:0
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER                                            23:16
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE                                                      30:30
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE                                           0x00000000
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE                                            0x00000001
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE                                                     31:31
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE                                          0x00000000
+#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE                                           0x00000001
+
+#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS                                                          0x02e0
+#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE                                                      0:0
+#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_FALSE                                         0x00000000
+#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_TRUE                                          0x00000001
+
+#define NV91C0_SET_L1_CONFIGURATION                                                                        0x0308
+#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY                                               2:0
+#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB                              0x00000001
+#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB                              0x00000002
+#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB                              0x00000003
+
+#define NV91C0_SET_RENDER_ENABLE_CONTROL                                                                   0x030c
+#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER                                     0:0
+#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE                        0x00000000
+#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE                         0x00000001
+
+#define NV91C0_WAIT_REF_COUNT                                                                              0x0360
+#define NV91C0_WAIT_REF_COUNT_REF_CNT                                                                        11:8
+#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM                                                                   0:0
+#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE                                                      0x00000000
+#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE                                                       0x00000001
+
+#define NV91C0_LAUNCH                                                                                      0x0368
+#define NV91C0_LAUNCHCTA_PARAM                                                                               31:0
+
+#define NV91C0_SET_LAUNCH_ID                                                                               0x036c
+#define NV91C0_SET_LAUNCH_ID_REF_CNT                                                                          3:0
+
+#define NV91C0_SET_CTA_THREAD_DIMENSION_A                                                                  0x03ac
+#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D0                                                                 15:0
+#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D1                                                                31:16
+
+#define NV91C0_SET_CTA_THREAD_DIMENSION_B                                                                  0x03b0
+#define NV91C0_SET_CTA_THREAD_DIMENSION_B_D2                                                                 15:0
+
+#define NV91C0_SET_CTA_PROGRAM_START                                                                       0x03b4
+#define NV91C0_SET_CTA_PROGRAM_START_OFFSET                                                                  31:0
+
+#define NV91C0_SET_FALCON00                                                                                0x0500
+#define NV91C0_SET_FALCON00_V                                                                                31:0
+
+#define NV91C0_SET_FALCON01                                                                                0x0504
+#define NV91C0_SET_FALCON01_V                                                                                31:0
+
+#define NV91C0_SET_FALCON02                                                                                0x0508
+#define NV91C0_SET_FALCON02_V                                                                                31:0
+
+#define NV91C0_SET_FALCON03                                                                                0x050c
+#define NV91C0_SET_FALCON03_V                                                                                31:0
+
+#define NV91C0_SET_FALCON04                                                                                0x0510
+#define NV91C0_SET_FALCON04_V                                                                                31:0
+
+#define NV91C0_SET_FALCON05                                                                                0x0514
+#define NV91C0_SET_FALCON05_V                                                                                31:0
+
+#define NV91C0_SET_FALCON06                                                                                0x0518
+#define NV91C0_SET_FALCON06_V                                                                                31:0
+
+#define NV91C0_SET_FALCON07                                                                                0x051c
+#define NV91C0_SET_FALCON07_V                                                                                31:0
+
+#define NV91C0_SET_FALCON08                                                                                0x0520
+#define NV91C0_SET_FALCON08_V                                                                                31:0
+
+#define NV91C0_SET_FALCON09                                                                                0x0524
+#define NV91C0_SET_FALCON09_V                                                                                31:0
+
+#define NV91C0_SET_FALCON10                                                                                0x0528
+#define NV91C0_SET_FALCON10_V                                                                                31:0
+
+#define NV91C0_SET_FALCON11                                                                                0x052c
+#define NV91C0_SET_FALCON11_V                                                                                31:0
+
+#define NV91C0_SET_FALCON12                                                                                0x0530
+#define NV91C0_SET_FALCON12_V                                                                                31:0
+
+#define NV91C0_SET_FALCON13                                                                                0x0534
+#define NV91C0_SET_FALCON13_V                                                                                31:0
+
+#define NV91C0_SET_FALCON14                                                                                0x0538
+#define NV91C0_SET_FALCON14_V                                                                                31:0
+
+#define NV91C0_SET_FALCON15                                                                                0x053c
+#define NV91C0_SET_FALCON15_V                                                                                31:0
+
+#define NV91C0_SET_FALCON16                                                                                0x0540
+#define NV91C0_SET_FALCON16_V                                                                                31:0
+
+#define NV91C0_SET_FALCON17                                                                                0x0544
+#define NV91C0_SET_FALCON17_V                                                                                31:0
+
+#define NV91C0_SET_FALCON18                                                                                0x0548
+#define NV91C0_SET_FALCON18_V                                                                                31:0
+
+#define NV91C0_SET_FALCON19                                                                                0x054c
+#define NV91C0_SET_FALCON19_V                                                                                31:0
+
+#define NV91C0_SET_FALCON20                                                                                0x0550
+#define NV91C0_SET_FALCON20_V                                                                                31:0
+
+#define NV91C0_SET_FALCON21                                                                                0x0554
+#define NV91C0_SET_FALCON21_V                                                                                31:0
+
+#define NV91C0_SET_FALCON22                                                                                0x0558
+#define NV91C0_SET_FALCON22_V                                                                                31:0
+
+#define NV91C0_SET_FALCON23                                                                                0x055c
+#define NV91C0_SET_FALCON23_V                                                                                31:0
+
+#define NV91C0_SET_FALCON24                                                                                0x0560
+#define NV91C0_SET_FALCON24_V                                                                                31:0
+
+#define NV91C0_SET_FALCON25                                                                                0x0564
+#define NV91C0_SET_FALCON25_V                                                                                31:0
+
+#define NV91C0_SET_FALCON26                                                                                0x0568
+#define NV91C0_SET_FALCON26_V                                                                                31:0
+
+#define NV91C0_SET_FALCON27                                                                                0x056c
+#define NV91C0_SET_FALCON27_V                                                                                31:0
+
+#define NV91C0_SET_FALCON28                                                                                0x0570
+#define NV91C0_SET_FALCON28_V                                                                                31:0
+
+#define NV91C0_SET_FALCON29                                                                                0x0574
+#define NV91C0_SET_FALCON29_V                                                                                31:0
+
+#define NV91C0_SET_FALCON30                                                                                0x0578
+#define NV91C0_SET_FALCON30_V                                                                                31:0
+
+#define NV91C0_SET_FALCON31                                                                                0x057c
+#define NV91C0_SET_FALCON31_V                                                                                31:0
+
+#define NV91C0_SET_MAX_SM_COUNT                                                                            0x0758
+#define NV91C0_SET_MAX_SM_COUNT_V                                                                             8:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NV91C0_SET_GRID_PARAM                                                                              0x0780
+#define NV91C0_SET_GRID_PARAM_V                                                                              31:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_C                                                                   0x0798
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER                                                           5:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_D                                                                   0x079c
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER                                                          31:0
+
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_E                                                                   0x07a0
+#define NV91C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP                                               25:0
+
+#define NV91C0_END_GRID                                                                                    0x0a04
+#define NV91C0_END_GRID_V                                                                                     0:0
+
+#define NV91C0_SET_LAUNCH_SIZE                                                                             0x0a08
+#define NV91C0_SET_LAUNCH_SIZE_V                                                                             31:0
+
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT                                                                  0x0d64
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA                                                                 3:0
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0                                                       0x00000000
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1                                                       0x00000001
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2                                                       0x00000002
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4                                                       0x00000003
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8                                                       0x00000004
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16                                                      0x00000005
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32                                                      0x00000006
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64                                                      0x00000007
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128                                                     0x00000008
+#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK                                                 0x0000000F
+
+#define NV91C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NV91C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NV91C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NV91C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NV91C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NV91C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NV91C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NV91C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT                                                                  0x1004
+#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE                                                              0:0
+#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE                                                 0x00000000
+#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE                                                  0x00000001
+
+#define NV91C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NV91C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NV91C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NV91C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NV91C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NV91C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NV91C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NV91C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NV91C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NV91C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NV91C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NV91C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NV91C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NV91C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NV91C0_UNBIND_ALL                                                                                  0x10f4
+#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS                                                                     0:0
+#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE                                                        0x00000000
+#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE                                                         0x00000001
+#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS                                                                    4:4
+#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE                                                       0x00000000
+#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE                                                        0x00000001
+#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS                                                                    8:8
+#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE                                                       0x00000000
+#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE                                                        0x00000001
+
+#define NV91C0_SET_SAMPLER_BINDING                                                                         0x1234
+#define NV91C0_SET_SAMPLER_BINDING_V                                                                          0:0
+#define NV91C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY                                                     0x00000000
+#define NV91C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING                                                0x00000001
+
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NV91C0_SET_SHADER_SCHEDULING                                                                       0x12ac
+#define NV91C0_SET_SHADER_SCHEDULING_MODE                                                                     0:0
+#define NV91C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST                                          0x00000000
+#define NV91C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN                                                  0x00000001
+
+#define NV91C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS                                                           2:1
+#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY                                            0x00000000
+
+#define NV91C0_SET_GLOBAL_COLOR_KEY                                                                        0x1354
+#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE                                                                    0:0
+#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE                                                       0x00000000
+#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE                                                        0x00000001
+
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NV91C0_PERFMON_TRANSFER                                                                            0x1524
+#define NV91C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NV91C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NV91C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NV91C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NV91C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NV91C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NV91C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NV91C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NV91C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NV91C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NV91C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NV91C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NV91C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NV91C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NV91C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NV91C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NV91C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NV91C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NV91C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NV91C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NV91C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NV91C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NV91C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NV91C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NV91C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
+
+#define NV91C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NV91C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING                                                            0x1664
+#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE                                                          1:0
+#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP                                          0x00000000
+#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP                                     0x00000001
+#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM                                    0x00000002
+#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM                                   0x00000003
+
+#define NV91C0_SET_SHADER_CONTROL                                                                          0x1690
+#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
+#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
+#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
+#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO                                               16:16
+#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE                                    0x00000000
+#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE                                     0x00000001
+#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR                                                           1:1
+#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY                                             0x00000000
+#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE                                    0x00000001
+#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR                                                       2:2
+#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO                                      0x00000000
+#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE                                0x00000001
+
+#define NV91C0_BIND_CONSTANT_BUFFER                                                                        0x1694
+#define NV91C0_BIND_CONSTANT_BUFFER_VALID                                                                     0:0
+#define NV91C0_BIND_CONSTANT_BUFFER_VALID_FALSE                                                        0x00000000
+#define NV91C0_BIND_CONSTANT_BUFFER_VALID_TRUE                                                         0x00000001
+#define NV91C0_BIND_CONSTANT_BUFFER_SHADER_SLOT                                                              12:8
+
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM                                                        8:8
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE                                           0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE                                            0x00000001
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE                                                            0x1930
+#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2                                                       0:0
+#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE                                          0x00000000
+#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE                                           0x00000001
+
+#define NV91C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NV91C0_PIPE_NOP                                                                                    0x1a2c
+#define NV91C0_PIPE_NOP_V                                                                                    31:0
+
+#define NV91C0_SET_SPARE00                                                                                 0x1a30
+#define NV91C0_SET_SPARE00_V                                                                                 31:0
+
+#define NV91C0_SET_SPARE01                                                                                 0x1a34
+#define NV91C0_SET_SPARE01_V                                                                                 31:0
+
+#define NV91C0_SET_SPARE02                                                                                 0x1a38
+#define NV91C0_SET_SPARE02_V                                                                                 31:0
+
+#define NV91C0_SET_SPARE03                                                                                 0x1a3c
+#define NV91C0_SET_SPARE03_V                                                                                 31:0
+
+#define NV91C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NV91C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NV91C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NV91C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NV91C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NV91C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NV91C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+
+#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A                                                              0x2380
+#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE                                                           16:0
+
+#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B                                                              0x2384
+#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER                                                   7:0
+
+#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C                                                              0x2388
+#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER                                                  31:0
+
+#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET                                                                 0x238c
+#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET_V                                                                 15:0
+
+#define NV91C0_LOAD_CONSTANT_BUFFER(i)                                                             (0x2390+(i)*4)
+#define NV91C0_LOAD_CONSTANT_BUFFER_V                                                                        31:0
+
+#define NV91C0_SET_SU_LD_ST_TARGET_A(j)                                                           (0x2700+(j)*32)
+#define NV91C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER                                                             7:0
+
+#define NV91C0_SET_SU_LD_ST_TARGET_B(j)                                                           (0x2704+(j)*32)
+#define NV91C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER                                                            31:0
+
+#define NV91C0_SET_SU_LD_ST_TARGET_C(j)                                                           (0x2708+(j)*32)
+#define NV91C0_SET_SU_LD_ST_TARGET_C_WIDTH                                                                   31:0
+
+#define NV91C0_SET_SU_LD_ST_TARGET_D(j)                                                           (0x270c+(j)*32)
+#define NV91C0_SET_SU_LD_ST_TARGET_D_HEIGHT                                                                  16:0
+#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY                                                       20:20
+#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR                                      0x00000000
+#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH                                            0x00000001
+
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT(j)                                                      (0x2710+(j)*32)
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE                                                                0:0
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR                                                   0x00000000
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA                                                    0x00000001
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR                                                              11:4
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED                                               0x00000000
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32                                    0x000000C0
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32                                    0x000000C1
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32                                    0x000000C2
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32                                     0x000000C3
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32                                     0x000000C4
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32                                     0x000000C5
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16                                        0x000000C6
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16                                    0x000000C7
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16                                    0x000000C8
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16                                    0x000000C9
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16                                    0x000000CA
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32                                              0x000000CB
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32                                              0x000000CC
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32                                              0x000000CD
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16                                     0x000000CE
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8                                               0x000000CF
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8                                            0x000000D0
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10                                            0x000000D1
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10                                        0x000000D2
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8                                               0x000000D5
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8                                            0x000000D6
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8                                           0x000000D7
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8                                           0x000000D8
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8                                           0x000000D9
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16                                                0x000000DA
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16                                              0x000000DB
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16                                              0x000000DC
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16                                              0x000000DD
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16                                              0x000000DE
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10                                            0x000000DF
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11                                           0x000000E0
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32                                                   0x000000E3
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32                                                   0x000000E4
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32                                                   0x000000E5
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8                                               0x000000E6
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8                                            0x000000E7
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5                                                 0x000000E8
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5                                               0x000000E9
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8                                                   0x000000EA
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8                                                 0x000000EB
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8                                                 0x000000EC
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8                                                 0x000000ED
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16                                                    0x000000EE
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16                                                   0x000000EF
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16                                                   0x000000F0
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16                                                   0x000000F1
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16                                                   0x000000F2
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8                                                     0x000000F3
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8                                                    0x000000F4
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8                                                    0x000000F5
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8                                                    0x000000F6
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8                                                     0x000000F7
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5                                               0x000000F8
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8                                               0x000000F9
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8                                            0x000000FA
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5                                               0x000000FB
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5                                               0x000000FC
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8                                               0x000000FD
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8                                               0x000000FE
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32                                                    0x000000FF
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16                                                    0x00000040
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16                                                   0x00000041
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32                                                   0x00000042
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8                                                   0x00000043
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16                                                0x00000044
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16                                              0x00000045
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32                                              0x00000046
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_B8G8R8A8                                               0x00000047
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA                                                              16:12
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16                                                     0x00000013
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8                                                   0x00000014
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24                                                   0x00000015
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24                                                   0x00000016
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24                                                   0x00000018
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32                                                    0x0000000A
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8                                              0x00000019
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8                                           0x0000001D
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8                                            0x0000001E
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8                                            0x0000001F
+#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT                                                        25:17
+
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j)                                                  (0x2714+(j)*32)
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH                                                           3:0
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB                                            0x00000000
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT                                                          7:4
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB                                           0x00000000
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS                                          0x00000001
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                         0x00000002
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                        0x00000003
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                      0x00000004
+#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                    0x00000005
+
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                2:0
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           6:4
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                               10:8
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                         14:12
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              18:16
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         22:20
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              26:24
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         30:28
+
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NV91C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NV91C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#define NV91C0_CALL_MME_MACRO(j)                                                                   (0x3800+(j)*8)
+#define NV91C0_CALL_MME_MACRO_V                                                                              31:0
+
+#define NV91C0_CALL_MME_DATA(j)                                                                    (0x3804+(j)*8)
+#define NV91C0_CALL_MME_DATA_V                                                                               31:0
+
+#endif /* _cl_fermi_compute_b_h_ */
diff --git a/classes/compute/cla0c0.h b/classes/compute/cla0c0.h
new file mode 100644
index 0000000..e8677ad
--- /dev/null
+++ b/classes/compute/cla0c0.h
@@ -0,0 +1,836 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_kepler_compute_a_h_
+#define _cl_kepler_compute_a_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../class/bin/sw_header.pl kepler_compute_a */
+
+#include "nvtypes.h"
+
+#define KEPLER_COMPUTE_A    0xA0C0
+
+typedef volatile struct _cla0c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 Reserved_0x148[0x2];
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 Reserved_0x1E8[0x2];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 Reserved_0x200[0x4];
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 Reserved_0x218[0x1];
+    NvU32 InvalidateShaderCaches;
+    NvU32 Reserved_0x220[0x8];
+    NvU32 SetCwdControl;
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 Reserved_0x24C[0xA];
+    NvU32 InvalidateConstantBufferCacheA;
+    NvU32 InvalidateConstantBufferCacheB;
+    NvU32 InvalidateConstantBufferCacheC;
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 Reserved_0x28C[0x1];
+    NvU32 CheckQmdVersion;
+    NvU32 Reserved_0x294[0x7];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x9];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 SetShaderLocalMemoryThrottledA;
+    NvU32 SetShaderLocalMemoryThrottledB;
+    NvU32 SetShaderLocalMemoryThrottledC;
+    NvU32 Reserved_0x2FC[0x5];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x7B];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x7F];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 Reserved_0x780[0x4];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x17F];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x3B];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x86];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x29];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x20];
+    NvU32 SetShaderControl;
+    NvU32 Reserved_0x1694[0x1];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BE];
+    NvU32 SetBindlessTexture;
+    NvU32 SetTrapHandler;
+    NvU32 Reserved_0x2610[0x353];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 Reserved_0x33E0[0x8];
+    NvU32 SetMmeShadowScratch[0x8];
+} kepler_compute_a_t;
+
+
+#define NVA0C0_SET_OBJECT                                                                                  0x0000
+#define NVA0C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVA0C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVA0C0_NO_OPERATION                                                                                0x0100
+#define NVA0C0_NO_OPERATION_V                                                                                31:0
+
+#define NVA0C0_SET_NOTIFY_A                                                                                0x0104
+#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVA0C0_SET_NOTIFY_B                                                                                0x0108
+#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVA0C0_NOTIFY                                                                                      0x010c
+#define NVA0C0_NOTIFY_TYPE                                                                                   31:0
+#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVA0C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVA0C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVA0C0_SEND_GO_IDLE                                                                                0x013c
+#define NVA0C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVA0C0_PM_TRIGGER                                                                                  0x0140
+#define NVA0C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVA0C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVA0C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVA0C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVA0C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVA0C0_LINE_COUNT                                                                                  0x0184
+#define NVA0C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVA0C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVA0C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
+
+#define NVA0C0_OFFSET_OUT                                                                                  0x018c
+#define NVA0C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVA0C0_PITCH_OUT                                                                                   0x0190
+#define NVA0C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVA0C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVA0C0_SET_DST_WIDTH                                                                               0x0198
+#define NVA0C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVA0C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVA0C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVA0C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVA0C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVA0C0_SET_DST_LAYER                                                                               0x01a4
+#define NVA0C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVA0C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
+
+#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
+
+#define NVA0C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVA0C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVA0C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVA0C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVA0C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVA0C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVA0C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVA0C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVA0C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVA0C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVA0C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVA0C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVA0C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVA0C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVA0C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVA0C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NVA0C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVA0C0_SET_CWD_CONTROL                                                                             0x0240
+#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
+#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
+#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
+
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVA0C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVA0C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVA0C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
+
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
+
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
+#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
+
+#define NVA0C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVA0C0_SET_QMD_VERSION                                                                             0x0288
+#define NVA0C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVA0C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVA0C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVA0C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVA0C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVA0C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVA0C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVA0C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVA0C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVA0C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
+
+#define NVA0C0_SET_SPA_VERSION                                                                             0x0310
+#define NVA0C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVA0C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVA0C0_SET_FALCON00                                                                                0x0500
+#define NVA0C0_SET_FALCON00_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON01                                                                                0x0504
+#define NVA0C0_SET_FALCON01_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON02                                                                                0x0508
+#define NVA0C0_SET_FALCON02_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON03                                                                                0x050c
+#define NVA0C0_SET_FALCON03_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON04                                                                                0x0510
+#define NVA0C0_SET_FALCON04_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON05                                                                                0x0514
+#define NVA0C0_SET_FALCON05_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON06                                                                                0x0518
+#define NVA0C0_SET_FALCON06_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON07                                                                                0x051c
+#define NVA0C0_SET_FALCON07_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON08                                                                                0x0520
+#define NVA0C0_SET_FALCON08_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON09                                                                                0x0524
+#define NVA0C0_SET_FALCON09_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON10                                                                                0x0528
+#define NVA0C0_SET_FALCON10_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON11                                                                                0x052c
+#define NVA0C0_SET_FALCON11_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON12                                                                                0x0530
+#define NVA0C0_SET_FALCON12_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON13                                                                                0x0534
+#define NVA0C0_SET_FALCON13_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON14                                                                                0x0538
+#define NVA0C0_SET_FALCON14_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON15                                                                                0x053c
+#define NVA0C0_SET_FALCON15_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON16                                                                                0x0540
+#define NVA0C0_SET_FALCON16_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON17                                                                                0x0544
+#define NVA0C0_SET_FALCON17_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON18                                                                                0x0548
+#define NVA0C0_SET_FALCON18_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON19                                                                                0x054c
+#define NVA0C0_SET_FALCON19_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON20                                                                                0x0550
+#define NVA0C0_SET_FALCON20_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON21                                                                                0x0554
+#define NVA0C0_SET_FALCON21_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON22                                                                                0x0558
+#define NVA0C0_SET_FALCON22_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON23                                                                                0x055c
+#define NVA0C0_SET_FALCON23_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON24                                                                                0x0560
+#define NVA0C0_SET_FALCON24_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON25                                                                                0x0564
+#define NVA0C0_SET_FALCON25_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON26                                                                                0x0568
+#define NVA0C0_SET_FALCON26_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON27                                                                                0x056c
+#define NVA0C0_SET_FALCON27_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON28                                                                                0x0570
+#define NVA0C0_SET_FALCON28_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON29                                                                                0x0574
+#define NVA0C0_SET_FALCON29_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON30                                                                                0x0578
+#define NVA0C0_SET_FALCON30_V                                                                                31:0
+
+#define NVA0C0_SET_FALCON31                                                                                0x057c
+#define NVA0C0_SET_FALCON31_V                                                                                31:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
+
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVA0C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVA0C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVA0C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NVA0C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NVA0C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NVA0C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NVA0C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NVA0C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NVA0C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NVA0C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NVA0C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NVA0C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NVA0C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NVA0C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NVA0C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NVA0C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NVA0C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NVA0C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NVA0C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NVA0C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVA0C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVA0C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVA0C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVA0C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVA0C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVA0C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NVA0C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVA0C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVA0C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NVA0C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVA0C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVA0C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
+
+#define NVA0C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NVA0C0_SET_SHADER_CONTROL                                                                          0x1690
+#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
+#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
+#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
+
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVA0C0_PIPE_NOP                                                                                    0x1a2c
+#define NVA0C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVA0C0_SET_SPARE00                                                                                 0x1a30
+#define NVA0C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVA0C0_SET_SPARE01                                                                                 0x1a34
+#define NVA0C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVA0C0_SET_SPARE02                                                                                 0x1a38
+#define NVA0C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVA0C0_SET_SPARE03                                                                                 0x1a3c
+#define NVA0C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVA0C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVA0C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVA0C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVA0C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+
+#define NVA0C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVA0C0_SET_TRAP_HANDLER                                                                            0x260c
+#define NVA0C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
+
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVA0C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVA0C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_kepler_compute_a_h_ */
diff --git a/classes/compute/cla1c0.h b/classes/compute/cla1c0.h
new file mode 100644
index 0000000..37462b1
--- /dev/null
+++ b/classes/compute/cla1c0.h
@@ -0,0 +1,866 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_kepler_compute_b_h_
+#define _cl_kepler_compute_b_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../class/bin/sw_header.pl kepler_compute_b */
+
+#include "nvtypes.h"
+
+#define KEPLER_COMPUTE_B    0xA1C0
+
+typedef volatile struct _cla1c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 Reserved_0x148[0x2];
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 Reserved_0x1E8[0x2];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 SetValidSpanOverflowAreaA;
+    NvU32 SetValidSpanOverflowAreaB;
+    NvU32 SetValidSpanOverflowAreaC;
+    NvU32 SetCoalesceWaitingPeriodUnit;
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 Reserved_0x218[0x1];
+    NvU32 InvalidateShaderCaches;
+    NvU32 Reserved_0x220[0x8];
+    NvU32 SetCwdControl;
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 Reserved_0x24C[0xA];
+    NvU32 InvalidateConstantBufferCacheA;
+    NvU32 InvalidateConstantBufferCacheB;
+    NvU32 InvalidateConstantBufferCacheC;
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 Reserved_0x28C[0x1];
+    NvU32 CheckQmdVersion;
+    NvU32 Reserved_0x294[0x7];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x1];
+    NvU32 SetGlobalLoadViaTexture;
+    NvU32 Reserved_0x2C8[0x7];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 SetShaderLocalMemoryThrottledA;
+    NvU32 SetShaderLocalMemoryThrottledB;
+    NvU32 SetShaderLocalMemoryThrottledC;
+    NvU32 Reserved_0x2FC[0x5];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x7B];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x7F];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 Reserved_0x780[0x4];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x17F];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x3B];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x86];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x7];
+    NvU32 ActivatePerfSettingsForComputeContext;
+    NvU32 Reserved_0x12AC[0x21];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x20];
+    NvU32 SetShaderControl;
+    NvU32 Reserved_0x1694[0x1];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BE];
+    NvU32 SetBindlessTexture;
+    NvU32 SetTrapHandler;
+    NvU32 Reserved_0x2610[0x353];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 Reserved_0x33E0[0x8];
+    NvU32 SetMmeShadowScratch[0x8];
+} kepler_compute_b_t;
+
+
+#define NVA1C0_SET_OBJECT                                                                                  0x0000
+#define NVA1C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVA1C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVA1C0_NO_OPERATION                                                                                0x0100
+#define NVA1C0_NO_OPERATION_V                                                                                31:0
+
+#define NVA1C0_SET_NOTIFY_A                                                                                0x0104
+#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVA1C0_SET_NOTIFY_B                                                                                0x0108
+#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVA1C0_NOTIFY                                                                                      0x010c
+#define NVA1C0_NOTIFY_TYPE                                                                                   31:0
+#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVA1C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVA1C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVA1C0_SEND_GO_IDLE                                                                                0x013c
+#define NVA1C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVA1C0_PM_TRIGGER                                                                                  0x0140
+#define NVA1C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVA1C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVA1C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVA1C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVA1C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVA1C0_LINE_COUNT                                                                                  0x0184
+#define NVA1C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVA1C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVA1C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
+
+#define NVA1C0_OFFSET_OUT                                                                                  0x018c
+#define NVA1C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVA1C0_PITCH_OUT                                                                                   0x0190
+#define NVA1C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVA1C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVA1C0_SET_DST_WIDTH                                                                               0x0198
+#define NVA1C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVA1C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVA1C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVA1C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVA1C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVA1C0_SET_DST_LAYER                                                                               0x01a4
+#define NVA1C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVA1C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
+
+#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
+
+#define NVA1C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVA1C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVA1C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVA1C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVA1C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVA1C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVA1C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVA1C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVA1C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVA1C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVA1C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVA1C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVA1C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVA1C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
+#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
+
+#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
+#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
+
+#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
+#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
+
+#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
+#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
+
+#define NVA1C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVA1C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NVA1C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVA1C0_SET_CWD_CONTROL                                                                             0x0240
+#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
+#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
+#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
+
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVA1C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVA1C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVA1C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
+
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
+
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
+#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
+
+#define NVA1C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVA1C0_SET_QMD_VERSION                                                                             0x0288
+#define NVA1C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVA1C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVA1C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVA1C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVA1C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVA1C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVA1C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVA1C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVA1C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVA1C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE                                                                 0x02c4
+#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE                                                             0:0
+#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE                                                0x00000000
+#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE                                                 0x00000001
+#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX                                                      23:4
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
+
+#define NVA1C0_SET_SPA_VERSION                                                                             0x0310
+#define NVA1C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVA1C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVA1C0_SET_FALCON00                                                                                0x0500
+#define NVA1C0_SET_FALCON00_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON01                                                                                0x0504
+#define NVA1C0_SET_FALCON01_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON02                                                                                0x0508
+#define NVA1C0_SET_FALCON02_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON03                                                                                0x050c
+#define NVA1C0_SET_FALCON03_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON04                                                                                0x0510
+#define NVA1C0_SET_FALCON04_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON05                                                                                0x0514
+#define NVA1C0_SET_FALCON05_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON06                                                                                0x0518
+#define NVA1C0_SET_FALCON06_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON07                                                                                0x051c
+#define NVA1C0_SET_FALCON07_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON08                                                                                0x0520
+#define NVA1C0_SET_FALCON08_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON09                                                                                0x0524
+#define NVA1C0_SET_FALCON09_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON10                                                                                0x0528
+#define NVA1C0_SET_FALCON10_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON11                                                                                0x052c
+#define NVA1C0_SET_FALCON11_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON12                                                                                0x0530
+#define NVA1C0_SET_FALCON12_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON13                                                                                0x0534
+#define NVA1C0_SET_FALCON13_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON14                                                                                0x0538
+#define NVA1C0_SET_FALCON14_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON15                                                                                0x053c
+#define NVA1C0_SET_FALCON15_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON16                                                                                0x0540
+#define NVA1C0_SET_FALCON16_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON17                                                                                0x0544
+#define NVA1C0_SET_FALCON17_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON18                                                                                0x0548
+#define NVA1C0_SET_FALCON18_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON19                                                                                0x054c
+#define NVA1C0_SET_FALCON19_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON20                                                                                0x0550
+#define NVA1C0_SET_FALCON20_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON21                                                                                0x0554
+#define NVA1C0_SET_FALCON21_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON22                                                                                0x0558
+#define NVA1C0_SET_FALCON22_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON23                                                                                0x055c
+#define NVA1C0_SET_FALCON23_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON24                                                                                0x0560
+#define NVA1C0_SET_FALCON24_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON25                                                                                0x0564
+#define NVA1C0_SET_FALCON25_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON26                                                                                0x0568
+#define NVA1C0_SET_FALCON26_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON27                                                                                0x056c
+#define NVA1C0_SET_FALCON27_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON28                                                                                0x0570
+#define NVA1C0_SET_FALCON28_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON29                                                                                0x0574
+#define NVA1C0_SET_FALCON29_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON30                                                                                0x0578
+#define NVA1C0_SET_FALCON30_V                                                                                31:0
+
+#define NVA1C0_SET_FALCON31                                                                                0x057c
+#define NVA1C0_SET_FALCON31_V                                                                                31:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
+
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVA1C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVA1C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVA1C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NVA1C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NVA1C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NVA1C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NVA1C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NVA1C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NVA1C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NVA1C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NVA1C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NVA1C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NVA1C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NVA1C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NVA1C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NVA1C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NVA1C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NVA1C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NVA1C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NVA1C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
+#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
+#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
+#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
+
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVA1C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVA1C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVA1C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVA1C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVA1C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVA1C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NVA1C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVA1C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVA1C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NVA1C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVA1C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVA1C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
+
+#define NVA1C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NVA1C0_SET_SHADER_CONTROL                                                                          0x1690
+#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL                                                             0:0
+#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO                                                 0x00000000
+#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY                                             0x00000001
+
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVA1C0_PIPE_NOP                                                                                    0x1a2c
+#define NVA1C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVA1C0_SET_SPARE00                                                                                 0x1a30
+#define NVA1C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVA1C0_SET_SPARE01                                                                                 0x1a34
+#define NVA1C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVA1C0_SET_SPARE02                                                                                 0x1a38
+#define NVA1C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVA1C0_SET_SPARE03                                                                                 0x1a3c
+#define NVA1C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVA1C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVA1C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVA1C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVA1C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+
+#define NVA1C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVA1C0_SET_TRAP_HANDLER                                                                            0x260c
+#define NVA1C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
+
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVA1C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVA1C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_kepler_compute_b_h_ */
diff --git a/classes/compute/clb0c0.h b/classes/compute/clb0c0.h
new file mode 100644
index 0000000..7f63b4a
--- /dev/null
+++ b/classes/compute/clb0c0.h
@@ -0,0 +1,931 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_maxwell_compute_a_h_
+#define _cl_maxwell_compute_a_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */
+
+#include "nvtypes.h"
+
+#define MAXWELL_COMPUTE_A    0xB0C0
+
+typedef volatile struct _clb0c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 Reserved_0x148[0x2];
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 Reserved_0x1E8[0x2];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 SetValidSpanOverflowAreaA;
+    NvU32 SetValidSpanOverflowAreaB;
+    NvU32 SetValidSpanOverflowAreaC;
+    NvU32 SetCoalesceWaitingPeriodUnit;
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 SetSelectMaxwellTextureHeaders;
+    NvU32 InvalidateShaderCaches;
+    NvU32 SetReservedSwMethod00;
+    NvU32 SetReservedSwMethod01;
+    NvU32 SetReservedSwMethod02;
+    NvU32 SetReservedSwMethod03;
+    NvU32 SetReservedSwMethod04;
+    NvU32 SetReservedSwMethod05;
+    NvU32 SetReservedSwMethod06;
+    NvU32 SetReservedSwMethod07;
+    NvU32 SetCwdControl;
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 SetReservedSwMethod08;
+    NvU32 SetReservedSwMethod09;
+    NvU32 SetReservedSwMethod10;
+    NvU32 SetReservedSwMethod11;
+    NvU32 SetReservedSwMethod12;
+    NvU32 SetReservedSwMethod13;
+    NvU32 SetReservedSwMethod14;
+    NvU32 SetReservedSwMethod15;
+    NvU32 Reserved_0x26C[0x2];
+    NvU32 InvalidateConstantBufferCacheA;
+    NvU32 InvalidateConstantBufferCacheB;
+    NvU32 InvalidateConstantBufferCacheC;
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 Reserved_0x28C[0x1];
+    NvU32 CheckQmdVersion;
+    NvU32 Reserved_0x294[0x7];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x9];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 SetShaderLocalMemoryThrottledA;
+    NvU32 SetShaderLocalMemoryThrottledB;
+    NvU32 SetShaderLocalMemoryThrottledC;
+    NvU32 Reserved_0x2FC[0x5];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x7B];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x7F];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 Reserved_0x780[0x4];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x17F];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x3B];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x86];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x7];
+    NvU32 ActivatePerfSettingsForComputeContext;
+    NvU32 Reserved_0x12AC[0x21];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x22];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BE];
+    NvU32 SetBindlessTexture;
+    NvU32 SetTrapHandler;
+    NvU32 Reserved_0x2610[0x34B];
+    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 StartShaderPerformanceCounter;
+    NvU32 StopShaderPerformanceCounter;
+    NvU32 Reserved_0x33E8[0x6];
+    NvU32 SetMmeShadowScratch[0x8];
+} maxwell_compute_a_t;
+
+
+#define NVB0C0_SET_OBJECT                                                                                  0x0000
+#define NVB0C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVB0C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVB0C0_NO_OPERATION                                                                                0x0100
+#define NVB0C0_NO_OPERATION_V                                                                                31:0
+
+#define NVB0C0_SET_NOTIFY_A                                                                                0x0104
+#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVB0C0_SET_NOTIFY_B                                                                                0x0108
+#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVB0C0_NOTIFY                                                                                      0x010c
+#define NVB0C0_NOTIFY_TYPE                                                                                   31:0
+#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVB0C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVB0C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVB0C0_SEND_GO_IDLE                                                                                0x013c
+#define NVB0C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVB0C0_PM_TRIGGER                                                                                  0x0140
+#define NVB0C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVB0C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVB0C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVB0C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVB0C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVB0C0_LINE_COUNT                                                                                  0x0184
+#define NVB0C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVB0C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVB0C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
+
+#define NVB0C0_OFFSET_OUT                                                                                  0x018c
+#define NVB0C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVB0C0_PITCH_OUT                                                                                   0x0190
+#define NVB0C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVB0C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVB0C0_SET_DST_WIDTH                                                                               0x0198
+#define NVB0C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVB0C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVB0C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVB0C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVB0C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVB0C0_SET_DST_LAYER                                                                               0x01a4
+#define NVB0C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVB0C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
+
+#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
+
+#define NVB0C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVB0C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVB0C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVB0C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVB0C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVB0C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVB0C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVB0C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVB0C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVB0C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVB0C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVB0C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVB0C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVB0C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
+#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
+
+#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
+#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
+
+#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
+#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
+
+#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
+#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
+
+#define NVB0C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVB0C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
+#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
+#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
+#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
+
+#define NVB0C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVB0C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
+#define NVB0C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
+#define NVB0C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
+#define NVB0C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
+#define NVB0C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
+#define NVB0C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
+#define NVB0C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
+#define NVB0C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
+#define NVB0C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
+
+#define NVB0C0_SET_CWD_CONTROL                                                                             0x0240
+#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
+#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
+#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
+
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVB0C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVB0C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVB0C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVB0C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
+#define NVB0C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
+#define NVB0C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
+#define NVB0C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
+#define NVB0C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
+#define NVB0C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
+#define NVB0C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
+#define NVB0C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
+
+#define NVB0C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
+#define NVB0C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
+
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
+
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
+
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
+#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
+
+#define NVB0C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVB0C0_SET_QMD_VERSION                                                                             0x0288
+#define NVB0C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVB0C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVB0C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVB0C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVB0C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVB0C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVB0C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVB0C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVB0C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVB0C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
+
+#define NVB0C0_SET_SPA_VERSION                                                                             0x0310
+#define NVB0C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVB0C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVB0C0_SET_FALCON00                                                                                0x0500
+#define NVB0C0_SET_FALCON00_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON01                                                                                0x0504
+#define NVB0C0_SET_FALCON01_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON02                                                                                0x0508
+#define NVB0C0_SET_FALCON02_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON03                                                                                0x050c
+#define NVB0C0_SET_FALCON03_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON04                                                                                0x0510
+#define NVB0C0_SET_FALCON04_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON05                                                                                0x0514
+#define NVB0C0_SET_FALCON05_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON06                                                                                0x0518
+#define NVB0C0_SET_FALCON06_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON07                                                                                0x051c
+#define NVB0C0_SET_FALCON07_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON08                                                                                0x0520
+#define NVB0C0_SET_FALCON08_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON09                                                                                0x0524
+#define NVB0C0_SET_FALCON09_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON10                                                                                0x0528
+#define NVB0C0_SET_FALCON10_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON11                                                                                0x052c
+#define NVB0C0_SET_FALCON11_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON12                                                                                0x0530
+#define NVB0C0_SET_FALCON12_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON13                                                                                0x0534
+#define NVB0C0_SET_FALCON13_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON14                                                                                0x0538
+#define NVB0C0_SET_FALCON14_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON15                                                                                0x053c
+#define NVB0C0_SET_FALCON15_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON16                                                                                0x0540
+#define NVB0C0_SET_FALCON16_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON17                                                                                0x0544
+#define NVB0C0_SET_FALCON17_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON18                                                                                0x0548
+#define NVB0C0_SET_FALCON18_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON19                                                                                0x054c
+#define NVB0C0_SET_FALCON19_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON20                                                                                0x0550
+#define NVB0C0_SET_FALCON20_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON21                                                                                0x0554
+#define NVB0C0_SET_FALCON21_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON22                                                                                0x0558
+#define NVB0C0_SET_FALCON22_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON23                                                                                0x055c
+#define NVB0C0_SET_FALCON23_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON24                                                                                0x0560
+#define NVB0C0_SET_FALCON24_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON25                                                                                0x0564
+#define NVB0C0_SET_FALCON25_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON26                                                                                0x0568
+#define NVB0C0_SET_FALCON26_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON27                                                                                0x056c
+#define NVB0C0_SET_FALCON27_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON28                                                                                0x0570
+#define NVB0C0_SET_FALCON28_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON29                                                                                0x0574
+#define NVB0C0_SET_FALCON29_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON30                                                                                0x0578
+#define NVB0C0_SET_FALCON30_V                                                                                31:0
+
+#define NVB0C0_SET_FALCON31                                                                                0x057c
+#define NVB0C0_SET_FALCON31_V                                                                                31:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
+
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVB0C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVB0C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVB0C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NVB0C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NVB0C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NVB0C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NVB0C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NVB0C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NVB0C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NVB0C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NVB0C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NVB0C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NVB0C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NVB0C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NVB0C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NVB0C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NVB0C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NVB0C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NVB0C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NVB0C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
+#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
+#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
+#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
+
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVB0C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVB0C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVB0C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVB0C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVB0C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVB0C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NVB0C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVB0C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVB0C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NVB0C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVB0C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVB0C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
+
+#define NVB0C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVB0C0_PIPE_NOP                                                                                    0x1a2c
+#define NVB0C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVB0C0_SET_SPARE00                                                                                 0x1a30
+#define NVB0C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVB0C0_SET_SPARE01                                                                                 0x1a34
+#define NVB0C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVB0C0_SET_SPARE02                                                                                 0x1a38
+#define NVB0C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVB0C0_SET_SPARE03                                                                                 0x1a3c
+#define NVB0C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVB0C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVB0C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVB0C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVB0C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+
+#define NVB0C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVB0C0_SET_TRAP_HANDLER                                                                            0x260c
+#define NVB0C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
+
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
+
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
+#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
+
+#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
+#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
+
+#define NVB0C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVB0C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_maxwell_compute_a_h_ */
diff --git a/classes/compute/clb1c0.h b/classes/compute/clb1c0.h
new file mode 100644
index 0000000..ba5519d
--- /dev/null
+++ b/classes/compute/clb1c0.h
@@ -0,0 +1,968 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_maxwell_compute_b_h_
+#define _cl_maxwell_compute_b_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */
+
+#include "nvtypes.h"
+
+#define MAXWELL_COMPUTE_B    0xB1C0
+
+typedef volatile struct _clb1c0_tag0 {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 Reserved_0x148[0x2];
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 Reserved_0x1E8[0x2];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 SetValidSpanOverflowAreaA;
+    NvU32 SetValidSpanOverflowAreaB;
+    NvU32 SetValidSpanOverflowAreaC;
+    NvU32 SetCoalesceWaitingPeriodUnit;
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 SetSelectMaxwellTextureHeaders;
+    NvU32 InvalidateShaderCaches;
+    NvU32 SetReservedSwMethod00;
+    NvU32 SetReservedSwMethod01;
+    NvU32 SetReservedSwMethod02;
+    NvU32 SetReservedSwMethod03;
+    NvU32 SetReservedSwMethod04;
+    NvU32 SetReservedSwMethod05;
+    NvU32 SetReservedSwMethod06;
+    NvU32 SetReservedSwMethod07;
+    NvU32 SetCwdControl;
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 SetReservedSwMethod08;
+    NvU32 SetReservedSwMethod09;
+    NvU32 SetReservedSwMethod10;
+    NvU32 SetReservedSwMethod11;
+    NvU32 SetReservedSwMethod12;
+    NvU32 SetReservedSwMethod13;
+    NvU32 SetReservedSwMethod14;
+    NvU32 SetReservedSwMethod15;
+    NvU32 SetGwcScgType;
+    NvU32 SetScgControl;
+    NvU32 InvalidateConstantBufferCacheA;
+    NvU32 InvalidateConstantBufferCacheB;
+    NvU32 InvalidateConstantBufferCacheC;
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 SetWfiConfig;
+    NvU32 CheckQmdVersion;
+    NvU32 WaitForIdleScgType;
+    NvU32 InvalidateSkedCaches;
+    NvU32 SetScgRenderEnableControl;
+    NvU32 Reserved_0x2A0[0x4];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x9];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 SetShaderLocalMemoryThrottledA;
+    NvU32 SetShaderLocalMemoryThrottledB;
+    NvU32 SetShaderLocalMemoryThrottledC;
+    NvU32 Reserved_0x2FC[0x5];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x7B];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x7F];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 Reserved_0x780[0x4];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x17F];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x3B];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x67];
+    NvU32 InvalidateSamplerCacheAll;
+    NvU32 InvalidateTextureHeaderCacheAll;
+    NvU32 Reserved_0x1214[0x1D];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x7];
+    NvU32 ActivatePerfSettingsForComputeContext;
+    NvU32 Reserved_0x12AC[0x21];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x22];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BE];
+    NvU32 SetBindlessTexture;
+    NvU32 SetTrapHandler;
+    NvU32 Reserved_0x2610[0x34B];
+    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 StartShaderPerformanceCounter;
+    NvU32 StopShaderPerformanceCounter;
+    NvU32 Reserved_0x33E8[0x6];
+    NvU32 SetMmeShadowScratch[0x8];
+} maxwell_compute_b_t;
+
+
+#define NVB1C0_SET_OBJECT                                                                                  0x0000
+#define NVB1C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVB1C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVB1C0_NO_OPERATION                                                                                0x0100
+#define NVB1C0_NO_OPERATION_V                                                                                31:0
+
+#define NVB1C0_SET_NOTIFY_A                                                                                0x0104
+#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVB1C0_SET_NOTIFY_B                                                                                0x0108
+#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVB1C0_NOTIFY                                                                                      0x010c
+#define NVB1C0_NOTIFY_TYPE                                                                                   31:0
+#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVB1C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVB1C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVB1C0_SEND_GO_IDLE                                                                                0x013c
+#define NVB1C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVB1C0_PM_TRIGGER                                                                                  0x0140
+#define NVB1C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVB1C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVB1C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVB1C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVB1C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVB1C0_LINE_COUNT                                                                                  0x0184
+#define NVB1C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVB1C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVB1C0_OFFSET_OUT_UPPER_VALUE                                                                         7:0
+
+#define NVB1C0_OFFSET_OUT                                                                                  0x018c
+#define NVB1C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVB1C0_PITCH_OUT                                                                                   0x0190
+#define NVB1C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVB1C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVB1C0_SET_DST_WIDTH                                                                               0x0198
+#define NVB1C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVB1C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVB1C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVB1C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVB1C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVB1C0_SET_DST_LAYER                                                                               0x01a4
+#define NVB1C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVB1C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V                                                                      19:0
+
+#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    15:0
+
+#define NVB1C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVB1C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVB1C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVB1C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVB1C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVB1C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVB1C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVB1C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVB1C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVB1C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVB1C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVB1C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVB1C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVB1C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
+#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
+
+#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
+#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
+
+#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
+#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
+
+#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
+#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
+
+#define NVB1C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVB1C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
+#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
+#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
+#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
+
+#define NVB1C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVB1C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
+#define NVB1C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
+#define NVB1C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
+#define NVB1C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
+#define NVB1C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
+#define NVB1C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
+#define NVB1C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
+#define NVB1C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
+#define NVB1C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
+
+#define NVB1C0_SET_CWD_CONTROL                                                                             0x0240
+#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
+#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
+#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
+
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVB1C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVB1C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVB1C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVB1C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
+#define NVB1C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
+#define NVB1C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
+#define NVB1C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
+#define NVB1C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
+#define NVB1C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
+#define NVB1C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
+#define NVB1C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
+
+#define NVB1C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
+#define NVB1C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
+
+#define NVB1C0_SET_GWC_SCG_TYPE                                                                            0x026c
+#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE                                                                      0:0
+#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0                                             0x00000000
+#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1                                                      0x00000001
+
+#define NVB1C0_SET_SCG_CONTROL                                                                             0x0270
+#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
+
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                               7:0
+
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
+
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
+#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
+
+#define NVB1C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVB1C0_SET_QMD_VERSION                                                                             0x0288
+#define NVB1C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVB1C0_SET_WFI_CONFIG                                                                              0x028c
+#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI                                                             0:0
+#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE                                                0x00000000
+#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE                                                 0x00000001
+
+#define NVB1C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVB1C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE                                                                      0x0294
+#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V                                                                      31:0
+
+#define NVB1C0_INVALIDATE_SKED_CACHES                                                                      0x0298
+#define NVB1C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
+
+#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL                                                               0x029c
+#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE                                      0:0
+#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE                         0x00000000
+#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE                          0x00000001
+
+#define NVB1C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVB1C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVB1C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVB1C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVB1C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVB1C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVB1C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
+
+#define NVB1C0_SET_SPA_VERSION                                                                             0x0310
+#define NVB1C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVB1C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVB1C0_SET_FALCON00                                                                                0x0500
+#define NVB1C0_SET_FALCON00_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON01                                                                                0x0504
+#define NVB1C0_SET_FALCON01_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON02                                                                                0x0508
+#define NVB1C0_SET_FALCON02_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON03                                                                                0x050c
+#define NVB1C0_SET_FALCON03_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON04                                                                                0x0510
+#define NVB1C0_SET_FALCON04_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON05                                                                                0x0514
+#define NVB1C0_SET_FALCON05_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON06                                                                                0x0518
+#define NVB1C0_SET_FALCON06_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON07                                                                                0x051c
+#define NVB1C0_SET_FALCON07_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON08                                                                                0x0520
+#define NVB1C0_SET_FALCON08_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON09                                                                                0x0524
+#define NVB1C0_SET_FALCON09_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON10                                                                                0x0528
+#define NVB1C0_SET_FALCON10_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON11                                                                                0x052c
+#define NVB1C0_SET_FALCON11_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON12                                                                                0x0530
+#define NVB1C0_SET_FALCON12_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON13                                                                                0x0534
+#define NVB1C0_SET_FALCON13_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON14                                                                                0x0538
+#define NVB1C0_SET_FALCON14_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON15                                                                                0x053c
+#define NVB1C0_SET_FALCON15_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON16                                                                                0x0540
+#define NVB1C0_SET_FALCON16_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON17                                                                                0x0544
+#define NVB1C0_SET_FALCON17_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON18                                                                                0x0548
+#define NVB1C0_SET_FALCON18_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON19                                                                                0x054c
+#define NVB1C0_SET_FALCON19_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON20                                                                                0x0550
+#define NVB1C0_SET_FALCON20_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON21                                                                                0x0554
+#define NVB1C0_SET_FALCON21_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON22                                                                                0x0558
+#define NVB1C0_SET_FALCON22_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON23                                                                                0x055c
+#define NVB1C0_SET_FALCON23_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON24                                                                                0x0560
+#define NVB1C0_SET_FALCON24_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON25                                                                                0x0564
+#define NVB1C0_SET_FALCON25_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON26                                                                                0x0568
+#define NVB1C0_SET_FALCON26_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON27                                                                                0x056c
+#define NVB1C0_SET_FALCON27_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON28                                                                                0x0570
+#define NVB1C0_SET_FALCON28_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON29                                                                                0x0574
+#define NVB1C0_SET_FALCON29_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON30                                                                                0x0578
+#define NVB1C0_SET_FALCON30_V                                                                                31:0
+
+#define NVB1C0_SET_FALCON31                                                                                0x057c
+#define NVB1C0_SET_FALCON31_V                                                                                31:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                        7:0
+
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVB1C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVB1C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVB1C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NVB1C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NVB1C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NVB1C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NVB1C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NVB1C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NVB1C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NVB1C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NVB1C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NVB1C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NVB1C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NVB1C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NVB1C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NVB1C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NVB1C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NVB1C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NVB1C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NVB1C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
+
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
+
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
+#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
+#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
+#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
+
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVB1C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVB1C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVB1C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVB1C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVB1C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVB1C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                            7:0
+
+#define NVB1C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVB1C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVB1C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                             7:0
+
+#define NVB1C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVB1C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVB1C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                             7:0
+
+#define NVB1C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVB1C0_PIPE_NOP                                                                                    0x1a2c
+#define NVB1C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVB1C0_SET_SPARE00                                                                                 0x1a30
+#define NVB1C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVB1C0_SET_SPARE01                                                                                 0x1a34
+#define NVB1C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVB1C0_SET_SPARE02                                                                                 0x1a38
+#define NVB1C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVB1C0_SET_SPARE03                                                                                 0x1a3c
+#define NVB1C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVB1C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVB1C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVB1C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVB1C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+
+#define NVB1C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVB1C0_SET_TRAP_HANDLER                                                                            0x260c
+#define NVB1C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
+
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
+
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
+#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
+
+#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
+#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
+
+#define NVB1C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVB1C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_maxwell_compute_b_h_ */
diff --git a/classes/compute/clc0c0.h b/classes/compute/clc0c0.h
new file mode 100644
index 0000000..ee090ec
--- /dev/null
+++ b/classes/compute/clc0c0.h
@@ -0,0 +1,1006 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_pascal_compute_a_h_
+#define _cl_pascal_compute_a_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */
+
+#include "nvtypes.h"
+
+#define PASCAL_COMPUTE_A    0xC0C0
+
+typedef volatile struct pascal_compute_a_struct {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 Reserved_0x148[0x2];
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 Reserved_0x1E8[0x2];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 SetValidSpanOverflowAreaA;
+    NvU32 SetValidSpanOverflowAreaB;
+    NvU32 SetValidSpanOverflowAreaC;
+    NvU32 SetCoalesceWaitingPeriodUnit;
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 SetSelectMaxwellTextureHeaders;
+    NvU32 InvalidateShaderCaches;
+    NvU32 SetReservedSwMethod00;
+    NvU32 SetReservedSwMethod01;
+    NvU32 SetReservedSwMethod02;
+    NvU32 SetReservedSwMethod03;
+    NvU32 SetReservedSwMethod04;
+    NvU32 SetReservedSwMethod05;
+    NvU32 SetReservedSwMethod06;
+    NvU32 SetReservedSwMethod07;
+    NvU32 SetCwdControl;
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 SetReservedSwMethod08;
+    NvU32 SetReservedSwMethod09;
+    NvU32 SetReservedSwMethod10;
+    NvU32 SetReservedSwMethod11;
+    NvU32 SetReservedSwMethod12;
+    NvU32 SetReservedSwMethod13;
+    NvU32 SetReservedSwMethod14;
+    NvU32 SetReservedSwMethod15;
+    NvU32 SetGwcScgType;
+    NvU32 SetScgControl;
+    NvU32 InvalidateConstantBufferCacheA;
+    NvU32 InvalidateConstantBufferCacheB;
+    NvU32 InvalidateConstantBufferCacheC;
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 SetWfiConfig;
+    NvU32 CheckQmdVersion;
+    NvU32 WaitForIdleScgType;
+    NvU32 InvalidateSkedCaches;
+    NvU32 SetScgRenderEnableControl;
+    NvU32 SetShaderSharedMemoryWindowA;
+    NvU32 SetShaderSharedMemoryWindowB;
+    NvU32 Reserved_0x2A8[0x2];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x9];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 SetShaderLocalMemoryThrottledA;
+    NvU32 SetShaderLocalMemoryThrottledB;
+    NvU32 SetShaderLocalMemoryThrottledC;
+    NvU32 Reserved_0x2FC[0x5];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x1];
+    NvU32 SetInlineQmdAddressA;
+    NvU32 SetInlineQmdAddressB;
+    NvU32 LoadInlineQmdData[0x40];
+    NvU32 Reserved_0x420[0x38];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x7F];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 Reserved_0x780[0x4];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x6];
+    NvU32 SetShaderLocalMemoryWindowA;
+    NvU32 SetShaderLocalMemoryWindowB;
+    NvU32 Reserved_0x7B8[0x177];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x3B];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x67];
+    NvU32 InvalidateSamplerCacheAll;
+    NvU32 InvalidateTextureHeaderCacheAll;
+    NvU32 Reserved_0x1214[0x1D];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x7];
+    NvU32 ActivatePerfSettingsForComputeContext;
+    NvU32 Reserved_0x12AC[0x21];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x22];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BE];
+    NvU32 SetBindlessTexture;
+    NvU32 SetTrapHandler;
+    NvU32 Reserved_0x2610[0x34B];
+    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 StartShaderPerformanceCounter;
+    NvU32 StopShaderPerformanceCounter;
+    NvU32 SetShaderPerformanceCounterSctlFilter;
+    NvU32 SetShaderPerformanceCounterCoreMioFilter;
+    NvU32 Reserved_0x33F0[0x4];
+    NvU32 SetMmeShadowScratch[0x8];
+} pascal_compute_a_t;
+
+
+#define NVC0C0_SET_OBJECT                                                                                  0x0000
+#define NVC0C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVC0C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVC0C0_NO_OPERATION                                                                                0x0100
+#define NVC0C0_NO_OPERATION_V                                                                                31:0
+
+#define NVC0C0_SET_NOTIFY_A                                                                                0x0104
+#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVC0C0_SET_NOTIFY_B                                                                                0x0108
+#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVC0C0_NOTIFY                                                                                      0x010c
+#define NVC0C0_NOTIFY_TYPE                                                                                   31:0
+#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVC0C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVC0C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVC0C0_SEND_GO_IDLE                                                                                0x013c
+#define NVC0C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVC0C0_PM_TRIGGER                                                                                  0x0140
+#define NVC0C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVC0C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVC0C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVC0C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVC0C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVC0C0_LINE_COUNT                                                                                  0x0184
+#define NVC0C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVC0C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVC0C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
+
+#define NVC0C0_OFFSET_OUT                                                                                  0x018c
+#define NVC0C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVC0C0_PITCH_OUT                                                                                   0x0190
+#define NVC0C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVC0C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVC0C0_SET_DST_WIDTH                                                                               0x0198
+#define NVC0C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVC0C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVC0C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVC0C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVC0C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVC0C0_SET_DST_LAYER                                                                               0x01a4
+#define NVC0C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVC0C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
+
+#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
+
+#define NVC0C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVC0C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVC0C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVC0C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC0C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC0C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVC0C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVC0C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVC0C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVC0C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVC0C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVC0C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVC0C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVC0C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
+#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
+
+#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
+#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
+
+#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
+#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
+
+#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
+#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
+
+#define NVC0C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVC0C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
+#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
+#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
+#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
+
+#define NVC0C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVC0C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
+#define NVC0C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
+#define NVC0C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
+#define NVC0C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
+#define NVC0C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
+#define NVC0C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
+#define NVC0C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
+#define NVC0C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
+#define NVC0C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
+
+#define NVC0C0_SET_CWD_CONTROL                                                                             0x0240
+#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
+#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
+#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
+
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVC0C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVC0C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVC0C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVC0C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
+#define NVC0C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
+#define NVC0C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
+#define NVC0C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
+#define NVC0C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
+#define NVC0C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
+#define NVC0C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
+#define NVC0C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
+
+#define NVC0C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
+#define NVC0C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
+
+#define NVC0C0_SET_GWC_SCG_TYPE                                                                            0x026c
+#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE                                                                      0:0
+#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0                                             0x00000000
+#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1                                                      0x00000001
+
+#define NVC0C0_SET_SCG_CONTROL                                                                             0x0270
+#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
+
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                              16:0
+
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
+
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
+#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
+
+#define NVC0C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVC0C0_SET_QMD_VERSION                                                                             0x0288
+#define NVC0C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVC0C0_SET_WFI_CONFIG                                                                              0x028c
+#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI                                                             0:0
+#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE                                                0x00000000
+#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE                                                 0x00000001
+
+#define NVC0C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVC0C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE                                                                      0x0294
+#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V                                                                      31:0
+
+#define NVC0C0_INVALIDATE_SKED_CACHES                                                                      0x0298
+#define NVC0C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
+
+#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL                                                               0x029c
+#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE                                      0:0
+#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE                         0x00000000
+#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE                          0x00000001
+
+#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
+#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
+
+#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
+#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
+
+#define NVC0C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVC0C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVC0C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVC0C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVC0C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVC0C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVC0C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
+
+#define NVC0C0_SET_SPA_VERSION                                                                             0x0310
+#define NVC0C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVC0C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVC0C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
+#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
+
+#define NVC0C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
+#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
+
+#define NVC0C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
+#define NVC0C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
+
+#define NVC0C0_SET_FALCON00                                                                                0x0500
+#define NVC0C0_SET_FALCON00_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON01                                                                                0x0504
+#define NVC0C0_SET_FALCON01_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON02                                                                                0x0508
+#define NVC0C0_SET_FALCON02_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON03                                                                                0x050c
+#define NVC0C0_SET_FALCON03_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON04                                                                                0x0510
+#define NVC0C0_SET_FALCON04_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON05                                                                                0x0514
+#define NVC0C0_SET_FALCON05_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON06                                                                                0x0518
+#define NVC0C0_SET_FALCON06_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON07                                                                                0x051c
+#define NVC0C0_SET_FALCON07_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON08                                                                                0x0520
+#define NVC0C0_SET_FALCON08_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON09                                                                                0x0524
+#define NVC0C0_SET_FALCON09_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON10                                                                                0x0528
+#define NVC0C0_SET_FALCON10_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON11                                                                                0x052c
+#define NVC0C0_SET_FALCON11_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON12                                                                                0x0530
+#define NVC0C0_SET_FALCON12_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON13                                                                                0x0534
+#define NVC0C0_SET_FALCON13_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON14                                                                                0x0538
+#define NVC0C0_SET_FALCON14_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON15                                                                                0x053c
+#define NVC0C0_SET_FALCON15_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON16                                                                                0x0540
+#define NVC0C0_SET_FALCON16_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON17                                                                                0x0544
+#define NVC0C0_SET_FALCON17_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON18                                                                                0x0548
+#define NVC0C0_SET_FALCON18_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON19                                                                                0x054c
+#define NVC0C0_SET_FALCON19_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON20                                                                                0x0550
+#define NVC0C0_SET_FALCON20_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON21                                                                                0x0554
+#define NVC0C0_SET_FALCON21_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON22                                                                                0x0558
+#define NVC0C0_SET_FALCON22_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON23                                                                                0x055c
+#define NVC0C0_SET_FALCON23_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON24                                                                                0x0560
+#define NVC0C0_SET_FALCON24_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON25                                                                                0x0564
+#define NVC0C0_SET_FALCON25_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON26                                                                                0x0568
+#define NVC0C0_SET_FALCON26_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON27                                                                                0x056c
+#define NVC0C0_SET_FALCON27_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON28                                                                                0x0570
+#define NVC0C0_SET_FALCON28_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON29                                                                                0x0574
+#define NVC0C0_SET_FALCON29_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON30                                                                                0x0578
+#define NVC0C0_SET_FALCON30_V                                                                                31:0
+
+#define NVC0C0_SET_FALCON31                                                                                0x057c
+#define NVC0C0_SET_FALCON31_V                                                                                31:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
+
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
+#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
+
+#define NVC0C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVC0C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVC0C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NVC0C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NVC0C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NVC0C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NVC0C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NVC0C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NVC0C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NVC0C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NVC0C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NVC0C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NVC0C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NVC0C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NVC0C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NVC0C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NVC0C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NVC0C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NVC0C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NVC0C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
+
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
+
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
+#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
+#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
+#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
+
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVC0C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVC0C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC0C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC0C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVC0C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVC0C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
+
+#define NVC0C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVC0C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVC0C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
+
+#define NVC0C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVC0C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVC0C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                            16:0
+
+#define NVC0C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVC0C0_PIPE_NOP                                                                                    0x1a2c
+#define NVC0C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVC0C0_SET_SPARE00                                                                                 0x1a30
+#define NVC0C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVC0C0_SET_SPARE01                                                                                 0x1a34
+#define NVC0C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVC0C0_SET_SPARE02                                                                                 0x1a38
+#define NVC0C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVC0C0_SET_SPARE03                                                                                 0x1a3c
+#define NVC0C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVC0C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVC0C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVC0C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVC0C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+
+#define NVC0C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVC0C0_SET_TRAP_HANDLER                                                                            0x260c
+#define NVC0C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
+#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
+
+#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
+#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
+
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
+#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
+
+#define NVC0C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVC0C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_pascal_compute_a_h_ */
diff --git a/classes/compute/clc1c0.h b/classes/compute/clc1c0.h
new file mode 100644
index 0000000..e5d824f
--- /dev/null
+++ b/classes/compute/clc1c0.h
@@ -0,0 +1,1026 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_pascal_compute_b_h_
+#define _cl_pascal_compute_b_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */
+
+#include "nvtypes.h"
+
+#define PASCAL_COMPUTE_B    0xC1C0
+
+typedef volatile struct pascal_compute_b_struct {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 FeAtomicSequenceBegin;
+    NvU32 FeAtomicSequenceEnd;
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 Reserved_0x1E8[0x2];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 SetValidSpanOverflowAreaA;
+    NvU32 SetValidSpanOverflowAreaB;
+    NvU32 SetValidSpanOverflowAreaC;
+    NvU32 SetCoalesceWaitingPeriodUnit;
+    NvU32 PerfmonTransfer;
+    NvU32 SetShaderSharedMemoryWindow;
+    NvU32 SetSelectMaxwellTextureHeaders;
+    NvU32 InvalidateShaderCaches;
+    NvU32 SetReservedSwMethod00;
+    NvU32 SetReservedSwMethod01;
+    NvU32 SetReservedSwMethod02;
+    NvU32 SetReservedSwMethod03;
+    NvU32 SetReservedSwMethod04;
+    NvU32 SetReservedSwMethod05;
+    NvU32 SetReservedSwMethod06;
+    NvU32 SetReservedSwMethod07;
+    NvU32 SetCwdControl;
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 SetReservedSwMethod08;
+    NvU32 SetReservedSwMethod09;
+    NvU32 SetReservedSwMethod10;
+    NvU32 SetReservedSwMethod11;
+    NvU32 SetReservedSwMethod12;
+    NvU32 SetReservedSwMethod13;
+    NvU32 SetReservedSwMethod14;
+    NvU32 SetReservedSwMethod15;
+    NvU32 SetGwcScgType;
+    NvU32 SetScgControl;
+    NvU32 InvalidateConstantBufferCacheA;
+    NvU32 InvalidateConstantBufferCacheB;
+    NvU32 InvalidateConstantBufferCacheC;
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 SetWfiConfig;
+    NvU32 CheckQmdVersion;
+    NvU32 WaitForIdleScgType;
+    NvU32 InvalidateSkedCaches;
+    NvU32 SetScgRenderEnableControl;
+    NvU32 SetShaderSharedMemoryWindowA;
+    NvU32 SetShaderSharedMemoryWindowB;
+    NvU32 ScgHysteresisControl;
+    NvU32 Reserved_0x2AC[0x1];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x9];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 SetShaderLocalMemoryThrottledA;
+    NvU32 SetShaderLocalMemoryThrottledB;
+    NvU32 SetShaderLocalMemoryThrottledC;
+    NvU32 Reserved_0x2FC[0x5];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x1];
+    NvU32 SetInlineQmdAddressA;
+    NvU32 SetInlineQmdAddressB;
+    NvU32 LoadInlineQmdData[0x40];
+    NvU32 Reserved_0x420[0x38];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x7F];
+    NvU32 SetShaderLocalMemoryWindow;
+    NvU32 Reserved_0x780[0x4];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x6];
+    NvU32 SetShaderLocalMemoryWindowA;
+    NvU32 SetShaderLocalMemoryWindowB;
+    NvU32 Reserved_0x7B8[0x177];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x57];
+    NvU32 SetSpareNoop12;
+    NvU32 SetSpareNoop13;
+    NvU32 SetSpareNoop14;
+    NvU32 SetSpareNoop15;
+    NvU32 Reserved_0xF54[0x3B];
+    NvU32 SetSpareNoop00;
+    NvU32 SetSpareNoop01;
+    NvU32 SetSpareNoop02;
+    NvU32 SetSpareNoop03;
+    NvU32 SetSpareNoop04;
+    NvU32 SetSpareNoop05;
+    NvU32 SetSpareNoop06;
+    NvU32 SetSpareNoop07;
+    NvU32 SetSpareNoop08;
+    NvU32 SetSpareNoop09;
+    NvU32 SetSpareNoop10;
+    NvU32 SetSpareNoop11;
+    NvU32 Reserved_0x1070[0x67];
+    NvU32 InvalidateSamplerCacheAll;
+    NvU32 InvalidateTextureHeaderCacheAll;
+    NvU32 Reserved_0x1214[0x1D];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x7];
+    NvU32 ActivatePerfSettingsForComputeContext;
+    NvU32 Reserved_0x12AC[0x21];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x22];
+    NvU32 SetProgramRegionA;
+    NvU32 SetProgramRegionB;
+    NvU32 Reserved_0x1610[0x22];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A24[0x1];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BE];
+    NvU32 SetBindlessTexture;
+    NvU32 SetTrapHandler;
+    NvU32 Reserved_0x2610[0x34B];
+    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 StartShaderPerformanceCounter;
+    NvU32 StopShaderPerformanceCounter;
+    NvU32 SetShaderPerformanceCounterSctlFilter;
+    NvU32 SetShaderPerformanceCounterCoreMioFilter;
+    NvU32 Reserved_0x33F0[0x4];
+    NvU32 SetMmeShadowScratch[0x8];
+} pascal_compute_b_t;
+
+
+#define NVC1C0_SET_OBJECT                                                                                  0x0000
+#define NVC1C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVC1C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVC1C0_NO_OPERATION                                                                                0x0100
+#define NVC1C0_NO_OPERATION_V                                                                                31:0
+
+#define NVC1C0_SET_NOTIFY_A                                                                                0x0104
+#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVC1C0_SET_NOTIFY_B                                                                                0x0108
+#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVC1C0_NOTIFY                                                                                      0x010c
+#define NVC1C0_NOTIFY_TYPE                                                                                   31:0
+#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVC1C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVC1C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVC1C0_SEND_GO_IDLE                                                                                0x013c
+#define NVC1C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVC1C0_PM_TRIGGER                                                                                  0x0140
+#define NVC1C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVC1C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVC1C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN                                                                    0x0148
+#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V                                                                    31:0
+
+#define NVC1C0_FE_ATOMIC_SEQUENCE_END                                                                      0x014c
+#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V                                                                      31:0
+
+#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVC1C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVC1C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVC1C0_LINE_COUNT                                                                                  0x0184
+#define NVC1C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVC1C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVC1C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
+
+#define NVC1C0_OFFSET_OUT                                                                                  0x018c
+#define NVC1C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVC1C0_PITCH_OUT                                                                                   0x0190
+#define NVC1C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVC1C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVC1C0_SET_DST_WIDTH                                                                               0x0198
+#define NVC1C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVC1C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVC1C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVC1C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVC1C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVC1C0_SET_DST_LAYER                                                                               0x01a4
+#define NVC1C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVC1C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
+
+#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
+
+#define NVC1C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVC1C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVC1C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVC1C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC1C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC1C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVC1C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVC1C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVC1C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVC1C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVC1C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVC1C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVC1C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVC1C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
+#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
+
+#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
+#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
+
+#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
+#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
+
+#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT                                                            0x020c
+#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS                                                       31:0
+
+#define NVC1C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVC1C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW                                                             0x0214
+#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS                                                  31:0
+
+#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS                                                          0x0218
+#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V                                                           0:0
+#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE                                              0x00000000
+#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE                                               0x00000001
+
+#define NVC1C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVC1C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
+#define NVC1C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
+#define NVC1C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
+#define NVC1C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
+#define NVC1C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
+#define NVC1C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
+#define NVC1C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
+#define NVC1C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
+#define NVC1C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
+
+#define NVC1C0_SET_CWD_CONTROL                                                                             0x0240
+#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION                                                                   0:0
+#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED                                              0x00000000
+#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN                                                0x00000001
+
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVC1C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVC1C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVC1C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVC1C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
+#define NVC1C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
+#define NVC1C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
+#define NVC1C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
+#define NVC1C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
+#define NVC1C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
+#define NVC1C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
+#define NVC1C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
+
+#define NVC1C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
+#define NVC1C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
+
+#define NVC1C0_SET_GWC_SCG_TYPE                                                                            0x026c
+#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE                                                                      0:0
+#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0                                             0x00000000
+#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1                                                      0x00000001
+
+#define NVC1C0_SET_SCG_CONTROL                                                                             0x0270
+#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
+#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT                                                        20:12
+#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE                                        24:24
+#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE                             0x00000000
+#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE                              0x00000001
+
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A                                                          0x0274
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER                                              16:0
+
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B                                                          0x0278
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER                                              31:0
+
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C                                                          0x027c
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT                                                 16:0
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2                                                   31:31
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE                                        0x00000000
+#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE                                         0x00000001
+
+#define NVC1C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVC1C0_SET_QMD_VERSION                                                                             0x0288
+#define NVC1C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVC1C0_SET_WFI_CONFIG                                                                              0x028c
+#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI                                                             0:0
+#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE                                                0x00000000
+#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE                                                 0x00000001
+
+#define NVC1C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVC1C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE                                                                      0x0294
+#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V                                                                      31:0
+
+#define NVC1C0_INVALIDATE_SKED_CACHES                                                                      0x0298
+#define NVC1C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
+
+#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL                                                               0x029c
+#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE                                      0:0
+#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE                         0x00000000
+#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE                          0x00000001
+
+#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
+#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
+
+#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
+#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
+
+#define NVC1C0_SCG_HYSTERESIS_CONTROL                                                                      0x02a8
+#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE                                                        0:0
+#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE                                           0x00000000
+#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE                                            0x00000001
+#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE                                                   1:1
+#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE                                      0x00000000
+#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE                                       0x00000001
+
+#define NVC1C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVC1C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVC1C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVC1C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVC1C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVC1C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVC1C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A                                                         0x02f0
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER                                                 7:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B                                                         0x02f4
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER                                                31:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C                                                         0x02f8
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT                                               8:0
+
+#define NVC1C0_SET_SPA_VERSION                                                                             0x0310
+#define NVC1C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVC1C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVC1C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
+#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
+
+#define NVC1C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
+#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
+
+#define NVC1C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
+#define NVC1C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
+
+#define NVC1C0_SET_FALCON00                                                                                0x0500
+#define NVC1C0_SET_FALCON00_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON01                                                                                0x0504
+#define NVC1C0_SET_FALCON01_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON02                                                                                0x0508
+#define NVC1C0_SET_FALCON02_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON03                                                                                0x050c
+#define NVC1C0_SET_FALCON03_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON04                                                                                0x0510
+#define NVC1C0_SET_FALCON04_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON05                                                                                0x0514
+#define NVC1C0_SET_FALCON05_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON06                                                                                0x0518
+#define NVC1C0_SET_FALCON06_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON07                                                                                0x051c
+#define NVC1C0_SET_FALCON07_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON08                                                                                0x0520
+#define NVC1C0_SET_FALCON08_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON09                                                                                0x0524
+#define NVC1C0_SET_FALCON09_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON10                                                                                0x0528
+#define NVC1C0_SET_FALCON10_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON11                                                                                0x052c
+#define NVC1C0_SET_FALCON11_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON12                                                                                0x0530
+#define NVC1C0_SET_FALCON12_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON13                                                                                0x0534
+#define NVC1C0_SET_FALCON13_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON14                                                                                0x0538
+#define NVC1C0_SET_FALCON14_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON15                                                                                0x053c
+#define NVC1C0_SET_FALCON15_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON16                                                                                0x0540
+#define NVC1C0_SET_FALCON16_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON17                                                                                0x0544
+#define NVC1C0_SET_FALCON17_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON18                                                                                0x0548
+#define NVC1C0_SET_FALCON18_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON19                                                                                0x054c
+#define NVC1C0_SET_FALCON19_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON20                                                                                0x0550
+#define NVC1C0_SET_FALCON20_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON21                                                                                0x0554
+#define NVC1C0_SET_FALCON21_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON22                                                                                0x0558
+#define NVC1C0_SET_FALCON22_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON23                                                                                0x055c
+#define NVC1C0_SET_FALCON23_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON24                                                                                0x0560
+#define NVC1C0_SET_FALCON24_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON25                                                                                0x0564
+#define NVC1C0_SET_FALCON25_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON26                                                                                0x0568
+#define NVC1C0_SET_FALCON26_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON27                                                                                0x056c
+#define NVC1C0_SET_FALCON27_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON28                                                                                0x0570
+#define NVC1C0_SET_FALCON28_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON29                                                                                0x0574
+#define NVC1C0_SET_FALCON29_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON30                                                                                0x0578
+#define NVC1C0_SET_FALCON30_V                                                                                31:0
+
+#define NVC1C0_SET_FALCON31                                                                                0x057c
+#define NVC1C0_SET_FALCON31_V                                                                                31:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW                                                              0x077c
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS                                                   31:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
+
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
+#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
+
+#define NVC1C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVC1C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVC1C0_SET_SPARE_NOOP12                                                                            0x0f44
+#define NVC1C0_SET_SPARE_NOOP12_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP13                                                                            0x0f48
+#define NVC1C0_SET_SPARE_NOOP13_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP14                                                                            0x0f4c
+#define NVC1C0_SET_SPARE_NOOP14_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP15                                                                            0x0f50
+#define NVC1C0_SET_SPARE_NOOP15_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP00                                                                            0x1040
+#define NVC1C0_SET_SPARE_NOOP00_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP01                                                                            0x1044
+#define NVC1C0_SET_SPARE_NOOP01_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP02                                                                            0x1048
+#define NVC1C0_SET_SPARE_NOOP02_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP03                                                                            0x104c
+#define NVC1C0_SET_SPARE_NOOP03_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP04                                                                            0x1050
+#define NVC1C0_SET_SPARE_NOOP04_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP05                                                                            0x1054
+#define NVC1C0_SET_SPARE_NOOP05_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP06                                                                            0x1058
+#define NVC1C0_SET_SPARE_NOOP06_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP07                                                                            0x105c
+#define NVC1C0_SET_SPARE_NOOP07_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP08                                                                            0x1060
+#define NVC1C0_SET_SPARE_NOOP08_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP09                                                                            0x1064
+#define NVC1C0_SET_SPARE_NOOP09_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP10                                                                            0x1068
+#define NVC1C0_SET_SPARE_NOOP10_V                                                                            31:0
+
+#define NVC1C0_SET_SPARE_NOOP11                                                                            0x106c
+#define NVC1C0_SET_SPARE_NOOP11_V                                                                            31:0
+
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
+
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
+
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
+#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
+#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
+#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
+
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVC1C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVC1C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC1C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC1C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVC1C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVC1C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
+
+#define NVC1C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVC1C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVC1C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
+
+#define NVC1C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVC1C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVC1C0_SET_PROGRAM_REGION_A                                                                        0x1608
+#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER                                                            16:0
+
+#define NVC1C0_SET_PROGRAM_REGION_B                                                                        0x160c
+#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER                                                            31:0
+
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVC1C0_PIPE_NOP                                                                                    0x1a2c
+#define NVC1C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVC1C0_SET_SPARE00                                                                                 0x1a30
+#define NVC1C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVC1C0_SET_SPARE01                                                                                 0x1a34
+#define NVC1C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVC1C0_SET_SPARE02                                                                                 0x1a38
+#define NVC1C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVC1C0_SET_SPARE03                                                                                 0x1a3c
+#define NVC1C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVC1C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVC1C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVC1C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVC1C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+
+#define NVC1C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVC1C0_SET_TRAP_HANDLER                                                                            0x260c
+#define NVC1C0_SET_TRAP_HANDLER_OFFSET                                                                       31:0
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
+#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
+
+#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
+#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
+
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
+#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
+
+#define NVC1C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVC1C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_pascal_compute_b_h_ */
diff --git a/classes/compute/clc3c0.h b/classes/compute/clc3c0.h
new file mode 100644
index 0000000..c70a44f
--- /dev/null
+++ b/classes/compute/clc3c0.h
@@ -0,0 +1,912 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_volta_compute_a_h_
+#define _cl_volta_compute_a_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */
+
+#include "nvtypes.h"
+
+#define VOLTA_COMPUTE_A    0xC3C0
+
+typedef volatile struct volta_compute_a_struct {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 FeAtomicSequenceBegin;
+    NvU32 FeAtomicSequenceEnd;
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 Reserved_0x1E8[0x2];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 SetValidSpanOverflowAreaA;
+    NvU32 SetValidSpanOverflowAreaB;
+    NvU32 SetValidSpanOverflowAreaC;
+    NvU32 Reserved_0x20C[0x1];
+    NvU32 PerfmonTransfer;
+    NvU32 Reserved_0x214[0x2];
+    NvU32 InvalidateShaderCaches;
+    NvU32 SetReservedSwMethod00;
+    NvU32 SetReservedSwMethod01;
+    NvU32 SetReservedSwMethod02;
+    NvU32 SetReservedSwMethod03;
+    NvU32 SetReservedSwMethod04;
+    NvU32 SetReservedSwMethod05;
+    NvU32 SetReservedSwMethod06;
+    NvU32 SetReservedSwMethod07;
+    NvU32 Reserved_0x240[0x1];
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 SetReservedSwMethod08;
+    NvU32 SetReservedSwMethod09;
+    NvU32 SetReservedSwMethod10;
+    NvU32 SetReservedSwMethod11;
+    NvU32 SetReservedSwMethod12;
+    NvU32 SetReservedSwMethod13;
+    NvU32 SetReservedSwMethod14;
+    NvU32 SetReservedSwMethod15;
+    NvU32 Reserved_0x26C[0x1];
+    NvU32 SetScgControl;
+    NvU32 Reserved_0x274[0x3];
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 Reserved_0x28C[0x1];
+    NvU32 CheckQmdVersion;
+    NvU32 Reserved_0x294[0x1];
+    NvU32 InvalidateSkedCaches;
+    NvU32 Reserved_0x29C[0x1];
+    NvU32 SetShaderSharedMemoryWindowA;
+    NvU32 SetShaderSharedMemoryWindowB;
+    NvU32 ScgHysteresisControl;
+    NvU32 Reserved_0x2AC[0x1];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x3];
+    NvU32 SetSkedCacheControl;
+    NvU32 Reserved_0x2D0[0x5];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 Reserved_0x2F0[0x8];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x1];
+    NvU32 SetInlineQmdAddressA;
+    NvU32 SetInlineQmdAddressB;
+    NvU32 LoadInlineQmdData[0x40];
+    NvU32 Reserved_0x420[0x38];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x84];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x6];
+    NvU32 SetShaderLocalMemoryWindowA;
+    NvU32 SetShaderLocalMemoryWindowB;
+    NvU32 Reserved_0x7B8[0x177];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x13];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x109];
+    NvU32 InvalidateSamplerCacheAll;
+    NvU32 InvalidateTextureHeaderCacheAll;
+    NvU32 Reserved_0x1214[0x1D];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x7];
+    NvU32 ActivatePerfSettingsForComputeContext;
+    NvU32 Reserved_0x12AC[0x21];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x46];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BA];
+    NvU32 SetTrapHandlerA;
+    NvU32 SetTrapHandlerB;
+    NvU32 Reserved_0x2600[0x2];
+    NvU32 SetBindlessTexture;
+    NvU32 Reserved_0x260C[0x33A];
+    NvU32 SetShaderPerformanceSnapshotCounterValue[0x8];
+    NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8];
+    NvU32 EnableShaderPerformanceSnapshotCounter;
+    NvU32 DisableShaderPerformanceSnapshotCounter;
+    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 StartShaderPerformanceCounter;
+    NvU32 StopShaderPerformanceCounter;
+    NvU32 SetShaderPerformanceCounterSctlFilter;
+    NvU32 SetShaderPerformanceCounterCoreMioFilter;
+    NvU32 Reserved_0x33F0[0x4];
+    NvU32 SetMmeShadowScratch[0x8];
+} volta_compute_a_t;
+
+
+#define NVC3C0_SET_OBJECT                                                                                  0x0000
+#define NVC3C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVC3C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVC3C0_NO_OPERATION                                                                                0x0100
+#define NVC3C0_NO_OPERATION_V                                                                                31:0
+
+#define NVC3C0_SET_NOTIFY_A                                                                                0x0104
+#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVC3C0_SET_NOTIFY_B                                                                                0x0108
+#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVC3C0_NOTIFY                                                                                      0x010c
+#define NVC3C0_NOTIFY_TYPE                                                                                   31:0
+#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVC3C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVC3C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVC3C0_SEND_GO_IDLE                                                                                0x013c
+#define NVC3C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVC3C0_PM_TRIGGER                                                                                  0x0140
+#define NVC3C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVC3C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVC3C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN                                                                    0x0148
+#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V                                                                    31:0
+
+#define NVC3C0_FE_ATOMIC_SEQUENCE_END                                                                      0x014c
+#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V                                                                      31:0
+
+#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVC3C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVC3C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVC3C0_LINE_COUNT                                                                                  0x0184
+#define NVC3C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVC3C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVC3C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
+
+#define NVC3C0_OFFSET_OUT                                                                                  0x018c
+#define NVC3C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVC3C0_PITCH_OUT                                                                                   0x0190
+#define NVC3C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVC3C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVC3C0_SET_DST_WIDTH                                                                               0x0198
+#define NVC3C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVC3C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVC3C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVC3C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVC3C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVC3C0_SET_DST_LAYER                                                                               0x01a4
+#define NVC3C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVC3C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
+
+#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
+
+#define NVC3C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVC3C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVC3C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVC3C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC3C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC3C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVC3C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVC3C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVC3C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVC3C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVC3C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVC3C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVC3C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVC3C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
+#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
+
+#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
+#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
+
+#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
+#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
+
+#define NVC3C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVC3C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVC3C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVC3C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
+#define NVC3C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
+#define NVC3C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
+#define NVC3C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
+#define NVC3C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
+#define NVC3C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
+#define NVC3C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
+#define NVC3C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
+#define NVC3C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
+
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVC3C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVC3C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVC3C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVC3C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
+#define NVC3C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
+#define NVC3C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
+#define NVC3C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
+#define NVC3C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
+#define NVC3C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
+#define NVC3C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
+#define NVC3C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
+
+#define NVC3C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
+#define NVC3C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
+
+#define NVC3C0_SET_SCG_CONTROL                                                                             0x0270
+#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
+#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT                                                        20:12
+#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE                                        24:24
+#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE                             0x00000000
+#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE                              0x00000001
+
+#define NVC3C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVC3C0_SET_QMD_VERSION                                                                             0x0288
+#define NVC3C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVC3C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVC3C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVC3C0_INVALIDATE_SKED_CACHES                                                                      0x0298
+#define NVC3C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
+
+#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
+#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
+
+#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
+#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
+
+#define NVC3C0_SCG_HYSTERESIS_CONTROL                                                                      0x02a8
+#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE                                                        0:0
+#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE                                           0x00000000
+#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE                                            0x00000001
+#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE                                                   1:1
+#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE                                      0x00000000
+#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE                                       0x00000001
+
+#define NVC3C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVC3C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVC3C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVC3C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVC3C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVC3C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVC3C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVC3C0_SET_SKED_CACHE_CONTROL                                                                      0x02cc
+#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID                                                             0:0
+#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE                                                0x00000000
+#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE                                                 0x00000001
+
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVC3C0_SET_SPA_VERSION                                                                             0x0310
+#define NVC3C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVC3C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVC3C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
+#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
+
+#define NVC3C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
+#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
+
+#define NVC3C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
+#define NVC3C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
+
+#define NVC3C0_SET_FALCON00                                                                                0x0500
+#define NVC3C0_SET_FALCON00_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON01                                                                                0x0504
+#define NVC3C0_SET_FALCON01_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON02                                                                                0x0508
+#define NVC3C0_SET_FALCON02_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON03                                                                                0x050c
+#define NVC3C0_SET_FALCON03_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON04                                                                                0x0510
+#define NVC3C0_SET_FALCON04_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON05                                                                                0x0514
+#define NVC3C0_SET_FALCON05_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON06                                                                                0x0518
+#define NVC3C0_SET_FALCON06_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON07                                                                                0x051c
+#define NVC3C0_SET_FALCON07_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON08                                                                                0x0520
+#define NVC3C0_SET_FALCON08_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON09                                                                                0x0524
+#define NVC3C0_SET_FALCON09_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON10                                                                                0x0528
+#define NVC3C0_SET_FALCON10_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON11                                                                                0x052c
+#define NVC3C0_SET_FALCON11_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON12                                                                                0x0530
+#define NVC3C0_SET_FALCON12_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON13                                                                                0x0534
+#define NVC3C0_SET_FALCON13_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON14                                                                                0x0538
+#define NVC3C0_SET_FALCON14_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON15                                                                                0x053c
+#define NVC3C0_SET_FALCON15_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON16                                                                                0x0540
+#define NVC3C0_SET_FALCON16_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON17                                                                                0x0544
+#define NVC3C0_SET_FALCON17_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON18                                                                                0x0548
+#define NVC3C0_SET_FALCON18_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON19                                                                                0x054c
+#define NVC3C0_SET_FALCON19_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON20                                                                                0x0550
+#define NVC3C0_SET_FALCON20_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON21                                                                                0x0554
+#define NVC3C0_SET_FALCON21_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON22                                                                                0x0558
+#define NVC3C0_SET_FALCON22_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON23                                                                                0x055c
+#define NVC3C0_SET_FALCON23_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON24                                                                                0x0560
+#define NVC3C0_SET_FALCON24_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON25                                                                                0x0564
+#define NVC3C0_SET_FALCON25_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON26                                                                                0x0568
+#define NVC3C0_SET_FALCON26_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON27                                                                                0x056c
+#define NVC3C0_SET_FALCON27_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON28                                                                                0x0570
+#define NVC3C0_SET_FALCON28_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON29                                                                                0x0574
+#define NVC3C0_SET_FALCON29_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON30                                                                                0x0578
+#define NVC3C0_SET_FALCON30_V                                                                                31:0
+
+#define NVC3C0_SET_FALCON31                                                                                0x057c
+#define NVC3C0_SET_FALCON31_V                                                                                31:0
+
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
+
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
+
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
+#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
+
+#define NVC3C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVC3C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL                                                                0x120c
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V                                                                 0:0
+
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL                                                         0x1210
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V                                                          0:0
+
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
+#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
+#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
+#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
+
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVC3C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVC3C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC3C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC3C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVC3C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVC3C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
+
+#define NVC3C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVC3C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVC3C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
+
+#define NVC3C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVC3C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVC3C0_PIPE_NOP                                                                                    0x1a2c
+#define NVC3C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVC3C0_SET_SPARE00                                                                                 0x1a30
+#define NVC3C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVC3C0_SET_SPARE01                                                                                 0x1a34
+#define NVC3C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVC3C0_SET_SPARE02                                                                                 0x1a38
+#define NVC3C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVC3C0_SET_SPARE03                                                                                 0x1a3c
+#define NVC3C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVC3C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVC3C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVC3C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVC3C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+
+#define NVC3C0_SET_TRAP_HANDLER_A                                                                          0x25f8
+#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER                                                              16:0
+
+#define NVC3C0_SET_TRAP_HANDLER_B                                                                          0x25fc
+#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER                                                              31:0
+
+#define NVC3C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i)                                    (0x32f4+(i)*4)
+#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V                                               31:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i)                              (0x3314+(i)*4)
+#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V                                         31:0
+
+#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                  0x3334
+#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                   0:0
+
+#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                 0x3338
+#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                  0:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
+#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
+
+#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
+#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
+
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
+#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
+
+#define NVC3C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVC3C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_volta_compute_a_h_ */
diff --git a/classes/compute/clc5c0.h b/classes/compute/clc5c0.h
new file mode 100644
index 0000000..3d0fd54
--- /dev/null
+++ b/classes/compute/clc5c0.h
@@ -0,0 +1,942 @@
+/*
+ * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _cl_turing_compute_a_h_
+#define _cl_turing_compute_a_h_
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */
+
+#include "nvtypes.h"
+
+#define TURING_COMPUTE_A    0xC5C0
+
+typedef volatile struct turing_compute_a_struct {
+    NvU32 SetObject;
+    NvU32 Reserved_0x04[0x3F];
+    NvU32 NoOperation;
+    NvU32 SetNotifyA;
+    NvU32 SetNotifyB;
+    NvU32 Notify;
+    NvU32 WaitForIdle;
+    NvU32 Reserved_0x114[0x7];
+    NvU32 SetGlobalRenderEnableA;
+    NvU32 SetGlobalRenderEnableB;
+    NvU32 SetGlobalRenderEnableC;
+    NvU32 SendGoIdle;
+    NvU32 PmTrigger;
+    NvU32 PmTriggerWfi;
+    NvU32 FeAtomicSequenceBegin;
+    NvU32 FeAtomicSequenceEnd;
+    NvU32 SetInstrumentationMethodHeader;
+    NvU32 SetInstrumentationMethodData;
+    NvU32 Reserved_0x158[0xA];
+    NvU32 LineLengthIn;
+    NvU32 LineCount;
+    NvU32 OffsetOutUpper;
+    NvU32 OffsetOut;
+    NvU32 PitchOut;
+    NvU32 SetDstBlockSize;
+    NvU32 SetDstWidth;
+    NvU32 SetDstHeight;
+    NvU32 SetDstDepth;
+    NvU32 SetDstLayer;
+    NvU32 SetDstOriginBytesX;
+    NvU32 SetDstOriginSamplesY;
+    NvU32 LaunchDma;
+    NvU32 LoadInlineData;
+    NvU32 Reserved_0x1B8[0x9];
+    NvU32 SetI2mSemaphoreA;
+    NvU32 SetI2mSemaphoreB;
+    NvU32 SetI2mSemaphoreC;
+    NvU32 SetSmScgControl;
+    NvU32 Reserved_0x1EC[0x1];
+    NvU32 SetI2mSpareNoop00;
+    NvU32 SetI2mSpareNoop01;
+    NvU32 SetI2mSpareNoop02;
+    NvU32 SetI2mSpareNoop03;
+    NvU32 SetValidSpanOverflowAreaA;
+    NvU32 SetValidSpanOverflowAreaB;
+    NvU32 SetValidSpanOverflowAreaC;
+    NvU32 Reserved_0x20C[0x1];
+    NvU32 PerfmonTransfer;
+    NvU32 SetQmdVirtualizationBaseA;
+    NvU32 SetQmdVirtualizationBaseB;
+    NvU32 InvalidateShaderCaches;
+    NvU32 SetReservedSwMethod00;
+    NvU32 SetReservedSwMethod01;
+    NvU32 SetReservedSwMethod02;
+    NvU32 SetReservedSwMethod03;
+    NvU32 SetReservedSwMethod04;
+    NvU32 SetReservedSwMethod05;
+    NvU32 SetReservedSwMethod06;
+    NvU32 SetReservedSwMethod07;
+    NvU32 Reserved_0x240[0x1];
+    NvU32 InvalidateTextureHeaderCacheNoWfi;
+    NvU32 SetCwdRefCounter;
+    NvU32 SetReservedSwMethod08;
+    NvU32 SetReservedSwMethod09;
+    NvU32 SetReservedSwMethod10;
+    NvU32 SetReservedSwMethod11;
+    NvU32 SetReservedSwMethod12;
+    NvU32 SetReservedSwMethod13;
+    NvU32 SetReservedSwMethod14;
+    NvU32 SetReservedSwMethod15;
+    NvU32 Reserved_0x26C[0x1];
+    NvU32 SetScgControl;
+    NvU32 Reserved_0x274[0x3];
+    NvU32 SetComputeClassVersion;
+    NvU32 CheckComputeClassVersion;
+    NvU32 SetQmdVersion;
+    NvU32 Reserved_0x28C[0x1];
+    NvU32 CheckQmdVersion;
+    NvU32 Reserved_0x294[0x1];
+    NvU32 InvalidateSkedCaches;
+    NvU32 SetQmdVirtualizationControl;
+    NvU32 SetShaderSharedMemoryWindowA;
+    NvU32 SetShaderSharedMemoryWindowB;
+    NvU32 ScgHysteresisControl;
+    NvU32 Reserved_0x2AC[0x1];
+    NvU32 SetCwdSlotCount;
+    NvU32 SendPcasA;
+    NvU32 SendPcasB;
+    NvU32 SendSignalingPcasB;
+    NvU32 Reserved_0x2C0[0x3];
+    NvU32 SetSkedCacheControl;
+    NvU32 Reserved_0x2D0[0x5];
+    NvU32 SetShaderLocalMemoryNonThrottledA;
+    NvU32 SetShaderLocalMemoryNonThrottledB;
+    NvU32 SetShaderLocalMemoryNonThrottledC;
+    NvU32 Reserved_0x2F0[0x8];
+    NvU32 SetSpaVersion;
+    NvU32 Reserved_0x314[0x1];
+    NvU32 SetInlineQmdAddressA;
+    NvU32 SetInlineQmdAddressB;
+    NvU32 LoadInlineQmdData[0x40];
+    NvU32 Reserved_0x420[0x38];
+    NvU32 SetFalcon00;
+    NvU32 SetFalcon01;
+    NvU32 SetFalcon02;
+    NvU32 SetFalcon03;
+    NvU32 SetFalcon04;
+    NvU32 SetFalcon05;
+    NvU32 SetFalcon06;
+    NvU32 SetFalcon07;
+    NvU32 SetFalcon08;
+    NvU32 SetFalcon09;
+    NvU32 SetFalcon10;
+    NvU32 SetFalcon11;
+    NvU32 SetFalcon12;
+    NvU32 SetFalcon13;
+    NvU32 SetFalcon14;
+    NvU32 SetFalcon15;
+    NvU32 SetFalcon16;
+    NvU32 SetFalcon17;
+    NvU32 SetFalcon18;
+    NvU32 SetFalcon19;
+    NvU32 SetFalcon20;
+    NvU32 SetFalcon21;
+    NvU32 SetFalcon22;
+    NvU32 SetFalcon23;
+    NvU32 SetFalcon24;
+    NvU32 SetFalcon25;
+    NvU32 SetFalcon26;
+    NvU32 SetFalcon27;
+    NvU32 SetFalcon28;
+    NvU32 SetFalcon29;
+    NvU32 SetFalcon30;
+    NvU32 SetFalcon31;
+    NvU32 Reserved_0x580[0x84];
+    NvU32 SetShaderLocalMemoryA;
+    NvU32 SetShaderLocalMemoryB;
+    NvU32 Reserved_0x798[0x6];
+    NvU32 SetShaderLocalMemoryWindowA;
+    NvU32 SetShaderLocalMemoryWindowB;
+    NvU32 Reserved_0x7B8[0x177];
+    NvU32 SetShaderCacheControl;
+    NvU32 Reserved_0xD98[0x2];
+    NvU32 SetScgComputeSchedulingParameters[0x10];
+    NvU32 Reserved_0xDE0[0x1];
+    NvU32 SetSmTimeoutInterval;
+    NvU32 Reserved_0xDE8[0x128];
+    NvU32 InvalidateTextureDataCacheNoWfi;
+    NvU32 Reserved_0x128C[0x7];
+    NvU32 ActivatePerfSettingsForComputeContext;
+    NvU32 Reserved_0x12AC[0x21];
+    NvU32 InvalidateSamplerCache;
+    NvU32 InvalidateTextureHeaderCache;
+    NvU32 InvalidateTextureDataCache;
+    NvU32 Reserved_0x133C[0x3A];
+    NvU32 InvalidateSamplerCacheNoWfi;
+    NvU32 Reserved_0x1428[0x40];
+    NvU32 SetShaderExceptions;
+    NvU32 Reserved_0x152C[0x9];
+    NvU32 SetRenderEnableA;
+    NvU32 SetRenderEnableB;
+    NvU32 SetRenderEnableC;
+    NvU32 SetTexSamplerPoolA;
+    NvU32 SetTexSamplerPoolB;
+    NvU32 SetTexSamplerPoolC;
+    NvU32 Reserved_0x1568[0x3];
+    NvU32 SetTexHeaderPoolA;
+    NvU32 SetTexHeaderPoolB;
+    NvU32 SetTexHeaderPoolC;
+    NvU32 Reserved_0x1580[0x46];
+    NvU32 InvalidateShaderCachesNoWfi;
+    NvU32 Reserved_0x169C[0xAA];
+    NvU32 SetRenderEnableOverride;
+    NvU32 Reserved_0x1948[0x37];
+    NvU32 Reserved_0x1A28[0x1];
+    NvU32 PipeNop;
+    NvU32 SetSpare00;
+    NvU32 SetSpare01;
+    NvU32 SetSpare02;
+    NvU32 SetSpare03;
+    NvU32 Reserved_0x1A40[0x30];
+    NvU32 SetReportSemaphoreA;
+    NvU32 SetReportSemaphoreB;
+    NvU32 SetReportSemaphoreC;
+    NvU32 SetReportSemaphoreD;
+    NvU32 Reserved_0x1B10[0x2BA];
+    NvU32 SetTrapHandlerA;
+    NvU32 SetTrapHandlerB;
+    NvU32 Reserved_0x2600[0x2];
+    NvU32 SetBindlessTexture;
+    NvU32 Reserved_0x260C[0x33A];
+    NvU32 SetShaderPerformanceSnapshotCounterValue[0x8];
+    NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8];
+    NvU32 EnableShaderPerformanceSnapshotCounter;
+    NvU32 DisableShaderPerformanceSnapshotCounter;
+    NvU32 SetShaderPerformanceCounterValueUpper[0x8];
+    NvU32 SetShaderPerformanceCounterValue[0x8];
+    NvU32 SetShaderPerformanceCounterEvent[0x8];
+    NvU32 SetShaderPerformanceCounterControlA[0x8];
+    NvU32 SetShaderPerformanceCounterControlB[0x8];
+    NvU32 SetShaderPerformanceCounterTrapControl;
+    NvU32 StartShaderPerformanceCounter;
+    NvU32 StopShaderPerformanceCounter;
+    NvU32 SetShaderPerformanceCounterSctlFilter;
+    NvU32 SetShaderPerformanceCounterCoreMioFilter;
+    NvU32 Reserved_0x33F0[0x4];
+    NvU32 SetMmeShadowScratch[0x8];
+} turing_compute_a_t;
+
+
+#define NVC5C0_SET_OBJECT                                                                                  0x0000
+#define NVC5C0_SET_OBJECT_CLASS_ID                                                                           15:0
+#define NVC5C0_SET_OBJECT_ENGINE_ID                                                                         20:16
+
+#define NVC5C0_NO_OPERATION                                                                                0x0100
+#define NVC5C0_NO_OPERATION_V                                                                                31:0
+
+#define NVC5C0_SET_NOTIFY_A                                                                                0x0104
+#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER                                                                     7:0
+
+#define NVC5C0_SET_NOTIFY_B                                                                                0x0108
+#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER                                                                    31:0
+
+#define NVC5C0_NOTIFY                                                                                      0x010c
+#define NVC5C0_NOTIFY_TYPE                                                                                   31:0
+#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY                                                                  0x00000000
+#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN                                                           0x00000001
+
+#define NVC5C0_WAIT_FOR_IDLE                                                                               0x0110
+#define NVC5C0_WAIT_FOR_IDLE_V                                                                               31:0
+
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A                                                                  0x0130
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER                                                        7:0
+
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B                                                                  0x0134
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER                                                       31:0
+
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C                                                                  0x0138
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE                                                                2:0
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE                                                   0x00000000
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE                                                    0x00000001
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL                                             0x00000002
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                         0x00000003
+#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                     0x00000004
+
+#define NVC5C0_SEND_GO_IDLE                                                                                0x013c
+#define NVC5C0_SEND_GO_IDLE_V                                                                                31:0
+
+#define NVC5C0_PM_TRIGGER                                                                                  0x0140
+#define NVC5C0_PM_TRIGGER_V                                                                                  31:0
+
+#define NVC5C0_PM_TRIGGER_WFI                                                                              0x0144
+#define NVC5C0_PM_TRIGGER_WFI_V                                                                              31:0
+
+#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN                                                                    0x0148
+#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V                                                                    31:0
+
+#define NVC5C0_FE_ATOMIC_SEQUENCE_END                                                                      0x014c
+#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V                                                                      31:0
+
+#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER                                                           0x0150
+#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V                                                           31:0
+
+#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA                                                             0x0154
+#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V                                                             31:0
+
+#define NVC5C0_LINE_LENGTH_IN                                                                              0x0180
+#define NVC5C0_LINE_LENGTH_IN_VALUE                                                                          31:0
+
+#define NVC5C0_LINE_COUNT                                                                                  0x0184
+#define NVC5C0_LINE_COUNT_VALUE                                                                              31:0
+
+#define NVC5C0_OFFSET_OUT_UPPER                                                                            0x0188
+#define NVC5C0_OFFSET_OUT_UPPER_VALUE                                                                        16:0
+
+#define NVC5C0_OFFSET_OUT                                                                                  0x018c
+#define NVC5C0_OFFSET_OUT_VALUE                                                                              31:0
+
+#define NVC5C0_PITCH_OUT                                                                                   0x0190
+#define NVC5C0_PITCH_OUT_VALUE                                                                               31:0
+
+#define NVC5C0_SET_DST_BLOCK_SIZE                                                                          0x0194
+#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH                                                                       3:0
+#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                                        0x00000000
+#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT                                                                      7:4
+#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                                       0x00000000
+#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                                                      0x00000001
+#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                                                     0x00000002
+#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                                                    0x00000003
+#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                                                  0x00000004
+#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                                                0x00000005
+#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH                                                                      11:8
+#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                                        0x00000000
+#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                                       0x00000001
+#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                                                      0x00000002
+#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                                                     0x00000003
+#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                                                   0x00000004
+#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                                                 0x00000005
+
+#define NVC5C0_SET_DST_WIDTH                                                                               0x0198
+#define NVC5C0_SET_DST_WIDTH_V                                                                               31:0
+
+#define NVC5C0_SET_DST_HEIGHT                                                                              0x019c
+#define NVC5C0_SET_DST_HEIGHT_V                                                                              31:0
+
+#define NVC5C0_SET_DST_DEPTH                                                                               0x01a0
+#define NVC5C0_SET_DST_DEPTH_V                                                                               31:0
+
+#define NVC5C0_SET_DST_LAYER                                                                               0x01a4
+#define NVC5C0_SET_DST_LAYER_V                                                                               31:0
+
+#define NVC5C0_SET_DST_ORIGIN_BYTES_X                                                                      0x01a8
+#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V                                                                      20:0
+
+#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y                                                                    0x01ac
+#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V                                                                    16:0
+
+#define NVC5C0_LAUNCH_DMA                                                                                  0x01b0
+#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT                                                                   0:0
+#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                                                0x00000000
+#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                                                      0x00000001
+#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE                                                                     5:4
+#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE                                                0x00000000
+#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY                                                   0x00000001
+#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE                                            0x00000002
+#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE                                                                      9:8
+#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                                          0x00000000
+#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT                                                     0x00000001
+#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE                                                             12:12
+#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS                                             0x00000000
+#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD                                               0x00000001
+#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE                                                                    1:1
+#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE                                                       0x00000000
+#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE                                                        0x00000001
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP                                                                      15:13
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD                                                         0x00000000
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN                                                         0x00000001
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX                                                         0x00000002
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC                                                         0x00000003
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC                                                         0x00000004
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND                                                         0x00000005
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR                                                          0x00000006
+#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR                                                         0x00000007
+#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT                                                                    3:2
+#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32                                                 0x00000000
+#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32                                                   0x00000001
+#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE                                                                   6:6
+#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE                                                      0x00000000
+#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE                                                       0x00000001
+
+#define NVC5C0_LOAD_INLINE_DATA                                                                            0x01b4
+#define NVC5C0_LOAD_INLINE_DATA_V                                                                            31:0
+
+#define NVC5C0_SET_I2M_SEMAPHORE_A                                                                         0x01dc
+#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC5C0_SET_I2M_SEMAPHORE_B                                                                         0x01e0
+#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC5C0_SET_I2M_SEMAPHORE_C                                                                         0x01e4
+#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD                                                                   31:0
+
+#define NVC5C0_SET_SM_SCG_CONTROL                                                                          0x01e8
+#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS                                                         0:0
+#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE                                            0x00000000
+#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE                                             0x00000001
+
+#define NVC5C0_SET_I2M_SPARE_NOOP00                                                                        0x01f0
+#define NVC5C0_SET_I2M_SPARE_NOOP00_V                                                                        31:0
+
+#define NVC5C0_SET_I2M_SPARE_NOOP01                                                                        0x01f4
+#define NVC5C0_SET_I2M_SPARE_NOOP01_V                                                                        31:0
+
+#define NVC5C0_SET_I2M_SPARE_NOOP02                                                                        0x01f8
+#define NVC5C0_SET_I2M_SPARE_NOOP02_V                                                                        31:0
+
+#define NVC5C0_SET_I2M_SPARE_NOOP03                                                                        0x01fc
+#define NVC5C0_SET_I2M_SPARE_NOOP03_V                                                                        31:0
+
+#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A                                                              0x0200
+#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER                                                   7:0
+
+#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B                                                              0x0204
+#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER                                                  31:0
+
+#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C                                                              0x0208
+#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE                                                           31:0
+
+#define NVC5C0_PERFMON_TRANSFER                                                                            0x0210
+#define NVC5C0_PERFMON_TRANSFER_V                                                                            31:0
+
+#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A                                                               0x0214
+#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER                                                    7:0
+
+#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B                                                               0x0218
+#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER                                                   31:0
+
+#define NVC5C0_INVALIDATE_SHADER_CACHES                                                                    0x021c
+#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION                                                           0:0
+#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE                                              0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE                                               0x00000001
+#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA                                                                  4:4
+#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE                                                     0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE                                                      0x00000001
+#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT                                                            12:12
+#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE                                                 0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE                                                  0x00000001
+#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS                                                                 1:1
+#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE                                                    0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE                                                     0x00000001
+#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA                                                            2:2
+#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE                                               0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE                                                0x00000001
+
+#define NVC5C0_SET_RESERVED_SW_METHOD00                                                                    0x0220
+#define NVC5C0_SET_RESERVED_SW_METHOD00_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD01                                                                    0x0224
+#define NVC5C0_SET_RESERVED_SW_METHOD01_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD02                                                                    0x0228
+#define NVC5C0_SET_RESERVED_SW_METHOD02_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD03                                                                    0x022c
+#define NVC5C0_SET_RESERVED_SW_METHOD03_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD04                                                                    0x0230
+#define NVC5C0_SET_RESERVED_SW_METHOD04_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD05                                                                    0x0234
+#define NVC5C0_SET_RESERVED_SW_METHOD05_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD06                                                                    0x0238
+#define NVC5C0_SET_RESERVED_SW_METHOD06_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD07                                                                    0x023c
+#define NVC5C0_SET_RESERVED_SW_METHOD07_V                                                                    31:0
+
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI                                                      0x0244
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES                                                   0:0
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL                                        0x00000000
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE                                        0x00000001
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG                                                    25:4
+
+#define NVC5C0_SET_CWD_REF_COUNTER                                                                         0x0248
+#define NVC5C0_SET_CWD_REF_COUNTER_SELECT                                                                     5:0
+#define NVC5C0_SET_CWD_REF_COUNTER_VALUE                                                                     23:8
+
+#define NVC5C0_SET_RESERVED_SW_METHOD08                                                                    0x024c
+#define NVC5C0_SET_RESERVED_SW_METHOD08_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD09                                                                    0x0250
+#define NVC5C0_SET_RESERVED_SW_METHOD09_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD10                                                                    0x0254
+#define NVC5C0_SET_RESERVED_SW_METHOD10_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD11                                                                    0x0258
+#define NVC5C0_SET_RESERVED_SW_METHOD11_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD12                                                                    0x025c
+#define NVC5C0_SET_RESERVED_SW_METHOD12_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD13                                                                    0x0260
+#define NVC5C0_SET_RESERVED_SW_METHOD13_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD14                                                                    0x0264
+#define NVC5C0_SET_RESERVED_SW_METHOD14_V                                                                    31:0
+
+#define NVC5C0_SET_RESERVED_SW_METHOD15                                                                    0x0268
+#define NVC5C0_SET_RESERVED_SW_METHOD15_V                                                                    31:0
+
+#define NVC5C0_SET_SCG_CONTROL                                                                             0x0270
+#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT                                                          8:0
+#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT                                                        20:12
+#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE                                        24:24
+#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE                             0x00000000
+#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE                              0x00000001
+
+#define NVC5C0_SET_COMPUTE_CLASS_VERSION                                                                   0x0280
+#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT                                                             15:0
+#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                   31:16
+
+#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION                                                                 0x0284
+#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT                                                           15:0
+#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED                                                 31:16
+
+#define NVC5C0_SET_QMD_VERSION                                                                             0x0288
+#define NVC5C0_SET_QMD_VERSION_CURRENT                                                                       15:0
+#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED                                                             31:16
+
+#define NVC5C0_CHECK_QMD_VERSION                                                                           0x0290
+#define NVC5C0_CHECK_QMD_VERSION_CURRENT                                                                     15:0
+#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED                                                           31:16
+
+#define NVC5C0_INVALIDATE_SKED_CACHES                                                                      0x0298
+#define NVC5C0_INVALIDATE_SKED_CACHES_V                                                                       0:0
+
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL                                                              0x029c
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK                                            7:0
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE                                                 8:8
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE                                    0x00000000
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE                                     0x00000001
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE                                    12:12
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE                         0x00000000
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE                          0x00000001
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE                                              16:16
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE                                   0x00000000
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE                                    0x00000001
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE                                   20:20
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE                        0x00000000
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE                         0x00000001
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE                                              24:24
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE                                   0x00000000
+#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE                                    0x00000001
+
+#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A                                                           0x02a0
+#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                          16:0
+
+#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B                                                           0x02a4
+#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS                                                31:0
+
+#define NVC5C0_SCG_HYSTERESIS_CONTROL                                                                      0x02a8
+#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE                                                        0:0
+#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE                                           0x00000000
+#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE                                            0x00000001
+#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE                                                   1:1
+#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE                                      0x00000000
+#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE                                       0x00000001
+
+#define NVC5C0_SET_CWD_SLOT_COUNT                                                                          0x02b0
+#define NVC5C0_SET_CWD_SLOT_COUNT_V                                                                           7:0
+
+#define NVC5C0_SEND_PCAS_A                                                                                 0x02b4
+#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8                                                              31:0
+
+#define NVC5C0_SEND_PCAS_B                                                                                 0x02b8
+#define NVC5C0_SEND_PCAS_B_FROM                                                                              23:0
+#define NVC5C0_SEND_PCAS_B_DELTA                                                                            31:24
+
+#define NVC5C0_SEND_SIGNALING_PCAS_B                                                                       0x02bc
+#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE                                                               0:0
+#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE                                                  0x00000000
+#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE                                                   0x00000001
+#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE                                                                 1:1
+#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE                                                    0x00000000
+#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE                                                     0x00000001
+
+#define NVC5C0_SET_SKED_CACHE_CONTROL                                                                      0x02cc
+#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID                                                             0:0
+#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE                                                0x00000000
+#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE                                                 0x00000001
+
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A                                                     0x02e4
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER                                             7:0
+
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B                                                     0x02e8
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER                                            31:0
+
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C                                                     0x02ec
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT                                           8:0
+
+#define NVC5C0_SET_SPA_VERSION                                                                             0x0310
+#define NVC5C0_SET_SPA_VERSION_MINOR                                                                          7:0
+#define NVC5C0_SET_SPA_VERSION_MAJOR                                                                         15:8
+
+#define NVC5C0_SET_INLINE_QMD_ADDRESS_A                                                                    0x0318
+#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER                                           31:0
+
+#define NVC5C0_SET_INLINE_QMD_ADDRESS_B                                                                    0x031c
+#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER                                           31:0
+
+#define NVC5C0_LOAD_INLINE_QMD_DATA(i)                                                             (0x0320+(i)*4)
+#define NVC5C0_LOAD_INLINE_QMD_DATA_V                                                                        31:0
+
+#define NVC5C0_SET_FALCON00                                                                                0x0500
+#define NVC5C0_SET_FALCON00_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON01                                                                                0x0504
+#define NVC5C0_SET_FALCON01_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON02                                                                                0x0508
+#define NVC5C0_SET_FALCON02_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON03                                                                                0x050c
+#define NVC5C0_SET_FALCON03_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON04                                                                                0x0510
+#define NVC5C0_SET_FALCON04_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON05                                                                                0x0514
+#define NVC5C0_SET_FALCON05_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON06                                                                                0x0518
+#define NVC5C0_SET_FALCON06_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON07                                                                                0x051c
+#define NVC5C0_SET_FALCON07_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON08                                                                                0x0520
+#define NVC5C0_SET_FALCON08_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON09                                                                                0x0524
+#define NVC5C0_SET_FALCON09_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON10                                                                                0x0528
+#define NVC5C0_SET_FALCON10_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON11                                                                                0x052c
+#define NVC5C0_SET_FALCON11_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON12                                                                                0x0530
+#define NVC5C0_SET_FALCON12_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON13                                                                                0x0534
+#define NVC5C0_SET_FALCON13_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON14                                                                                0x0538
+#define NVC5C0_SET_FALCON14_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON15                                                                                0x053c
+#define NVC5C0_SET_FALCON15_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON16                                                                                0x0540
+#define NVC5C0_SET_FALCON16_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON17                                                                                0x0544
+#define NVC5C0_SET_FALCON17_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON18                                                                                0x0548
+#define NVC5C0_SET_FALCON18_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON19                                                                                0x054c
+#define NVC5C0_SET_FALCON19_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON20                                                                                0x0550
+#define NVC5C0_SET_FALCON20_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON21                                                                                0x0554
+#define NVC5C0_SET_FALCON21_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON22                                                                                0x0558
+#define NVC5C0_SET_FALCON22_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON23                                                                                0x055c
+#define NVC5C0_SET_FALCON23_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON24                                                                                0x0560
+#define NVC5C0_SET_FALCON24_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON25                                                                                0x0564
+#define NVC5C0_SET_FALCON25_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON26                                                                                0x0568
+#define NVC5C0_SET_FALCON26_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON27                                                                                0x056c
+#define NVC5C0_SET_FALCON27_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON28                                                                                0x0570
+#define NVC5C0_SET_FALCON28_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON29                                                                                0x0574
+#define NVC5C0_SET_FALCON29_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON30                                                                                0x0578
+#define NVC5C0_SET_FALCON30_V                                                                                31:0
+
+#define NVC5C0_SET_FALCON31                                                                                0x057c
+#define NVC5C0_SET_FALCON31_V                                                                                31:0
+
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A                                                                   0x0790
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER                                                       16:0
+
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B                                                                   0x0794
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER                                                       31:0
+
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A                                                            0x07b0
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER                                           16:0
+
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B                                                            0x07b4
+#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS                                                 31:0
+
+#define NVC5C0_SET_SHADER_CACHE_CONTROL                                                                    0x0d94
+#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE                                                0:0
+#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE                                   0x00000000
+#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE                                    0x00000001
+
+#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i)                                            (0x0da0+(i)*4)
+#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V                                                       31:0
+
+#define NVC5C0_SET_SM_TIMEOUT_INTERVAL                                                                     0x0de4
+#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT                                                            5:0
+
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI                                                        0x1288
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES                                                     0:0
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL                                          0x00000000
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE                                          0x00000001
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG                                                      25:4
+
+#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT                                                  0x12a8
+#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL                                                 0:0
+#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE                                    0x00000000
+#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE                                     0x00000001
+
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE                                                                    0x1330
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES                                                                 0:0
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL                                                      0x00000000
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE                                                      0x00000001
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG                                                                  25:4
+
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE                                                             0x1334
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES                                                          0:0
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL                                               0x00000000
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE                                               0x00000001
+#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG                                                           25:4
+
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE                                                               0x1338
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES                                                            0:0
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL                                                 0x00000000
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE                                                 0x00000001
+#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG                                                             25:4
+
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI                                                             0x1424
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES                                                          0:0
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL                                               0x00000000
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE                                               0x00000001
+#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG                                                           25:4
+
+#define NVC5C0_SET_SHADER_EXCEPTIONS                                                                       0x1528
+#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE                                                                   0:0
+#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE                                                      0x00000000
+#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE                                                       0x00000001
+
+#define NVC5C0_SET_RENDER_ENABLE_A                                                                         0x1550
+#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER                                                               7:0
+
+#define NVC5C0_SET_RENDER_ENABLE_B                                                                         0x1554
+#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER                                                              31:0
+
+#define NVC5C0_SET_RENDER_ENABLE_C                                                                         0x1558
+#define NVC5C0_SET_RENDER_ENABLE_C_MODE                                                                       2:0
+#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE                                                          0x00000000
+#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE                                                           0x00000001
+#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                                                    0x00000002
+#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                                                0x00000003
+#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                                            0x00000004
+
+#define NVC5C0_SET_TEX_SAMPLER_POOL_A                                                                      0x155c
+#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER                                                           16:0
+
+#define NVC5C0_SET_TEX_SAMPLER_POOL_B                                                                      0x1560
+#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER                                                           31:0
+
+#define NVC5C0_SET_TEX_SAMPLER_POOL_C                                                                      0x1564
+#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX                                                          19:0
+
+#define NVC5C0_SET_TEX_HEADER_POOL_A                                                                       0x1574
+#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER                                                            16:0
+
+#define NVC5C0_SET_TEX_HEADER_POOL_B                                                                       0x1578
+#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER                                                            31:0
+
+#define NVC5C0_SET_TEX_HEADER_POOL_C                                                                       0x157c
+#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX                                                           21:0
+
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI                                                             0x1698
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION                                                    0:0
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE                                       0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE                                        0x00000001
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA                                                    4:4
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE                                       0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE                                        0x00000001
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT                                                     12:12
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE                                          0x00000000
+#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE                                           0x00000001
+
+#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE                                                                  0x1944
+#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE                                                                1:0
+#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE                                       0x00000000
+#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER                                           0x00000001
+#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER                                            0x00000002
+
+#define NVC5C0_PIPE_NOP                                                                                    0x1a2c
+#define NVC5C0_PIPE_NOP_V                                                                                    31:0
+
+#define NVC5C0_SET_SPARE00                                                                                 0x1a30
+#define NVC5C0_SET_SPARE00_V                                                                                 31:0
+
+#define NVC5C0_SET_SPARE01                                                                                 0x1a34
+#define NVC5C0_SET_SPARE01_V                                                                                 31:0
+
+#define NVC5C0_SET_SPARE02                                                                                 0x1a38
+#define NVC5C0_SET_SPARE02_V                                                                                 31:0
+
+#define NVC5C0_SET_SPARE03                                                                                 0x1a3c
+#define NVC5C0_SET_SPARE03_V                                                                                 31:0
+
+#define NVC5C0_SET_REPORT_SEMAPHORE_A                                                                      0x1b00
+#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER                                                            7:0
+
+#define NVC5C0_SET_REPORT_SEMAPHORE_B                                                                      0x1b04
+#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER                                                           31:0
+
+#define NVC5C0_SET_REPORT_SEMAPHORE_C                                                                      0x1b08
+#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD                                                                31:0
+
+#define NVC5C0_SET_REPORT_SEMAPHORE_D                                                                      0x1b0c
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION                                                               1:0
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE                                                0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP                                                   0x00000003
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE                                                         20:20
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE                                              0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE                                               0x00000001
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE                                                        28:28
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS                                        0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD                                          0x00000001
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE                                                           2:2
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE                                              0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE                                               0x00000001
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE                                                        3:3
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE                                           0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE                                            0x00000001
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP                                                           11:9
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD                                             0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN                                             0x00000001
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX                                             0x00000002
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC                                             0x00000003
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC                                             0x00000004
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND                                             0x00000005
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR                                              0x00000006
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR                                             0x00000007
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT                                                      18:17
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32                                     0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32                                       0x00000001
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP                                                      19:19
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE                                           0x00000000
+#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE                                            0x00000001
+
+#define NVC5C0_SET_TRAP_HANDLER_A                                                                          0x25f8
+#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER                                                              16:0
+
+#define NVC5C0_SET_TRAP_HANDLER_B                                                                          0x25fc
+#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER                                                              31:0
+
+#define NVC5C0_SET_BINDLESS_TEXTURE                                                                        0x2608
+#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT                                               2:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i)                                    (0x32f4+(i)*4)
+#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V                                               31:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i)                              (0x3314+(i)*4)
+#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V                                         31:0
+
+#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                  0x3334
+#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                   0:0
+
+#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER                                                 0x3338
+#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V                                                  0:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i)                                       (0x333c+(i)*4)
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V                                                  31:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i)                                             (0x335c+(i)*4)
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V                                                        31:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i)                                             (0x337c+(i)*4)
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT                                                     7:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i)                                         (0x339c+(i)*4)
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0                                                1:0
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0                                           4:2
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1                                                6:5
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1                                           9:7
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2                                              11:10
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2                                         14:12
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3                                              16:15
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3                                         19:17
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4                                              21:20
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4                                         24:22
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5                                              26:25
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5                                         29:27
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE                                               31:30
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i)                                         (0x33bc+(i)*4)
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE                                                  0:0
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE                                                  2:1
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED                                              3:3
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC                                                 19:4
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL                                                 0x33dc
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK                                               7:0
+
+#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER                                                            0x33e0
+#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                  7:0
+
+#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER                                                             0x33e4
+#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK                                                   7:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER                                                  0x33e8
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V                                                  31:0
+
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER                                              0x33ec
+#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V                                              31:0
+
+#define NVC5C0_SET_MME_SHADOW_SCRATCH(i)                                                           (0x3400+(i)*4)
+#define NVC5C0_SET_MME_SHADOW_SCRATCH_V                                                                      31:0
+
+#endif /* _cl_turing_compute_a_h_ */
diff --git a/classes/compute/index.html b/classes/compute/index.html
new file mode 100644
index 0000000..19aa93f
--- /dev/null
+++ b/classes/compute/index.html
@@ -0,0 +1,18 @@
+<html>
+    <head><title>compute</title></head>
+    <body>
+        <h1>compute</h1>
+        <a href="cl50c0.h">cl50c0.h</a><br/>
+        <a href="cl85c0.h">cl85c0.h</a><br/>
+        <a href="cl90c0.h">cl90c0.h</a><br/>
+        <a href="cl91c0.h">cl91c0.h</a><br/>
+        <a href="cla0c0.h">cla0c0.h</a><br/>
+        <a href="cla1c0.h">cla1c0.h</a><br/>
+        <a href="clb0c0.h">clb0c0.h</a><br/>
+        <a href="clb1c0.h">clb1c0.h</a><br/>
+        <a href="clc0c0.h">clc0c0.h</a><br/>
+        <a href="clc1c0.h">clc1c0.h</a><br/>
+        <a href="clc3c0.h">clc3c0.h</a><br/>
+        <a href="clc5c0.h">clc5c0.h</a><br/>
+    </body>
+</html>
diff --git a/classes/display/README.txt b/classes/display/README.txt
new file mode 100644
index 0000000..ea97c6e
--- /dev/null
+++ b/classes/display/README.txt
@@ -0,0 +1,190 @@
+EVO CLASSES
+
+The NVIDIA "EVO" Display Engine was introduced in NV50, and has been
+incrementally updated in GPUs since then.
+
+EVO consists of several channels:
+
+    "core": This channel is used to perform modesets, as well as things
+            such as manage the LUT, and cursor properties (other than
+            position).  It has GPU scope.
+    "base": This channel is intended to be used for OpenGL SwapBuffers
+            flipping.  There is one base channel per head.
+    "overlay": This channel is intended to be used for flipping the
+            overlay.  There is one overlay channel per head.
+    "overlay immediate": This channel is intended to be used to position
+            the overlay within the raster of the head.  There is one
+            overlay immediate channel per head.  Originally, it was
+            conceived that a display driver would position the overlay
+            in response to a window move, using the "overlay immediate"
+            channel, and a video driver would flip buffers using the
+            overlay channel.
+    "cursor": This channel is used to position the cursor.  There is
+            one cursor channel per head.  The cursor format and buffer
+            is specified through the core channel.  It was originally
+            conceived that the management of cursor would be distributed
+            between the core and cursor channels in the same way that
+            overlay management is distributed between overlay and overlay
+            immediate channels.  The cursor channel allows low-latency
+            cursor position updates, asynchronously to the core channel.
+
+The "NVDisplay" Engine is new in Volta, and is a major improvement upon EVO.
+The software interface consists of a set of channels as in EVO, but how those
+channels can be used is more flexible.
+
+    "core": This channel is similar to EVO's core channel, except it does not
+            support programming a surface as a base layer.
+    "window": This channel replaces EVO's base and overlay channels.  It is
+            designed support a superset of the capabilities of the earlier
+            channels, but in addition supports scaling, alpha blending, and
+            blend order, among other improvements.  Windows are not inherently
+            bound to a head and must be bound explicitly with core channel
+            methods.
+    "window immediate": Like EVO's overlay immediate, this can be used to
+            position the corresponding window channel on the raster.  Unlike
+            EVO's overlay immediate, this is a DMA channel to support
+            enqueuing more than one update at a time.
+    "cursor": This is similar to EVO's cursor channel.  There is one cursor
+            per head.
+
+There is a per-channel header file that defines the method interface to
+each channel.
+
+There are both a "class name" and a software class number that are
+used to describe the combination of channel versions used together.
+
+The table below describes which class name is used with which GPU,
+and which channel header files are used with that class.
+
+__________________________________________________________________________
+
+Class Name:                 DISP010X
+Software Class Number:      5070
+Cursor Channel:             cl507a.h
+Overlay Immediate Channel:  cl507b.h
+Base Channel:               cl507c.h
+Core Channel:               cl507d.h
+Overlay Channel:            cl507e.h
+GPUs:                       nv50
+__________________________________________________________________________
+
+Class Name:                 DISP011X
+Software Class Number:      8270
+Cursor Channel:             cl827a.h
+Overlay Immediate Channel:  cl827b.h
+Base Channel:               cl827c.h
+Core Channel:               cl827d.h
+Overlay Channel:            cl827e.h
+GPUs:                       g84, g86, g92
+__________________________________________________________________________
+
+Class Name:                 DISP012X
+Software Class Number:      8370
+Cursor Channel:             cl827a.h
+Overlay Immediate Channel:  cl827b.h
+Base Channel:               cl837c.h
+Core Channel:               cl837d.h
+Overlay Channel:            cl837e.h
+GPUs:                       gt200
+__________________________________________________________________________
+
+Class Name:                 DISP014X
+Software Class Number:      8870
+Cursor Channel:             cl827a.h
+Overlay Immediate Channel:  cl827b.h
+Base Channel:               cl837c.h
+Core Channel:               cl887d.h
+Overlay Channel:            cl837e.h
+GPUs:                       g94, g96, g98, mcp7x
+__________________________________________________________________________
+
+Class Name:                 DISP015X
+Software Class Number:      8570
+Cursor Channel:             cl857a.h
+Overlay Immediate Channel:  cl857b.h
+Base Channel:               cl857c.h
+Core Channel:               cl857d.h
+Overlay Channel:            cl857e.h
+GPUs:                       gt215, gt216, gt218, mcp89
+                            gf100, gf104, gf106, gf114, gf116, gf108
+__________________________________________________________________________
+
+Class Name:                 DISP020X
+Software Class Number:      9070
+Cursor Channel:             cl907a.h
+Overlay Immediate Channel:  cl907b.h
+Base Channel:               cl907c.h
+Core Channel:               cl907d.h
+Overlay Channel:            cl907e.h
+GPUs:                       gf119
+__________________________________________________________________________
+
+Class Name:                 DISP021X
+Software Class Number:      9170
+Cursor Channel:             cl917a.h
+Overlay Immediate Channel:  cl917b.h
+Base Channel:               cl917c.h
+Core Channel:               cl917d.h
+Overlay Channel:            cl917e.h
+GPUs:                       gk104, gk106, gk107
+__________________________________________________________________________
+
+Class Name:                 DISP022X
+Software Class Number:      9270
+Cursor Channel:             cl917a.h
+Overlay Immediate Channel:  cl917b.h
+Base Channel:               cl927c.h
+Core Channel:               cl927d.h
+Overlay Channel:            cl917e.h
+GPUs:                       gk110, gk208
+__________________________________________________________________________
+
+Class Name:                 DISP024X
+Software Class Number:      9470
+Cursor Channel:             cl917a.h
+Overlay Immediate Channel:  cl917b.h
+Base Channel:               cl927c.h
+Core Channel:               cl947d.h
+Overlay Channel:            cl917e.h
+GPUs:                       gm107, gm108
+__________________________________________________________________________
+
+Class Name:                 DISP025X
+Software Class Number:      9570
+Cursor Channel:             cl917a.h
+Overlay Immediate Channel:  cl917b.h
+Base Channel:               cl927c.h
+Core Channel:               cl957d.h
+Overlay Channel:            cl917e.h
+GPUs:                       gm200, gm204, gm206
+__________________________________________________________________________
+
+Class Name:                 DISP027X
+Software Class Number:      9770
+Cursor Channel:             cl917a.h
+Overlay Immediate Channel:  cl917b.h
+Base Channel:               cl927c.h
+Core Channel:               cl977d.h
+Overlay Channel:            cl917e.h
+GPUs:                       gp100
+__________________________________________________________________________
+
+Class Name:                 DISP028X
+Software Class Number:      9870
+Cursor Channel:             cl917a.h
+Overlay Immediate Channel:  cl917b.h
+Base Channel:               cl927c.h
+Core Channel:               cl987d.h
+Overlay Channel:            cl917e.h
+GPUs:                       gp102, gp104, gp106, gp107, gp108
+__________________________________________________________________________
+
+Class Name:                 NVD_20
+Software Class Number:      C370
+Cursor Channel:             clc37a.h
+Window Immediate Channel:   clc37b.h
+Core Channel:               clc37d.h
+Window Channel:             clc37e.h
+GPUs:                       gv100
+__________________________________________________________________________
+
diff --git a/classes/display/cl507a.h b/classes/display/cl507a.h
new file mode 100644
index 0000000..d2c38f4
--- /dev/null
+++ b/classes/display/cl507a.h
@@ -0,0 +1,56 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl507a_h_
+#define _cl507a_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV507A_CURSOR_CHANNEL_PIO                                               (0x0000507A)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
+    NvV32 Reserved02[0x3DE];
+} Nv50DispCursorControlPio;
+
+#define NV507A_FREE                                                             (0x00000008)
+#define NV507A_FREE_COUNT                                                       5:0
+#define NV507A_UPDATE                                                           (0x00000080)
+#define NV507A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV507A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV507A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
+#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
+#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl507a_h
+
diff --git a/classes/display/cl507b.h b/classes/display/cl507b.h
new file mode 100644
index 0000000..460bc27
--- /dev/null
+++ b/classes/display/cl507b.h
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl507b_h_
+#define _cl507b_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV507B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000507B)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
+    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
+    NvV32 Reserved02[0x3DD];
+} Nv50DispOverlayImmControlPio;
+
+#define NV507B_FREE                                                             (0x00000008)
+#define NV507B_FREE_COUNT                                                       5:0
+#define NV507B_UPDATE                                                           (0x00000080)
+#define NV507B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV507B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV507B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV507B_SET_POINT_OUT                                                    (0x00000084)
+#define NV507B_SET_POINT_OUT_X                                                  15:0
+#define NV507B_SET_POINT_OUT_Y                                                  31:16
+#define NV507B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
+#define NV507B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl507b_h
+
diff --git a/classes/display/cl507c.h b/classes/display/cl507c.h
new file mode 100644
index 0000000..db9aba5
--- /dev/null
+++ b/classes/display/cl507c.h
@@ -0,0 +1,194 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl507c_h_
+#define _cl507c_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV507C_BASE_CHANNEL_DMA                                                 (0x0000507C)
+
+#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
+#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
+#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
+
+
+// dma opcode instructions
+#define NV507C_DMA                                     0x00000000 
+#define NV507C_DMA_OPCODE                                   31:29 
+#define NV507C_DMA_OPCODE_METHOD                       0x00000000 
+#define NV507C_DMA_OPCODE_JUMP                         0x00000001 
+#define NV507C_DMA_OPCODE_NONINC_METHOD                0x00000002 
+#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
+#define NV507C_DMA_OPCODE                                   31:29 
+#define NV507C_DMA_OPCODE_METHOD                       0x00000000 
+#define NV507C_DMA_OPCODE_NONINC_METHOD                0x00000002 
+#define NV507C_DMA_METHOD_COUNT                             27:18 
+#define NV507C_DMA_METHOD_OFFSET                             11:2 
+#define NV507C_DMA_DATA                                      31:0 
+#define NV507C_DMA_NOP                                 0x00000000 
+#define NV507C_DMA_OPCODE                                   31:29 
+#define NV507C_DMA_OPCODE_JUMP                         0x00000001 
+#define NV507C_DMA_JUMP_OFFSET                               11:2 
+#define NV507C_DMA_OPCODE                                   31:29 
+#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
+#define NV507C_DMA_SET_SUBDEVICE_MASK_VALUE                  11:0 
+
+// class methods
+#define NV507C_PUT                                                              (0x00000000)
+#define NV507C_PUT_PTR                                                          11:2
+#define NV507C_GET                                                              (0x00000004)
+#define NV507C_GET_PTR                                                          11:2
+#define NV507C_GET_SCANLINE                                                     (0x00000010)
+#define NV507C_GET_SCANLINE_LINE                                                15:0
+#define NV507C_UPDATE                                                           (0x00000080)
+#define NV507C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV507C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV507C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV507C_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
+#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
+#define NV507C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV507C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
+#define NV507C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
+#define NV507C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
+#define NV507C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV507C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
+#define NV507C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV507C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
+#define NV507C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV507C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV507C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV507C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV507C_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV507C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV507C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV507C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV507C_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
+#define NV507C_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
+#define NV507C_SET_BASE_LUT_LO                                                  (0x000000E0)
+#define NV507C_SET_BASE_LUT_LO_ENABLE                                           31:30
+#define NV507C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
+#define NV507C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
+#define NV507C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
+#define NV507C_SET_BASE_LUT_LO_MODE                                             29:29
+#define NV507C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
+#define NV507C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
+#define NV507C_SET_BASE_LUT_LO_ORIGIN                                           7:2
+#define NV507C_SET_BASE_LUT_HI                                                  (0x000000E4)
+#define NV507C_SET_BASE_LUT_HI_ORIGIN                                           31:0
+#define NV507C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
+#define NV507C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
+#define NV507C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
+#define NV507C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
+#define NV507C_SET_OUTPUT_LUT_LO_MODE                                           30:30
+#define NV507C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
+#define NV507C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
+#define NV507C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
+#define NV507C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
+#define NV507C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
+#define NV507C_SET_PROCESSING                                                   (0x00000110)
+#define NV507C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV507C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV507C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV507C_SET_CONVERSION                                                   (0x00000114)
+#define NV507C_SET_CONVERSION_GAIN                                              15:0
+#define NV507C_SET_CONVERSION_OFS                                               31:16
+#define NV507C_SET_SPARE                                                        (0x000007BC)
+#define NV507C_SET_SPARE_UNUSED                                                 31:0
+#define NV507C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV507C_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV507C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
+#define NV507C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV507C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
+#define NV507C_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV507C_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV507C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
+#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV507C_SURFACE_SET_STORAGE_PITCH                                        17:8
+#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV507C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
+#define NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
+#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
+#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
+#define NV507C_SURFACE_SET_PARAMS_GAMMA                                         2:2
+#define NV507C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
+#define NV507C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
+#define NV507C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
+#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
+#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
+#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
+#define NV507C_SURFACE_SET_PARAMS_KIND                                          22:16
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_PITCH                               (0x00000000)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2                        (0x00000070)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ               (0x00000072)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1                       (0x00000074)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ              (0x00000076)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4                             (0x00000078)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8                             (0x00000079)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ                    (0x0000007A)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ                    (0x0000007B)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4                             (0x0000007C)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8                             (0x0000007D)
+#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4                            (0x0000007E)
+#define NV507C_SURFACE_SET_PARAMS_KIND_FROM_PTE                                 (0x0000007F)
+#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE                                   24:24
+#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256                    (0x00000000)
+#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024                   (0x00000001)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl507c_h
+
diff --git a/classes/display/cl507d.h b/classes/display/cl507d.h
new file mode 100644
index 0000000..675b9e4
--- /dev/null
+++ b/classes/display/cl507d.h
@@ -0,0 +1,676 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl507d_h_
+#define _cl507d_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV507D_CORE_CHANNEL_DMA                                                 (0x0000507D)
+
+#define NV_DISP_CORE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_SIZEOF                                               0x00000054
+#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0                                         0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE                                    0:0
+#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0                                      15:1
+#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP                               29:16
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1                                       0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE                                  0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE                            0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE                             0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO                         1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_R0                                    3:3
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_R1                                    31:22
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_2                                       0x00000002
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_2_R2                                    31:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_3                                       0x00000003
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_3_R3                                    31:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_4                                       0x00000004
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_4_R4                                    31:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5                              0x00000005
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE                   0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE             0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE              0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE                    1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE              0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE               0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE                 3:3
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE           0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE            0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6                              0x00000006
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE                   0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE             0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE              0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE                    1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE              0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE               0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE                 3:3
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE           0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE            0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7                              0x00000007
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE                   0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE             0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE              0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE                    1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE              0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE               0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE                 3:3
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE           0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE            0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8                              0x00000008
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18                0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24                1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18                  2:2
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE            0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE             0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24                  3:3
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE            0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE             0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A                4:4
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B                5:5
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS             6:6
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE       0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE        0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS                    7:7
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE              0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE               0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI                          9:9
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE                    0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE                     0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9                              0x00000009
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18                0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24                1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18                  2:2
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE            0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE             0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24                  3:3
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE            0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE             0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A                4:4
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B                5:5
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE          0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE           0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS             6:6
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE       0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE        0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS                    7:7
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE              0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE               0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI                          9:9
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE                    0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE                     0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10                            0x0000000A
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC               0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC                 1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE           0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE            0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11                            0x0000000B
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC               0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC                 1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE           0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE            0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12                            0x0000000C
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC               0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC                 1:1
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE           0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE            0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13                            0x0000000D
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE                     0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE               0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE                0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0                         31:2
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14                            0x0000000E
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444          14:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1                         15:15
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422          30:16
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2                         31:31
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15                            0x0000000F
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444          14:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3                         15:15
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422          30:16
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4                         31:31
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16                            0x00000010
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444          14:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5                         15:15
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422          30:16
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6                         31:31
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17                            0x00000011
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE                     0:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE               0x00000000
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE                0x00000001
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0                         31:2
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18                            0x00000012
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444          14:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1                         15:15
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422          30:16
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2                         31:31
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19                            0x00000013
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444          14:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3                         15:15
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422          30:16
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4                         31:31
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20                            0x00000014
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444          14:0
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5                         15:15
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422          30:16
+#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6                         31:31
+
+
+// dma opcode instructions
+#define NV507D_DMA                                     0x00000000 
+#define NV507D_DMA_OPCODE                                   31:29 
+#define NV507D_DMA_OPCODE_METHOD                       0x00000000 
+#define NV507D_DMA_OPCODE_JUMP                         0x00000001 
+#define NV507D_DMA_OPCODE_NONINC_METHOD                0x00000002 
+#define NV507D_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
+#define NV507D_DMA_OPCODE                                   31:29 
+#define NV507D_DMA_OPCODE_METHOD                       0x00000000 
+#define NV507D_DMA_OPCODE_NONINC_METHOD                0x00000002 
+#define NV507D_DMA_METHOD_COUNT                             27:18 
+#define NV507D_DMA_METHOD_OFFSET                             11:2 
+#define NV507D_DMA_DATA                                      31:0 
+#define NV507D_DMA_NOP                                 0x00000000 
+#define NV507D_DMA_OPCODE                                   31:29 
+#define NV507D_DMA_OPCODE_JUMP                         0x00000001 
+#define NV507D_DMA_JUMP_OFFSET                               11:2 
+#define NV507D_DMA_OPCODE                                   31:29 
+#define NV507D_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
+#define NV507D_DMA_SET_SUBDEVICE_MASK_VALUE                  11:0 
+
+// class methods
+#define NV507D_PUT                                                              (0x00000000)
+#define NV507D_PUT_PTR                                                          11:2
+#define NV507D_GET                                                              (0x00000004)
+#define NV507D_GET_PTR                                                          11:2
+#define NV507D_UPDATE                                                           (0x00000080)
+#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
+#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV507D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV507D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
+#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV507D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV507D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV507D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV507D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV507D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV507D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV507D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV507D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV507D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV507D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV507D_SET_SPARE                                                        (0x000003BC)
+#define NV507D_SET_SPARE_UNUSED                                                 31:0
+#define NV507D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV507D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV507D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
+#define NV507D_DAC_SET_CONTROL_OWNER                                            3:0
+#define NV507D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV507D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV507D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV507D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV507D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV507D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL                                         13:8
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
+#define NV507D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
+#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
+#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
+#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
+#define NV507D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
+#define NV507D_DAC_SET_POLARITY_HSYNC                                           0:0
+#define NV507D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV507D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV507D_DAC_SET_POLARITY_VSYNC                                           1:1
+#define NV507D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV507D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV507D_DAC_SET_POLARITY_RESERVED                                        31:2
+#define NV507D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
+#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
+#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
+#define NV507D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
+#define NV507D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
+#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
+
+#define NV507D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
+#define NV507D_SOR_SET_CONTROL_OWNER                                            3:0
+#define NV507D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV507D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV507D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV507D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV507D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV507D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
+#define NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
+#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
+#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+
+#define NV507D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
+#define NV507D_PIOR_SET_CONTROL_OWNER                                           3:0
+#define NV507D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
+#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
+#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
+#define NV507D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
+#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
+#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
+#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
+#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
+#define NV507D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
+#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
+#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+
+#define NV507D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
+#define NV507D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV507D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV507D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
+#define NV507D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
+#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
+#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
+#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
+#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
+#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
+#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
+#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
+#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
+#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
+#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
+#define NV507D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
+#define NV507D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
+#define NV507D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV507D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
+#define NV507D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV507D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV507D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV507D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
+#define NV507D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV507D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV507D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
+#define NV507D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV507D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV507D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
+#define NV507D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV507D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV507D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
+#define NV507D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV507D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV507D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
+#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
+#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
+#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
+#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV507D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
+#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV507D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
+#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV507D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
+#define NV507D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
+#define NV507D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
+#define NV507D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
+#define NV507D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV507D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
+#define NV507D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV507D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
+#define NV507D_HEAD_SET_SIZE_WIDTH                                              14:0
+#define NV507D_HEAD_SET_SIZE_HEIGHT                                             30:16
+#define NV507D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
+#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV507D_HEAD_SET_STORAGE_PITCH                                           17:8
+#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
+#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV507D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
+#define NV507D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV507D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV507D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV507D_HEAD_SET_PARAMS_KIND                                             22:16
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH                                  (0x00000000)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2                           (0x00000070)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ                  (0x00000072)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1                          (0x00000074)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ                 (0x00000076)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4                                (0x00000078)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8                                (0x00000079)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ                       (0x0000007A)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ                       (0x0000007B)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS4                                (0x0000007C)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS8                                (0x0000007D)
+#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C128_MS4                               (0x0000007E)
+#define NV507D_HEAD_SET_PARAMS_KIND_FROM_PTE                                    (0x0000007F)
+#define NV507D_HEAD_SET_PARAMS_PART_STRIDE                                      24:24
+#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256                       (0x00000000)
+#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024                      (0x00000001)
+#define NV507D_HEAD_SET_CONTEXT_DMA_ISO(a)                                      (0x00000874 + (a)*0x00000400)
+#define NV507D_HEAD_SET_CONTEXT_DMA_ISO_HANDLE                                  31:0
+#define NV507D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
+#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
+#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
+#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
+#define NV507D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
+#define NV507D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
+#define NV507D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
+#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV507D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV507D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV507D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV507D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
+#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV507D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV507D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV507D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
+#define NV507D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
+#define NV507D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
+#define NV507D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
+#define NV507D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
+#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
+#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV507D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
+#define NV507D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV507D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV507D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl507d_h
+
diff --git a/classes/display/cl507e.h b/classes/display/cl507e.h
new file mode 100644
index 0000000..1827276
--- /dev/null
+++ b/classes/display/cl507e.h
@@ -0,0 +1,173 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl507e_h_
+#define _cl507e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV507E_OVERLAY_CHANNEL_DMA                                              (0x0000507E)
+
+#define NV_DISP_OVERLAY_NOTIFIER_1                                                   0x00000000
+#define NV_DISP_OVERLAY_NOTIFIER_1_SIZEOF                                            0x00000008
+#define NV_DISP_OVERLAY_NOTIFIER_1__0                                                0x00000000
+#define NV_DISP_OVERLAY_NOTIFIER_1__0_PRESENT_COUNT                                  15:0
+#define NV_DISP_OVERLAY_NOTIFIER_1__0_TIMESTAMP                                      29:16
+#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS                                         31:30
+#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_NOT_BEGUN                               0x00000000
+#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_BEGUN                                   0x00000001
+#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_FINISHED                                0x00000002
+#define NV_DISP_OVERLAY_NOTIFIER_1__1                                                0x00000001
+#define NV_DISP_OVERLAY_NOTIFIER_1__1_PRESENT_START_TIME                             31:0
+
+
+// dma opcode instructions
+#define NV507E_DMA                                     0x00000000 
+#define NV507E_DMA_OPCODE                                   31:29 
+#define NV507E_DMA_OPCODE_METHOD                       0x00000000 
+#define NV507E_DMA_OPCODE_JUMP                         0x00000001 
+#define NV507E_DMA_OPCODE_NONINC_METHOD                0x00000002 
+#define NV507E_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
+#define NV507E_DMA_OPCODE                                   31:29 
+#define NV507E_DMA_OPCODE_METHOD                       0x00000000 
+#define NV507E_DMA_OPCODE_NONINC_METHOD                0x00000002 
+#define NV507E_DMA_METHOD_COUNT                             27:18 
+#define NV507E_DMA_METHOD_OFFSET                             11:2 
+#define NV507E_DMA_DATA                                      31:0 
+#define NV507E_DMA_NOP                                 0x00000000 
+#define NV507E_DMA_OPCODE                                   31:29 
+#define NV507E_DMA_OPCODE_JUMP                         0x00000001 
+#define NV507E_DMA_JUMP_OFFSET                               11:2 
+#define NV507E_DMA_OPCODE                                   31:29 
+#define NV507E_DMA_OPCODE_SET_SUBDEVICE_MASK           0x00000003 
+#define NV507E_DMA_SET_SUBDEVICE_MASK_VALUE                  11:0 
+
+// class methods
+#define NV507E_PUT                                                              (0x00000000)
+#define NV507E_PUT_PTR                                                          11:2
+#define NV507E_GET                                                              (0x00000004)
+#define NV507E_GET_PTR                                                          11:2
+#define NV507E_UPDATE                                                           (0x00000080)
+#define NV507E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV507E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV507E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV507E_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
+#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
+#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
+#define NV507E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV507E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
+#define NV507E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV507E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
+#define NV507E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV507E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
+#define NV507E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV507E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV507E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV507E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV507E_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV507E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV507E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV507E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV507E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV507E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV507E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
+#define NV507E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
+#define NV507E_SET_POINT_IN                                                     (0x000000E0)
+#define NV507E_SET_POINT_IN_X                                                   14:0
+#define NV507E_SET_POINT_IN_Y                                                   30:16
+#define NV507E_SET_SIZE_IN                                                      (0x000000E4)
+#define NV507E_SET_SIZE_IN_WIDTH                                                14:0
+#define NV507E_SET_SIZE_IN_HEIGHT                                               30:16
+#define NV507E_SET_SIZE_OUT                                                     (0x000000E8)
+#define NV507E_SET_SIZE_OUT_WIDTH                                               14:0
+#define NV507E_SET_COMPOSITION_CONTROL                                          (0x00000100)
+#define NV507E_SET_COMPOSITION_CONTROL_MODE                                     3:0
+#define NV507E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
+#define NV507E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
+#define NV507E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
+#define NV507E_SET_KEY_COLOR                                                    (0x00000104)
+#define NV507E_SET_KEY_COLOR_COLOR                                              31:0
+#define NV507E_SET_KEY_MASK                                                     (0x00000108)
+#define NV507E_SET_KEY_MASK_MASK                                                31:0
+#define NV507E_SET_TIMESTAMP_VALUE                                              (0x00000120)
+#define NV507E_SET_TIMESTAMP_VALUE_TIMESTAMP                                    31:0
+#define NV507E_SET_UPDATE_TIMESTAMP                                             (0x00000124)
+#define NV507E_SET_UPDATE_TIMESTAMP_TIMESTAMP                                   31:0
+#define NV507E_SET_SPARE                                                        (0x000007BC)
+#define NV507E_SET_SPARE_UNUSED                                                 31:0
+#define NV507E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV507E_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV507E_SURFACE_SET_OFFSET                                               (0x00000800)
+#define NV507E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV507E_SURFACE_SET_SIZE                                                 (0x00000808)
+#define NV507E_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV507E_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV507E_SURFACE_SET_STORAGE                                              (0x0000080C)
+#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV507E_SURFACE_SET_STORAGE_PITCH                                        17:8
+#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV507E_SURFACE_SET_PARAMS                                               (0x00000810)
+#define NV507E_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
+#define NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
+#define NV507E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV507E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
+#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
+#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
+#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
+#define NV507E_SURFACE_SET_PARAMS_KIND                                          22:16
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_PITCH                               (0x00000000)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2                        (0x00000070)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ               (0x00000072)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1                       (0x00000074)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ              (0x00000076)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4                             (0x00000078)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8                             (0x00000079)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ                    (0x0000007A)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ                    (0x0000007B)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4                             (0x0000007C)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8                             (0x0000007D)
+#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4                            (0x0000007E)
+#define NV507E_SURFACE_SET_PARAMS_KIND_FROM_PTE                                 (0x0000007F)
+#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE                                   24:24
+#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256                    (0x00000000)
+#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024                   (0x00000001)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl507e_h
+
diff --git a/classes/display/cl827a.h b/classes/display/cl827a.h
new file mode 100644
index 0000000..bd10ceb
--- /dev/null
+++ b/classes/display/cl827a.h
@@ -0,0 +1,56 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl827a_h_
+#define _cl827a_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV827A_CURSOR_CHANNEL_PIO                                               (0x0000827A)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
+    NvV32 Reserved02[0x3DE];
+} G82DispCursorControlPio;
+
+#define NV827A_FREE                                                             (0x00000008)
+#define NV827A_FREE_COUNT                                                       5:0
+#define NV827A_UPDATE                                                           (0x00000080)
+#define NV827A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV827A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV827A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
+#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
+#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl827a_h
+
diff --git a/classes/display/cl827b.h b/classes/display/cl827b.h
new file mode 100644
index 0000000..f85bfc2
--- /dev/null
+++ b/classes/display/cl827b.h
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl827b_h_
+#define _cl827b_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV827B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000827B)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
+    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
+    NvV32 Reserved02[0x3DD];
+} G82DispOverlayImmControlPio;
+
+#define NV827B_FREE                                                             (0x00000008)
+#define NV827B_FREE_COUNT                                                       5:0
+#define NV827B_UPDATE                                                           (0x00000080)
+#define NV827B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV827B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV827B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV827B_SET_POINT_OUT                                                    (0x00000084)
+#define NV827B_SET_POINT_OUT_X                                                  15:0
+#define NV827B_SET_POINT_OUT_Y                                                  31:16
+#define NV827B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
+#define NV827B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl827b_h
+
diff --git a/classes/display/cl827c.h b/classes/display/cl827c.h
new file mode 100644
index 0000000..a92df84
--- /dev/null
+++ b/classes/display/cl827c.h
@@ -0,0 +1,181 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl827c_h_
+#define _cl827c_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV827C_BASE_CHANNEL_DMA                                                 (0x0000827C)
+
+#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
+#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
+#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
+
+
+// dma opcode instructions
+#define NV827C_DMA                                                         0x00000000 
+#define NV827C_DMA_OPCODE                                                       31:29 
+#define NV827C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV827C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV827C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV827C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV827C_DMA_OPCODE                                                       31:29 
+#define NV827C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV827C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV827C_DMA_METHOD_COUNT                                                 27:18 
+#define NV827C_DMA_METHOD_OFFSET                                                 11:2 
+#define NV827C_DMA_DATA                                                          31:0 
+#define NV827C_DMA_NOP                                                     0x00000000 
+#define NV827C_DMA_OPCODE                                                       31:29 
+#define NV827C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV827C_DMA_JUMP_OFFSET                                                   11:2 
+#define NV827C_DMA_OPCODE                                                       31:29 
+#define NV827C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV827C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV827C_PUT                                                              (0x00000000)
+#define NV827C_PUT_PTR                                                          11:2
+#define NV827C_GET                                                              (0x00000004)
+#define NV827C_GET_PTR                                                          11:2
+#define NV827C_GET_SCANLINE                                                     (0x00000010)
+#define NV827C_GET_SCANLINE_LINE                                                15:0
+#define NV827C_UPDATE                                                           (0x00000080)
+#define NV827C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV827C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV827C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV827C_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
+#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
+#define NV827C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV827C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
+#define NV827C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
+#define NV827C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
+#define NV827C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV827C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
+#define NV827C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV827C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
+#define NV827C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV827C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV827C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV827C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV827C_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV827C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV827C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV827C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV827C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV827C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV827C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
+#define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
+#define NV827C_SET_BASE_LUT_LO                                                  (0x000000E0)
+#define NV827C_SET_BASE_LUT_LO_ENABLE                                           31:30
+#define NV827C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
+#define NV827C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
+#define NV827C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
+#define NV827C_SET_BASE_LUT_LO_MODE                                             29:29
+#define NV827C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
+#define NV827C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
+#define NV827C_SET_BASE_LUT_LO_ORIGIN                                           7:2
+#define NV827C_SET_BASE_LUT_HI                                                  (0x000000E4)
+#define NV827C_SET_BASE_LUT_HI_ORIGIN                                           31:0
+#define NV827C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
+#define NV827C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
+#define NV827C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
+#define NV827C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
+#define NV827C_SET_OUTPUT_LUT_LO_MODE                                           30:30
+#define NV827C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
+#define NV827C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
+#define NV827C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
+#define NV827C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
+#define NV827C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
+#define NV827C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
+#define NV827C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV827C_SET_PROCESSING                                                   (0x00000110)
+#define NV827C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV827C_SET_CONVERSION                                                   (0x00000114)
+#define NV827C_SET_CONVERSION_GAIN                                              15:0
+#define NV827C_SET_CONVERSION_OFS                                               31:16
+#define NV827C_SET_SPARE                                                        (0x000007BC)
+#define NV827C_SET_SPARE_UNUSED                                                 31:0
+#define NV827C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV827C_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV827C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
+#define NV827C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV827C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
+#define NV827C_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV827C_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV827C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
+#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV827C_SURFACE_SET_STORAGE_PITCH                                        17:8
+#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV827C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
+#define NV827C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
+#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
+#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
+#define NV827C_SURFACE_SET_PARAMS_GAMMA                                         2:2
+#define NV827C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
+#define NV827C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
+#define NV827C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
+#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
+#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
+#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
+#define NV827C_SURFACE_SET_PARAMS_RESERVED0                                     22:16
+#define NV827C_SURFACE_SET_PARAMS_RESERVED1                                     24:24
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl827c_h
+
diff --git a/classes/display/cl827d.h b/classes/display/cl827d.h
new file mode 100644
index 0000000..7294769
--- /dev/null
+++ b/classes/display/cl827d.h
@@ -0,0 +1,678 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl827d_h_
+#define _cl827d_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV827D_CORE_CHANNEL_DMA                                                 (0x0000827D)
+
+#define NV827D_CORE_NOTIFIER_1                                                      0x00000000
+#define NV827D_CORE_NOTIFIER_1_SIZEOF                                               0x00000054
+#define NV827D_CORE_NOTIFIER_1_COMPLETION_0                                         0x00000000
+#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE                                    0:0
+#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_R0                                      15:1
+#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP                               29:16
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1                                       0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE                                  0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE                            0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE                             0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO                         1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_R0                                    3:3
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_R1                                    31:22
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_2                                       0x00000002
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_2_R2                                    31:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_3                                       0x00000003
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_3_R3                                    31:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_4                                       0x00000004
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_4_R4                                    31:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5                              0x00000005
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE                   0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE             0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE              0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE                    1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE              0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE               0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE                 3:3
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE           0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE            0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6                              0x00000006
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE                   0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE             0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE              0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE                    1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE              0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE               0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE                 3:3
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE           0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE            0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7                              0x00000007
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE                   0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE             0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE              0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE                    1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE              0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE               0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE                 3:3
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE           0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE            0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8                              0x00000008
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18                0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24                1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18                  2:2
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE            0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE             0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24                  3:3
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE            0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE             0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A                4:4
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B                5:5
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS             6:6
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE       0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE        0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS                    7:7
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE              0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE               0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI                          9:9
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE                    0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE                     0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9                              0x00000009
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18                0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24                1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18                  2:2
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE            0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE             0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24                  3:3
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE            0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE             0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A                4:4
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B                5:5
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE          0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE           0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS             6:6
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE       0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE        0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS                    7:7
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE              0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE               0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI                          9:9
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE                    0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE                     0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10                            0x0000000A
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC               0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC                 1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE           0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE            0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11                            0x0000000B
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC               0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC                 1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE           0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE            0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12                            0x0000000C
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC               0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC                 1:1
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE           0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE            0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13                            0x0000000D
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE                     0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE               0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE                0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0                         31:2
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14                            0x0000000E
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444          14:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1                         15:15
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422          30:16
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2                         31:31
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15                            0x0000000F
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444          14:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3                         15:15
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422          30:16
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4                         31:31
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16                            0x00000010
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444          14:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5                         15:15
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422          30:16
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6                         31:31
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17                            0x00000011
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE                     0:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE               0x00000000
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE                0x00000001
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0                         31:2
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18                            0x00000012
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444          14:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1                         15:15
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422          30:16
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2                         31:31
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19                            0x00000013
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444          14:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3                         15:15
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422          30:16
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4                         31:31
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20                            0x00000014
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444          14:0
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5                         15:15
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422          30:16
+#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6                         31:31
+
+
+// dma opcode instructions
+#define NV827D_DMA                                                         0x00000000 
+#define NV827D_DMA_OPCODE                                                       31:29 
+#define NV827D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV827D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV827D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV827D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV827D_DMA_OPCODE                                                       31:29 
+#define NV827D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV827D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV827D_DMA_METHOD_COUNT                                                 27:18 
+#define NV827D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV827D_DMA_DATA                                                          31:0 
+#define NV827D_DMA_NOP                                                     0x00000000 
+#define NV827D_DMA_OPCODE                                                       31:29 
+#define NV827D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV827D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV827D_DMA_OPCODE                                                       31:29 
+#define NV827D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV827D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV827D_PUT                                                              (0x00000000)
+#define NV827D_PUT_PTR                                                          11:2
+#define NV827D_GET                                                              (0x00000004)
+#define NV827D_GET_PTR                                                          11:2
+#define NV827D_UPDATE                                                           (0x00000080)
+#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
+#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV827D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV827D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV827D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
+#define NV827D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV827D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV827D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV827D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV827D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV827D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV827D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV827D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV827D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV827D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV827D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV827D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV827D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV827D_SET_SPARE                                                        (0x000003BC)
+#define NV827D_SET_SPARE_UNUSED                                                 31:0
+#define NV827D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV827D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV827D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
+#define NV827D_DAC_SET_CONTROL_OWNER                                            3:0
+#define NV827D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV827D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV827D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV827D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV827D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV827D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV827D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV827D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL                                         13:8
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
+#define NV827D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
+#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
+#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
+#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
+#define NV827D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
+#define NV827D_DAC_SET_POLARITY_HSYNC                                           0:0
+#define NV827D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV827D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV827D_DAC_SET_POLARITY_VSYNC                                           1:1
+#define NV827D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV827D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV827D_DAC_SET_POLARITY_RESERVED                                        31:2
+#define NV827D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
+#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
+#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
+#define NV827D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
+#define NV827D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
+#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
+
+#define NV827D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
+#define NV827D_SOR_SET_CONTROL_OWNER                                            3:0
+#define NV827D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV827D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV827D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV827D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV827D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV827D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV827D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV827D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
+#define NV827D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
+#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
+#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+
+#define NV827D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
+#define NV827D_PIOR_SET_CONTROL_OWNER                                           3:0
+#define NV827D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
+#define NV827D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
+#define NV827D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
+#define NV827D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
+#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
+#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
+#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
+#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
+#define NV827D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV827D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV827D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
+#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
+#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+
+#define NV827D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
+#define NV827D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV827D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV827D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
+#define NV827D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
+#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
+#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
+#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
+#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
+#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
+#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
+#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
+#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
+#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
+#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
+#define NV827D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
+#define NV827D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
+#define NV827D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV827D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
+#define NV827D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV827D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV827D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV827D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
+#define NV827D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV827D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV827D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
+#define NV827D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV827D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV827D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
+#define NV827D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV827D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV827D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
+#define NV827D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV827D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV827D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
+#define NV827D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV827D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV827D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
+#define NV827D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
+#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
+#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV827D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
+#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV827D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
+#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV827D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
+#define NV827D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
+#define NV827D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
+#define NV827D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
+#define NV827D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV827D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
+#define NV827D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV827D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
+#define NV827D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV827D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
+#define NV827D_HEAD_SET_SIZE_WIDTH                                              14:0
+#define NV827D_HEAD_SET_SIZE_HEIGHT                                             30:16
+#define NV827D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
+#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV827D_HEAD_SET_STORAGE_PITCH                                           17:8
+#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
+#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV827D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
+#define NV827D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV827D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV827D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV827D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV827D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV827D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV827D_HEAD_SET_PARAMS_RESERVED0                                        22:16
+#define NV827D_HEAD_SET_PARAMS_RESERVED1                                        24:24
+#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
+#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV827D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
+#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
+#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
+#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
+#define NV827D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
+#define NV827D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
+#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
+#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
+#define NV827D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
+#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV827D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV827D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV827D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV827D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV827D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV827D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
+#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV827D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV827D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV827D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
+#define NV827D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
+#define NV827D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
+#define NV827D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
+#define NV827D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
+#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
+#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV827D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
+#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV827D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
+#define NV827D_HEAD_SET_CONVERSION_GAIN                                         15:0
+#define NV827D_HEAD_SET_CONVERSION_OFS                                          31:16
+#define NV827D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
+#define NV827D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV827D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV827D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl827d_h
+
diff --git a/classes/display/cl827e.h b/classes/display/cl827e.h
new file mode 100644
index 0000000..b142fd1
--- /dev/null
+++ b/classes/display/cl827e.h
@@ -0,0 +1,183 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl827e_h_
+#define _cl827e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV827E_OVERLAY_CHANNEL_DMA                                              (0x0000827E)
+
+#define NV_DISP_NOTIFICATION_1                                                       0x00000000
+#define NV_DISP_NOTIFICATION_1_SIZEOF                                                0x00000010
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0                                          0x00000000
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0                             31:0
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1                                          0x00000001
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1                             31:0
+#define NV_DISP_NOTIFICATION_1__2                                                    0x00000002
+#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP                                    31:0
+#define NV_DISP_NOTIFICATION_1__3                                                    0x00000003
+#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT                                      7:0
+#define NV_DISP_NOTIFICATION_1__3_R0                                                 15:8
+#define NV_DISP_NOTIFICATION_1__3_STATUS                                             31:16
+#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN                                   0x00008000
+#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN                                       0x0000FFFF
+#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED                                    0x00000000
+
+
+#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
+#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
+#define NV_DISP_NOTIFICATION_INFO16__0_R0                                            15:8
+
+
+#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
+#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
+
+
+// dma opcode instructions
+#define NV827E_DMA                                                         0x00000000 
+#define NV827E_DMA_OPCODE                                                       31:29 
+#define NV827E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV827E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV827E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV827E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV827E_DMA_OPCODE                                                       31:29 
+#define NV827E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV827E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV827E_DMA_METHOD_COUNT                                                 27:18 
+#define NV827E_DMA_METHOD_OFFSET                                                 11:2 
+#define NV827E_DMA_DATA                                                          31:0 
+#define NV827E_DMA_NOP                                                     0x00000000 
+#define NV827E_DMA_OPCODE                                                       31:29 
+#define NV827E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV827E_DMA_JUMP_OFFSET                                                   11:2 
+#define NV827E_DMA_OPCODE                                                       31:29 
+#define NV827E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV827E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV827E_PUT                                                              (0x00000000)
+#define NV827E_PUT_PTR                                                          11:2
+#define NV827E_GET                                                              (0x00000004)
+#define NV827E_GET_PTR                                                          11:2
+#define NV827E_UPDATE                                                           (0x00000080)
+#define NV827E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV827E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV827E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV827E_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
+#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
+#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
+#define NV827E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV827E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
+#define NV827E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV827E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
+#define NV827E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV827E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
+#define NV827E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV827E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV827E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV827E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV827E_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV827E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV827E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV827E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV827E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV827E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV827E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
+#define NV827E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
+#define NV827E_SET_POINT_IN                                                     (0x000000E0)
+#define NV827E_SET_POINT_IN_X                                                   14:0
+#define NV827E_SET_POINT_IN_Y                                                   30:16
+#define NV827E_SET_SIZE_IN                                                      (0x000000E4)
+#define NV827E_SET_SIZE_IN_WIDTH                                                14:0
+#define NV827E_SET_SIZE_IN_HEIGHT                                               30:16
+#define NV827E_SET_SIZE_OUT                                                     (0x000000E8)
+#define NV827E_SET_SIZE_OUT_WIDTH                                               14:0
+#define NV827E_SET_COMPOSITION_CONTROL                                          (0x00000100)
+#define NV827E_SET_COMPOSITION_CONTROL_MODE                                     3:0
+#define NV827E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
+#define NV827E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
+#define NV827E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
+#define NV827E_SET_KEY_COLOR                                                    (0x00000104)
+#define NV827E_SET_KEY_COLOR_COLOR                                              31:0
+#define NV827E_SET_KEY_MASK                                                     (0x00000108)
+#define NV827E_SET_KEY_MASK_MASK                                                31:0
+#define NV827E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV827E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV827E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV827E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV827E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV827E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV827E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV827E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV827E_SET_SPARE                                                        (0x000007BC)
+#define NV827E_SET_SPARE_UNUSED                                                 31:0
+#define NV827E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV827E_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV827E_SURFACE_SET_OFFSET                                               (0x00000800)
+#define NV827E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV827E_SURFACE_SET_SIZE                                                 (0x00000808)
+#define NV827E_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV827E_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV827E_SURFACE_SET_STORAGE                                              (0x0000080C)
+#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV827E_SURFACE_SET_STORAGE_PITCH                                        17:8
+#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV827E_SURFACE_SET_PARAMS                                               (0x00000810)
+#define NV827E_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV827E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
+#define NV827E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
+#define NV827E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV827E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV827E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
+#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
+#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
+#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
+#define NV827E_SURFACE_SET_PARAMS_RESERVED0                                     22:16
+#define NV827E_SURFACE_SET_PARAMS_RESERVED1                                     24:24
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl827e_h
+
diff --git a/classes/display/cl837c.h b/classes/display/cl837c.h
new file mode 100644
index 0000000..a05d3f2
--- /dev/null
+++ b/classes/display/cl837c.h
@@ -0,0 +1,181 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl837c_h_
+#define _cl837c_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV837C_BASE_CHANNEL_DMA                                                 (0x0000837C)
+
+#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
+#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
+#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
+
+
+// dma opcode instructions
+#define NV837C_DMA                                                         0x00000000 
+#define NV837C_DMA_OPCODE                                                       31:29 
+#define NV837C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV837C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV837C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV837C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV837C_DMA_OPCODE                                                       31:29 
+#define NV837C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV837C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV837C_DMA_METHOD_COUNT                                                 27:18 
+#define NV837C_DMA_METHOD_OFFSET                                                 11:2 
+#define NV837C_DMA_DATA                                                          31:0 
+#define NV837C_DMA_NOP                                                     0x00000000 
+#define NV837C_DMA_OPCODE                                                       31:29 
+#define NV837C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV837C_DMA_JUMP_OFFSET                                                   11:2 
+#define NV837C_DMA_OPCODE                                                       31:29 
+#define NV837C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV837C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV837C_PUT                                                              (0x00000000)
+#define NV837C_PUT_PTR                                                          11:2
+#define NV837C_GET                                                              (0x00000004)
+#define NV837C_GET_PTR                                                          11:2
+#define NV837C_GET_SCANLINE                                                     (0x00000010)
+#define NV837C_GET_SCANLINE_LINE                                                15:0
+#define NV837C_UPDATE                                                           (0x00000080)
+#define NV837C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV837C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV837C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV837C_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
+#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
+#define NV837C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV837C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
+#define NV837C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
+#define NV837C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
+#define NV837C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV837C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
+#define NV837C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV837C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
+#define NV837C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV837C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV837C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV837C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV837C_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV837C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV837C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV837C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV837C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV837C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV837C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
+#define NV837C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
+#define NV837C_SET_BASE_LUT_LO                                                  (0x000000E0)
+#define NV837C_SET_BASE_LUT_LO_ENABLE                                           31:30
+#define NV837C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
+#define NV837C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
+#define NV837C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
+#define NV837C_SET_BASE_LUT_LO_MODE                                             29:29
+#define NV837C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
+#define NV837C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
+#define NV837C_SET_BASE_LUT_LO_ORIGIN                                           7:2
+#define NV837C_SET_BASE_LUT_HI                                                  (0x000000E4)
+#define NV837C_SET_BASE_LUT_HI_ORIGIN                                           31:0
+#define NV837C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
+#define NV837C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
+#define NV837C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
+#define NV837C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
+#define NV837C_SET_OUTPUT_LUT_LO_MODE                                           30:30
+#define NV837C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
+#define NV837C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
+#define NV837C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
+#define NV837C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
+#define NV837C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
+#define NV837C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
+#define NV837C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV837C_SET_PROCESSING                                                   (0x00000110)
+#define NV837C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV837C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV837C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV837C_SET_CONVERSION                                                   (0x00000114)
+#define NV837C_SET_CONVERSION_GAIN                                              15:0
+#define NV837C_SET_CONVERSION_OFS                                               31:16
+#define NV837C_SET_SPARE                                                        (0x000007BC)
+#define NV837C_SET_SPARE_UNUSED                                                 31:0
+#define NV837C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV837C_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV837C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
+#define NV837C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV837C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
+#define NV837C_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV837C_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV837C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
+#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV837C_SURFACE_SET_STORAGE_PITCH                                        17:8
+#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV837C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
+#define NV837C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
+#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
+#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
+#define NV837C_SURFACE_SET_PARAMS_GAMMA                                         2:2
+#define NV837C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
+#define NV837C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
+#define NV837C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
+#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
+#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
+#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
+#define NV837C_SURFACE_SET_PARAMS_RESERVED0                                     22:16
+#define NV837C_SURFACE_SET_PARAMS_RESERVED1                                     24:24
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl837c_h
+
diff --git a/classes/display/cl837d.h b/classes/display/cl837d.h
new file mode 100644
index 0000000..57c04f2
--- /dev/null
+++ b/classes/display/cl837d.h
@@ -0,0 +1,709 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl837d_h_
+#define _cl837d_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV837D_CORE_CHANNEL_DMA                                                 (0x0000837D)
+
+#define NV837D_CORE_NOTIFIER_1                                                      0x00000000
+#define NV837D_CORE_NOTIFIER_1_SIZEOF                                               0x00000054
+#define NV837D_CORE_NOTIFIER_1_COMPLETION_0                                         0x00000000
+#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE                                    0:0
+#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_R0                                      15:1
+#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP                               29:16
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1                                       0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE                                  0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE                            0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE                             0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO                         1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_R0                                    3:3
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_R1                                    31:22
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_2                                       0x00000002
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_2_R2                                    31:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_3                                       0x00000003
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_3_R3                                    31:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_4                                       0x00000004
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_4_R4                                    31:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5                              0x00000005
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE                   0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE             0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE              0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE                    1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE              0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE               0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE                 3:3
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE           0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE            0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6                              0x00000006
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE                   0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE             0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE              0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE                    1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE              0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE               0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE                 3:3
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE           0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE            0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7                              0x00000007
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE                   0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE             0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE              0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE                    1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE              0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE               0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE                 3:3
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE           0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE            0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8                              0x00000008
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18                0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24                1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18                  2:2
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE            0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE             0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24                  3:3
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE            0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE             0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A                4:4
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B                5:5
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS             6:6
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE       0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE        0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS                    7:7
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE              0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE               0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI                          9:9
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE                    0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE                     0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9                              0x00000009
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18                0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24                1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18                  2:2
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE            0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE             0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24                  3:3
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE            0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE             0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A                4:4
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B                5:5
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE          0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE           0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS             6:6
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE       0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE        0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS                    7:7
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE              0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE               0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI                          9:9
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE                    0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE                     0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10                            0x0000000A
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC               0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC                 1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE           0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE            0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11                            0x0000000B
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC               0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC                 1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE           0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE            0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12                            0x0000000C
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC               0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC                 1:1
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE           0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE            0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13                            0x0000000D
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE                     0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE               0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE                0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0                         31:2
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14                            0x0000000E
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444          14:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1                         15:15
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422          30:16
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2                         31:31
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15                            0x0000000F
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444          14:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3                         15:15
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422          30:16
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4                         31:31
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16                            0x00000010
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444          14:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5                         15:15
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422          30:16
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6                         31:31
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17                            0x00000011
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE                     0:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE               0x00000000
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE                0x00000001
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0                         31:2
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18                            0x00000012
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444          14:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1                         15:15
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422          30:16
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2                         31:31
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19                            0x00000013
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444          14:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3                         15:15
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422          30:16
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4                         31:31
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20                            0x00000014
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444          14:0
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5                         15:15
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422          30:16
+#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6                         31:31
+
+
+// dma opcode instructions
+#define NV837D_DMA                                                         0x00000000 
+#define NV837D_DMA_OPCODE                                                       31:29 
+#define NV837D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV837D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV837D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV837D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV837D_DMA_OPCODE                                                       31:29 
+#define NV837D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV837D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV837D_DMA_METHOD_COUNT                                                 27:18 
+#define NV837D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV837D_DMA_DATA                                                          31:0 
+#define NV837D_DMA_NOP                                                     0x00000000 
+#define NV837D_DMA_OPCODE                                                       31:29 
+#define NV837D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV837D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV837D_DMA_OPCODE                                                       31:29 
+#define NV837D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV837D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV837D_PUT                                                              (0x00000000)
+#define NV837D_PUT_PTR                                                          11:2
+#define NV837D_GET                                                              (0x00000004)
+#define NV837D_GET_PTR                                                          11:2
+#define NV837D_UPDATE                                                           (0x00000080)
+#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
+#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV837D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV837D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV837D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
+#define NV837D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV837D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV837D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV837D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV837D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV837D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV837D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV837D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV837D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV837D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV837D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV837D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV837D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV837D_SET_SPARE                                                        (0x000003BC)
+#define NV837D_SET_SPARE_UNUSED                                                 31:0
+#define NV837D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV837D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV837D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
+#define NV837D_DAC_SET_CONTROL_OWNER                                            3:0
+#define NV837D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV837D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV837D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV837D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV837D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV837D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV837D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV837D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL                                         13:8
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
+#define NV837D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
+#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
+#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
+#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
+#define NV837D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
+#define NV837D_DAC_SET_POLARITY_HSYNC                                           0:0
+#define NV837D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV837D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV837D_DAC_SET_POLARITY_VSYNC                                           1:1
+#define NV837D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV837D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV837D_DAC_SET_POLARITY_RESERVED                                        31:2
+#define NV837D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
+#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
+#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
+#define NV837D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
+#define NV837D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
+#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
+
+#define NV837D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
+#define NV837D_SOR_SET_CONTROL_OWNER                                            3:0
+#define NV837D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV837D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV837D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV837D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
+#define NV837D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
+#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
+#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
+#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
+
+#define NV837D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
+#define NV837D_PIOR_SET_CONTROL_OWNER                                           3:0
+#define NV837D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
+#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
+#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
+#define NV837D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
+#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
+#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
+#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
+#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
+#define NV837D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
+#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
+#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH                                     19:16
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                             (0x00000000)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                          (0x00000001)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                          (0x00000002)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                          (0x00000003)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                          (0x00000004)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                          (0x00000005)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                          (0x00000006)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                          (0x00000007)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                          (0x00000008)
+#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                          (0x00000009)
+
+#define NV837D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
+#define NV837D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV837D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV837D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
+#define NV837D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
+#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
+#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
+#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
+#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
+#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
+#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
+#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
+#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
+#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
+#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
+#define NV837D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
+#define NV837D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
+#define NV837D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV837D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
+#define NV837D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV837D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV837D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV837D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
+#define NV837D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV837D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV837D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
+#define NV837D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV837D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV837D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
+#define NV837D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV837D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV837D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
+#define NV837D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV837D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV837D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
+#define NV837D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV837D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV837D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
+#define NV837D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
+#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
+#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV837D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
+#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV837D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
+#define NV837D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV837D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV837D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
+#define NV837D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
+#define NV837D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
+#define NV837D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
+#define NV837D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV837D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
+#define NV837D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV837D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
+#define NV837D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV837D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
+#define NV837D_HEAD_SET_SIZE_WIDTH                                              14:0
+#define NV837D_HEAD_SET_SIZE_HEIGHT                                             30:16
+#define NV837D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
+#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV837D_HEAD_SET_STORAGE_PITCH                                           17:8
+#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
+#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV837D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
+#define NV837D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV837D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV837D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV837D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV837D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV837D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV837D_HEAD_SET_PARAMS_RESERVED0                                        22:16
+#define NV837D_HEAD_SET_PARAMS_RESERVED1                                        24:24
+#define NV837D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
+#define NV837D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV837D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
+#define NV837D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
+#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
+#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
+#define NV837D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
+#define NV837D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
+#define NV837D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
+#define NV837D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
+#define NV837D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
+#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV837D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV837D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV837D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV837D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV837D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV837D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
+#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV837D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV837D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV837D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
+#define NV837D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
+#define NV837D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
+#define NV837D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
+#define NV837D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV837D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV837D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
+#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
+#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV837D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
+#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV837D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
+#define NV837D_HEAD_SET_CONVERSION_GAIN                                         15:0
+#define NV837D_HEAD_SET_CONVERSION_OFS                                          31:16
+#define NV837D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
+#define NV837D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV837D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV837D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl837d_h
+
diff --git a/classes/display/cl837e.h b/classes/display/cl837e.h
new file mode 100644
index 0000000..62cc069
--- /dev/null
+++ b/classes/display/cl837e.h
@@ -0,0 +1,195 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl837e_h_
+#define _cl837e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV837E_OVERLAY_CHANNEL_DMA                                              (0x0000837E)
+
+#define NV_DISP_NOTIFICATION_1                                                       0x00000000
+#define NV_DISP_NOTIFICATION_1_SIZEOF                                                0x00000010
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0                                          0x00000000
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0                             31:0
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1                                          0x00000001
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1                             31:0
+#define NV_DISP_NOTIFICATION_1__2                                                    0x00000002
+#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP                                    31:0
+#define NV_DISP_NOTIFICATION_1__3                                                    0x00000003
+#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT                                      7:0
+#define NV_DISP_NOTIFICATION_1__3_R0                                                 15:8
+#define NV_DISP_NOTIFICATION_1__3_STATUS                                             31:16
+#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN                                   0x00008000
+#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN                                       0x0000FFFF
+#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED                                    0x00000000
+
+
+#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
+#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
+#define NV_DISP_NOTIFICATION_INFO16__0_R0                                            15:8
+
+
+#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
+#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
+
+
+// dma opcode instructions
+#define NV837E_DMA                                                         0x00000000 
+#define NV837E_DMA_OPCODE                                                       31:29 
+#define NV837E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV837E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV837E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV837E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV837E_DMA_OPCODE                                                       31:29 
+#define NV837E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV837E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV837E_DMA_METHOD_COUNT                                                 27:18 
+#define NV837E_DMA_METHOD_OFFSET                                                 11:2 
+#define NV837E_DMA_DATA                                                          31:0 
+#define NV837E_DMA_NOP                                                     0x00000000 
+#define NV837E_DMA_OPCODE                                                       31:29 
+#define NV837E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV837E_DMA_JUMP_OFFSET                                                   11:2 
+#define NV837E_DMA_OPCODE                                                       31:29 
+#define NV837E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV837E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV837E_PUT                                                              (0x00000000)
+#define NV837E_PUT_PTR                                                          11:2
+#define NV837E_GET                                                              (0x00000004)
+#define NV837E_GET_PTR                                                          11:2
+#define NV837E_UPDATE                                                           (0x00000080)
+#define NV837E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV837E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV837E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV837E_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
+#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
+#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
+#define NV837E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV837E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
+#define NV837E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV837E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
+#define NV837E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV837E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
+#define NV837E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV837E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV837E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV837E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV837E_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV837E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV837E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV837E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV837E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV837E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV837E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
+#define NV837E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV837E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
+#define NV837E_SET_OVERLAY_LUT_LO_ENABLE                                        30:30
+#define NV837E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
+#define NV837E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
+#define NV837E_SET_OVERLAY_LUT_LO_MODE                                          29:29
+#define NV837E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
+#define NV837E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
+#define NV837E_SET_OVERLAY_LUT_LO_ORIGIN                                        7:2
+#define NV837E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
+#define NV837E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
+#define NV837E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
+#define NV837E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
+#define NV837E_SET_POINT_IN                                                     (0x000000E0)
+#define NV837E_SET_POINT_IN_X                                                   14:0
+#define NV837E_SET_POINT_IN_Y                                                   30:16
+#define NV837E_SET_SIZE_IN                                                      (0x000000E4)
+#define NV837E_SET_SIZE_IN_WIDTH                                                14:0
+#define NV837E_SET_SIZE_IN_HEIGHT                                               30:16
+#define NV837E_SET_SIZE_OUT                                                     (0x000000E8)
+#define NV837E_SET_SIZE_OUT_WIDTH                                               14:0
+#define NV837E_SET_COMPOSITION_CONTROL                                          (0x00000100)
+#define NV837E_SET_COMPOSITION_CONTROL_MODE                                     3:0
+#define NV837E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
+#define NV837E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
+#define NV837E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
+#define NV837E_SET_KEY_COLOR                                                    (0x00000104)
+#define NV837E_SET_KEY_COLOR_COLOR                                              31:0
+#define NV837E_SET_KEY_MASK                                                     (0x00000108)
+#define NV837E_SET_KEY_MASK_MASK                                                31:0
+#define NV837E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV837E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV837E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV837E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV837E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV837E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV837E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV837E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV837E_SET_SPARE                                                        (0x000007BC)
+#define NV837E_SET_SPARE_UNUSED                                                 31:0
+#define NV837E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV837E_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV837E_SURFACE_SET_OFFSET                                               (0x00000800)
+#define NV837E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV837E_SURFACE_SET_SIZE                                                 (0x00000808)
+#define NV837E_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV837E_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV837E_SURFACE_SET_STORAGE                                              (0x0000080C)
+#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV837E_SURFACE_SET_STORAGE_PITCH                                        17:8
+#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV837E_SURFACE_SET_PARAMS                                               (0x00000810)
+#define NV837E_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV837E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
+#define NV837E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
+#define NV837E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV837E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV837E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
+#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
+#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
+#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
+#define NV837E_SURFACE_SET_PARAMS_RESERVED0                                     22:16
+#define NV837E_SURFACE_SET_PARAMS_RESERVED1                                     24:24
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl837e_h
+
diff --git a/classes/display/cl857a.h b/classes/display/cl857a.h
new file mode 100644
index 0000000..cc5fbca
--- /dev/null
+++ b/classes/display/cl857a.h
@@ -0,0 +1,56 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl857a_h_
+#define _cl857a_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV857A_CURSOR_CHANNEL_PIO                                               (0x0000857A)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
+    NvV32 Reserved02[0x3DE];
+} GT214DispCursorControlPio;
+
+#define NV857A_FREE                                                             (0x00000008)
+#define NV857A_FREE_COUNT                                                       5:0
+#define NV857A_UPDATE                                                           (0x00000080)
+#define NV857A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV857A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV857A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
+#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
+#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl857a_h
+
diff --git a/classes/display/cl857b.h b/classes/display/cl857b.h
new file mode 100644
index 0000000..a6c8c49
--- /dev/null
+++ b/classes/display/cl857b.h
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl857b_h_
+#define _cl857b_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV857B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000857B)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
+    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
+    NvV32 Reserved02[0x3DD];
+} GT214DispOverlayImmControlPio;
+
+#define NV857B_FREE                                                             (0x00000008)
+#define NV857B_FREE_COUNT                                                       5:0
+#define NV857B_UPDATE                                                           (0x00000080)
+#define NV857B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV857B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV857B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV857B_SET_POINT_OUT                                                    (0x00000084)
+#define NV857B_SET_POINT_OUT_X                                                  15:0
+#define NV857B_SET_POINT_OUT_Y                                                  31:16
+#define NV857B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
+#define NV857B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl857b_h
+
diff --git a/classes/display/cl857c.h b/classes/display/cl857c.h
new file mode 100644
index 0000000..bfb610c
--- /dev/null
+++ b/classes/display/cl857c.h
@@ -0,0 +1,188 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl857c_h_
+#define _cl857c_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV857C_BASE_CHANNEL_DMA                                                 (0x0000857C)
+
+#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
+#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
+#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
+
+
+// dma opcode instructions
+#define NV857C_DMA                                                                              0x00000000 
+#define NV857C_DMA_OPCODE                                                                            31:29 
+#define NV857C_DMA_OPCODE_METHOD                                                                0x00000000 
+#define NV857C_DMA_OPCODE_JUMP                                                                  0x00000001 
+#define NV857C_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
+#define NV857C_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
+#define NV857C_DMA_OPCODE                                                                            31:29 
+#define NV857C_DMA_OPCODE_METHOD                                                                0x00000000 
+#define NV857C_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
+#define NV857C_DMA_METHOD_COUNT                                                                      27:18 
+#define NV857C_DMA_METHOD_OFFSET                                                                      11:2 
+#define NV857C_DMA_DATA                                                                               31:0 
+#define NV857C_DMA_DATA_NOP                                                                     0x00000000 
+#define NV857C_DMA_OPCODE                                                                            31:29 
+#define NV857C_DMA_OPCODE_JUMP                                                                  0x00000001 
+#define NV857C_DMA_JUMP_OFFSET                                                                        11:2 
+#define NV857C_DMA_OPCODE                                                                            31:29 
+#define NV857C_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
+#define NV857C_DMA_SET_SUBDEVICE_MASK_VALUE                                                           11:0 
+
+// class methods
+#define NV857C_PUT                                                              (0x00000000)
+#define NV857C_PUT_PTR                                                          11:2
+#define NV857C_GET                                                              (0x00000004)
+#define NV857C_GET_PTR                                                          11:2
+#define NV857C_GET_SCANLINE                                                     (0x00000010)
+#define NV857C_GET_SCANLINE_LINE                                                15:0
+#define NV857C_UPDATE                                                           (0x00000080)
+#define NV857C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV857C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV857C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV857C_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
+#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
+#define NV857C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV857C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
+#define NV857C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
+#define NV857C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
+#define NV857C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV857C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
+#define NV857C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
+#define NV857C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
+#define NV857C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
+#define NV857C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV857C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
+#define NV857C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV857C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV857C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV857C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV857C_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV857C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV857C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV857C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV857C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
+#define NV857C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
+#define NV857C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
+#define NV857C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV857C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV857C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
+#define NV857C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
+#define NV857C_SET_BASE_LUT_LO                                                  (0x000000E0)
+#define NV857C_SET_BASE_LUT_LO_ENABLE                                           31:30
+#define NV857C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
+#define NV857C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
+#define NV857C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000003)
+#define NV857C_SET_BASE_LUT_LO_MODE                                             29:29
+#define NV857C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
+#define NV857C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
+#define NV857C_SET_BASE_LUT_LO_ORIGIN                                           7:2
+#define NV857C_SET_BASE_LUT_HI                                                  (0x000000E4)
+#define NV857C_SET_BASE_LUT_HI_ORIGIN                                           31:0
+#define NV857C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
+#define NV857C_SET_OUTPUT_LUT_LO_ENABLE                                         31:31
+#define NV857C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
+#define NV857C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000001)
+#define NV857C_SET_OUTPUT_LUT_LO_MODE                                           30:30
+#define NV857C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
+#define NV857C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
+#define NV857C_SET_OUTPUT_LUT_LO_ORIGIN                                         7:2
+#define NV857C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
+#define NV857C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
+#define NV857C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
+#define NV857C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV857C_SET_PROCESSING                                                   (0x00000110)
+#define NV857C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV857C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV857C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV857C_SET_CONVERSION                                                   (0x00000114)
+#define NV857C_SET_CONVERSION_GAIN                                              15:0
+#define NV857C_SET_CONVERSION_OFS                                               31:16
+#define NV857C_SET_SPARE                                                        (0x000007BC)
+#define NV857C_SET_SPARE_UNUSED                                                 31:0
+#define NV857C_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV857C_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV857C_SURFACE_SET_OFFSET(a,b)                                          (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
+#define NV857C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV857C_SURFACE_SET_SIZE(a)                                              (0x00000808 + (a)*0x00000020)
+#define NV857C_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV857C_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV857C_SURFACE_SET_STORAGE(a)                                           (0x0000080C + (a)*0x00000020)
+#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV857C_SURFACE_SET_STORAGE_PITCH                                        19:8
+#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV857C_SURFACE_SET_PARAMS(a)                                            (0x00000810 + (a)*0x00000020)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
+#define NV857C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
+#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
+#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
+#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X8_AA                            (0x00000003)
+#define NV857C_SURFACE_SET_PARAMS_GAMMA                                         2:2
+#define NV857C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
+#define NV857C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
+#define NV857C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
+#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
+#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
+#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
+#define NV857C_SURFACE_SET_PARAMS_RESERVED0                                     22:16
+#define NV857C_SURFACE_SET_PARAMS_RESERVED1                                     24:24
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl857c_h
+
diff --git a/classes/display/cl857d.h b/classes/display/cl857d.h
new file mode 100644
index 0000000..13ef79f
--- /dev/null
+++ b/classes/display/cl857d.h
@@ -0,0 +1,1121 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl857d_h_
+#define _cl857d_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV857D_CORE_CHANNEL_DMA                                                 (0x0000857D)
+
+#define NV857D_CORE_NOTIFIER_2                                                      0x00000000
+#define NV857D_CORE_NOTIFIER_2_SIZEOF                                               0x00000124
+#define NV857D_CORE_NOTIFIER_2_COMPLETION_0                                         0x00000000
+#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE                                    0:0
+#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_R0                                      15:1
+#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_TIMESTAMP                               29:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1                                       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE                                  0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_FALSE                            0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_TRUE                             0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO                         1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED              3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_FALSE        0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_TRUE         0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA                        22:22
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2                                       0x00000002
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED                    0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_FALSE              0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_TRUE               0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY                      1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_FALSE                0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_TRUE                 0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_R2                                    31:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3                                       0x00000003
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3_R3                                    31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4                                       0x00000004
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4_R4                                    31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5                                       0x00000005
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5_R5                                    31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6                                       0x00000006
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6_R6                                    31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7                                       0x00000007
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7_R7                                    31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8                                       0x00000008
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8_R8                                    31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9                              0x00000009
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE                   0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE                    1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_FALSE              0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_TRUE               0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_R0                           31:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10                             0x0000000A
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11                             0x0000000B
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE                  0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_FALSE            0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_TRUE             0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE                   1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE                3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_FALSE          0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_TRUE           0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_R0                          31:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12                             0x0000000C
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13                             0x0000000D
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE                  0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_FALSE            0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_TRUE             0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE                   1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE                3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_FALSE          0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_TRUE           0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_R0                          31:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14                             0x0000000E
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15                             0x0000000F
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE                  0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_FALSE            0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_TRUE             0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE                   1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE                3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_FALSE          0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_TRUE           0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_R0                          31:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16                             0x00000010
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17                             0x00000011
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18                             0x00000012
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19                             0x00000013
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20                             0x00000014
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21                             0x00000015
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22                             0x00000016
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23                             0x00000017
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24                             0x00000018
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25                             0x00000019
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26                             0x0000001A
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27                             0x0000001B
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28                             0x0000001C
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29                             0x0000001D
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30                             0x0000001E
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31                             0x0000001F
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24               1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18                 2:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24                 3:3
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A               4:4
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B               5:5
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS            6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS                   7:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_FALSE             0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_TRUE              0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI                         9:9
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_FALSE                   0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_TRUE                    0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A                        10:10
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B                        11:11
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_FALSE                  0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_TRUE                   0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ           12:12
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_FALSE     0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_TRUE      0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_R0                          31:14
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32                             0x00000020
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32_R1                          31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33                            0x00000021
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC                 1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_R0                         31:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34                            0x00000022
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34_R1                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35                            0x00000023
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC                 1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_R0                         31:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36                            0x00000024
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36_R1                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37                            0x00000025
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC                 1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_R0                         31:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38                            0x00000026
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38_R1                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39                            0x00000027
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC               0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC                 1:1
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_FALSE           0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_TRUE            0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_R0                         31:7
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40                            0x00000028
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40_R1                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41                            0x00000029
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE                     0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_FALSE               0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_TRUE                0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_R0                         31:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42                            0x0000002A
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R1                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R2                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43                            0x0000002B
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R3                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R4                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44                            0x0000002C
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R5                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R6                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45                            0x0000002D
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45_R7                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46                            0x0000002E
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46_R8                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47                            0x0000002F
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47_R9                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48                            0x00000030
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48_R10                        31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49                            0x00000031
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE                     0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_FALSE               0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_TRUE                0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_R0                         31:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50                            0x00000032
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R1                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R2                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51                            0x00000033
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R3                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R4                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52                            0x00000034
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R5                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R6                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53                            0x00000035
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53_R7                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54                            0x00000036
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54_R8                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55                            0x00000037
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55_R9                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56                            0x00000038
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56_R10                        31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57                            0x00000039
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE                     0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_FALSE               0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_TRUE                0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_R0                         31:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58                            0x0000003A
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R1                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R2                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59                            0x0000003B
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R3                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R4                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60                            0x0000003C
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R5                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R6                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61                            0x0000003D
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61_R7                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62                            0x0000003E
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62_R8                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63                            0x0000003F
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63_R9                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64                            0x00000040
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64_R10                        31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65                            0x00000041
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE                     0:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_FALSE               0x00000000
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_TRUE                0x00000001
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_R0                         31:2
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66                            0x00000042
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R1                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R2                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67                            0x00000043
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R3                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R4                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68                            0x00000044
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP444          14:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R5                         15:15
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP422          30:16
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R6                         31:31
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69                            0x00000045
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69_R7                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70                            0x00000046
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70_R8                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71                            0x00000047
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71_R9                         31:0
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72                            0x00000048
+#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72_R10                        31:0
+
+
+// dma opcode instructions
+#define NV857D_DMA                                                                              0x00000000 
+#define NV857D_DMA_OPCODE                                                                            31:29 
+#define NV857D_DMA_OPCODE_METHOD                                                                0x00000000 
+#define NV857D_DMA_OPCODE_JUMP                                                                  0x00000001 
+#define NV857D_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
+#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
+#define NV857D_DMA_OPCODE                                                                            31:29 
+#define NV857D_DMA_OPCODE_METHOD                                                                0x00000000 
+#define NV857D_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
+#define NV857D_DMA_METHOD_COUNT                                                                      27:18 
+#define NV857D_DMA_METHOD_OFFSET                                                                      11:2 
+#define NV857D_DMA_DATA                                                                               31:0 
+#define NV857D_DMA_DATA_NOP                                                                     0x00000000 
+#define NV857D_DMA_OPCODE                                                                            31:29 
+#define NV857D_DMA_OPCODE_JUMP                                                                  0x00000001 
+#define NV857D_DMA_JUMP_OFFSET                                                                        11:2 
+#define NV857D_DMA_OPCODE                                                                            31:29 
+#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
+#define NV857D_DMA_SET_SUBDEVICE_MASK_VALUE                                                           11:0 
+
+// class methods
+#define NV857D_PUT                                                              (0x00000000)
+#define NV857D_PUT_PTR                                                          11:2
+#define NV857D_GET                                                              (0x00000004)
+#define NV857D_GET_PTR                                                          11:2
+#define NV857D_UPDATE                                                           (0x00000080)
+#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
+#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV857D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV857D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
+#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV857D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV857D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV857D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV857D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV857D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV857D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV857D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV857D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV857D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV857D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV857D_SET_SPARE                                                        (0x000003BC)
+#define NV857D_SET_SPARE_UNUSED                                                 31:0
+#define NV857D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV857D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV857D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
+#define NV857D_DAC_SET_CONTROL_OWNER                                            3:0
+#define NV857D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV857D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV857D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV857D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV857D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV857D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL                                         13:8
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
+#define NV857D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
+#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
+#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
+#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
+#define NV857D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
+#define NV857D_DAC_SET_POLARITY_HSYNC                                           0:0
+#define NV857D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV857D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV857D_DAC_SET_POLARITY_VSYNC                                           1:1
+#define NV857D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV857D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV857D_DAC_SET_POLARITY_RESERVED                                        31:2
+#define NV857D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
+#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
+#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
+#define NV857D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
+#define NV857D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
+#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
+
+#define NV857D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
+#define NV857D_SOR_SET_CONTROL_OWNER                                            3:0
+#define NV857D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV857D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV857D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV857D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV857D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV857D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV857D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
+#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
+#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
+#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
+
+#define NV857D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
+#define NV857D_PIOR_SET_CONTROL_OWNER                                           3:0
+#define NV857D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
+#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
+#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
+#define NV857D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
+#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
+#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
+#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
+#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
+#define NV857D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
+#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
+#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH                                     19:16
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                             (0x00000000)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                          (0x00000001)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                          (0x00000002)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                          (0x00000003)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                          (0x00000004)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                          (0x00000005)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                          (0x00000006)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                          (0x00000007)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                          (0x00000008)
+#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                          (0x00000009)
+
+#define NV857D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
+#define NV857D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV857D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV857D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
+#define NV857D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
+#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
+#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
+#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
+#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
+#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
+#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
+#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
+#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
+#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
+#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
+#define NV857D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
+#define NV857D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
+#define NV857D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV857D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
+#define NV857D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV857D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV857D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV857D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
+#define NV857D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV857D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV857D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
+#define NV857D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV857D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV857D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
+#define NV857D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV857D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV857D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
+#define NV857D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV857D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV857D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
+#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
+#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
+#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
+#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV857D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
+#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV857D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
+#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV857D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
+#define NV857D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
+#define NV857D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
+#define NV857D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
+#define NV857D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV857D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
+#define NV857D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV857D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
+#define NV857D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV857D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
+#define NV857D_HEAD_SET_SIZE_WIDTH                                              14:0
+#define NV857D_HEAD_SET_SIZE_HEIGHT                                             30:16
+#define NV857D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
+#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV857D_HEAD_SET_STORAGE_PITCH                                           19:8
+#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
+#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV857D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
+#define NV857D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV857D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV857D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X8_AA                               (0x00000003)
+#define NV857D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV857D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV857D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV857D_HEAD_SET_PARAMS_RESERVED0                                        22:16
+#define NV857D_HEAD_SET_PARAMS_RESERVED1                                        24:24
+#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
+#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV857D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
+#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
+#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
+#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
+#define NV857D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
+#define NV857D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
+#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
+#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
+#define NV857D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
+#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV857D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV857D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV857D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV857D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
+#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV857D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV857D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV857D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
+#define NV857D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
+#define NV857D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
+#define NV857D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
+#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV857D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
+#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X8_AA            (0x00000003)
+#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
+#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV857D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
+#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV857D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
+#define NV857D_HEAD_SET_CONVERSION_GAIN                                         15:0
+#define NV857D_HEAD_SET_CONVERSION_OFS                                          31:16
+#define NV857D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
+#define NV857D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV857D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV857D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl857d_h
+
diff --git a/classes/display/cl857e.h b/classes/display/cl857e.h
new file mode 100644
index 0000000..045a134
--- /dev/null
+++ b/classes/display/cl857e.h
@@ -0,0 +1,195 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl857e_h_
+#define _cl857e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV857E_OVERLAY_CHANNEL_DMA                                              (0x0000857E)
+
+#define NV_DISP_NOTIFICATION_1                                                       0x00000000
+#define NV_DISP_NOTIFICATION_1_SIZEOF                                                0x00000010
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0                                          0x00000000
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0                             31:0
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1                                          0x00000001
+#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1                             31:0
+#define NV_DISP_NOTIFICATION_1__2                                                    0x00000002
+#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP                                    31:0
+#define NV_DISP_NOTIFICATION_1__3                                                    0x00000003
+#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT                                      7:0
+#define NV_DISP_NOTIFICATION_1__3_R0                                                 15:8
+#define NV_DISP_NOTIFICATION_1__3_STATUS                                             31:16
+#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN                                   0x00008000
+#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN                                       0x0000FFFF
+#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED                                    0x00000000
+
+
+#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
+#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
+#define NV_DISP_NOTIFICATION_INFO16__0_R0                                            15:8
+
+
+#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
+#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
+
+
+// dma opcode instructions
+#define NV857E_DMA                                                                              0x00000000 
+#define NV857E_DMA_OPCODE                                                                            31:29 
+#define NV857E_DMA_OPCODE_METHOD                                                                0x00000000 
+#define NV857E_DMA_OPCODE_JUMP                                                                  0x00000001 
+#define NV857E_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
+#define NV857E_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
+#define NV857E_DMA_OPCODE                                                                            31:29 
+#define NV857E_DMA_OPCODE_METHOD                                                                0x00000000 
+#define NV857E_DMA_OPCODE_NONINC_METHOD                                                         0x00000002 
+#define NV857E_DMA_METHOD_COUNT                                                                      27:18 
+#define NV857E_DMA_METHOD_OFFSET                                                                      11:2 
+#define NV857E_DMA_DATA                                                                               31:0 
+#define NV857E_DMA_DATA_NOP                                                                     0x00000000 
+#define NV857E_DMA_OPCODE                                                                            31:29 
+#define NV857E_DMA_OPCODE_JUMP                                                                  0x00000001 
+#define NV857E_DMA_JUMP_OFFSET                                                                        11:2 
+#define NV857E_DMA_OPCODE                                                                            31:29 
+#define NV857E_DMA_OPCODE_SET_SUBDEVICE_MASK                                                    0x00000003 
+#define NV857E_DMA_SET_SUBDEVICE_MASK_VALUE                                                           11:0 
+
+// class methods
+#define NV857E_PUT                                                              (0x00000000)
+#define NV857E_PUT_PTR                                                          11:2
+#define NV857E_GET                                                              (0x00000004)
+#define NV857E_GET_PTR                                                          11:2
+#define NV857E_UPDATE                                                           (0x00000080)
+#define NV857E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV857E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV857E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV857E_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
+#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
+#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
+#define NV857E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV857E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
+#define NV857E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV857E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
+#define NV857E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV857E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
+#define NV857E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV857E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV857E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV857E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV857E_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV857E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV857E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV857E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV857E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV857E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV857E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
+#define NV857E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV857E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
+#define NV857E_SET_OVERLAY_LUT_LO_ENABLE                                        30:30
+#define NV857E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
+#define NV857E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
+#define NV857E_SET_OVERLAY_LUT_LO_MODE                                          29:29
+#define NV857E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
+#define NV857E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
+#define NV857E_SET_OVERLAY_LUT_LO_ORIGIN                                        7:2
+#define NV857E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
+#define NV857E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
+#define NV857E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
+#define NV857E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
+#define NV857E_SET_POINT_IN                                                     (0x000000E0)
+#define NV857E_SET_POINT_IN_X                                                   14:0
+#define NV857E_SET_POINT_IN_Y                                                   30:16
+#define NV857E_SET_SIZE_IN                                                      (0x000000E4)
+#define NV857E_SET_SIZE_IN_WIDTH                                                14:0
+#define NV857E_SET_SIZE_IN_HEIGHT                                               30:16
+#define NV857E_SET_SIZE_OUT                                                     (0x000000E8)
+#define NV857E_SET_SIZE_OUT_WIDTH                                               14:0
+#define NV857E_SET_COMPOSITION_CONTROL                                          (0x00000100)
+#define NV857E_SET_COMPOSITION_CONTROL_MODE                                     3:0
+#define NV857E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
+#define NV857E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
+#define NV857E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE                 (0x00000002)
+#define NV857E_SET_KEY_COLOR                                                    (0x00000104)
+#define NV857E_SET_KEY_COLOR_COLOR                                              31:0
+#define NV857E_SET_KEY_MASK                                                     (0x00000108)
+#define NV857E_SET_KEY_MASK_MASK                                                31:0
+#define NV857E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV857E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV857E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV857E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV857E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV857E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV857E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV857E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV857E_SET_SPARE                                                        (0x000007BC)
+#define NV857E_SET_SPARE_UNUSED                                                 31:0
+#define NV857E_SET_SPARE_NOOP(b)                                                (0x000007C0 + (b)*0x00000004)
+#define NV857E_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV857E_SURFACE_SET_OFFSET                                               (0x00000800)
+#define NV857E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV857E_SURFACE_SET_SIZE                                                 (0x00000808)
+#define NV857E_SURFACE_SET_SIZE_WIDTH                                           14:0
+#define NV857E_SURFACE_SET_SIZE_HEIGHT                                          30:16
+#define NV857E_SURFACE_SET_STORAGE                                              (0x0000080C)
+#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV857E_SURFACE_SET_STORAGE_PITCH                                        19:8
+#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                20:20
+#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV857E_SURFACE_SET_PARAMS                                               (0x00000810)
+#define NV857E_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV857E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
+#define NV857E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
+#define NV857E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV857E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV857E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
+#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
+#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
+#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
+#define NV857E_SURFACE_SET_PARAMS_RESERVED0                                     22:16
+#define NV857E_SURFACE_SET_PARAMS_RESERVED1                                     24:24
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl857e_h
+
diff --git a/classes/display/cl887d.h b/classes/display/cl887d.h
new file mode 100644
index 0000000..fde2a4a
--- /dev/null
+++ b/classes/display/cl887d.h
@@ -0,0 +1,1078 @@
+/* 
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl887d_h_
+#define _cl887d_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV887D_CORE_CHANNEL_DMA                                                 (0x0000887D)
+
+#define NV887D_CORE_NOTIFIER_2                                                      0x00000000
+#define NV887D_CORE_NOTIFIER_2_SIZEOF                                               0x00000124
+#define NV887D_CORE_NOTIFIER_2_COMPLETION_0                                         0x00000000
+#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE                                    0:0
+#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_R0                                      15:1
+#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_TIMESTAMP                               29:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1                                       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE                                  0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_FALSE                            0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_TRUE                             0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO                         1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO                        2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_R0                                    3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA                        20:20
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS               21:21
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_R1                                    31:22
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_2                                       0x00000002
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_2_R2                                    31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_3                                       0x00000003
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_3_R3                                    31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_4                                       0x00000004
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_4_R4                                    31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_5                                       0x00000005
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_5_R5                                    31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_6                                       0x00000006
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_6_R6                                    31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_7                                       0x00000007
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_7_R7                                    31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_8                                       0x00000008
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_8_R8                                    31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9                              0x00000009
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE                   0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE                    1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_FALSE              0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_TRUE               0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_R0                           31:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10                             0x0000000A
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11                             0x0000000B
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE                  0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_FALSE            0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_TRUE             0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE                   1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE                3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_FALSE          0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_TRUE           0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_R0                          31:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12                             0x0000000C
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13                             0x0000000D
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE                  0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_FALSE            0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_TRUE             0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE                   1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE                3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_FALSE          0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_TRUE           0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_R0                          31:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14                             0x0000000E
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15                             0x0000000F
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE                  0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_FALSE            0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_TRUE             0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE                   1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE                3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_FALSE          0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_TRUE           0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_R0                          31:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16                             0x00000010
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17                             0x00000011
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18                             0x00000012
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19                             0x00000013
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20                             0x00000014
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21                             0x00000015
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22                             0x00000016
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23                             0x00000017
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24                             0x00000018
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25                             0x00000019
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26                             0x0000001A
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27                             0x0000001B
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28                             0x0000001C
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29                             0x0000001D
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30                             0x0000001E
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31                             0x0000001F
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24               1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18                 2:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24                 3:3
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A               4:4
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B               5:5
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS            6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_FALSE      0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_TRUE       0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS                   7:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_FALSE             0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_TRUE              0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI                         9:9
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_FALSE                   0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_TRUE                    0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A                        10:10
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B                        11:11
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_FALSE                  0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_TRUE                   0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_R0                          31:12
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32                             0x00000020
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32_R1                          31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33                            0x00000021
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC                 1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_R0                         31:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34                            0x00000022
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34_R1                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35                            0x00000023
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC                 1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_R0                         31:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36                            0x00000024
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36_R1                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37                            0x00000025
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC                 1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_R0                         31:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38                            0x00000026
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38_R1                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39                            0x00000027
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC               0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC                 1:1
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_FALSE           0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_TRUE            0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_R0                         31:7
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40                            0x00000028
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40_R1                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41                            0x00000029
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE                     0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_FALSE               0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_TRUE                0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_R0                         31:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42                            0x0000002A
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R1                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R2                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43                            0x0000002B
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R3                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R4                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44                            0x0000002C
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R5                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R6                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45                            0x0000002D
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45_R7                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46                            0x0000002E
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46_R8                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47                            0x0000002F
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47_R9                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48                            0x00000030
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48_R10                        31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49                            0x00000031
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE                     0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_FALSE               0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_TRUE                0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_R0                         31:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50                            0x00000032
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R1                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R2                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51                            0x00000033
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R3                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R4                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52                            0x00000034
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R5                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R6                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53                            0x00000035
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53_R7                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54                            0x00000036
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54_R8                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55                            0x00000037
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55_R9                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56                            0x00000038
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56_R10                        31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57                            0x00000039
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE                     0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_FALSE               0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_TRUE                0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_R0                         31:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58                            0x0000003A
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R1                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R2                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59                            0x0000003B
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R3                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R4                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60                            0x0000003C
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R5                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R6                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61                            0x0000003D
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61_R7                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62                            0x0000003E
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62_R8                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63                            0x0000003F
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63_R9                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64                            0x00000040
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64_R10                        31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65                            0x00000041
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE                     0:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_FALSE               0x00000000
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_TRUE                0x00000001
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_R0                         31:2
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66                            0x00000042
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R1                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R2                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67                            0x00000043
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R3                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R4                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68                            0x00000044
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP444          14:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R5                         15:15
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP422          30:16
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R6                         31:31
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69                            0x00000045
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69_R7                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70                            0x00000046
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70_R8                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71                            0x00000047
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71_R9                         31:0
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72                            0x00000048
+#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72_R10                        31:0
+
+
+// dma opcode instructions
+#define NV887D_DMA                                                         0x00000000 
+#define NV887D_DMA_OPCODE                                                       31:29 
+#define NV887D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV887D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV887D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV887D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV887D_DMA_OPCODE                                                       31:29 
+#define NV887D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV887D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV887D_DMA_METHOD_COUNT                                                 27:18 
+#define NV887D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV887D_DMA_DATA                                                          31:0 
+#define NV887D_DMA_NOP                                                     0x00000000 
+#define NV887D_DMA_OPCODE                                                       31:29 
+#define NV887D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV887D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV887D_DMA_OPCODE                                                       31:29 
+#define NV887D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV887D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV887D_PUT                                                              (0x00000000)
+#define NV887D_PUT_PTR                                                          11:2
+#define NV887D_GET                                                              (0x00000004)
+#define NV887D_GET_PTR                                                          11:2
+#define NV887D_UPDATE                                                           (0x00000080)
+#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1                                    8:8
+#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV887D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV887D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV887D_UPDATE_INTERLOCK_WITH_BASE1                                      9:9
+#define NV887D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   10:10
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               11:11
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV887D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV887D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV887D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV887D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV887D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV887D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV887D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV887D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV887D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV887D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV887D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV887D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV887D_SET_SPARE                                                        (0x000003BC)
+#define NV887D_SET_SPARE_UNUSED                                                 31:0
+#define NV887D_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV887D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV887D_DAC_SET_CONTROL(a)                                               (0x00000400 + (a)*0x00000080)
+#define NV887D_DAC_SET_CONTROL_OWNER                                            3:0
+#define NV887D_DAC_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV887D_DAC_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV887D_DAC_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV887D_DAC_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV887D_DAC_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV887D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV887D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV887D_DAC_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL                                         13:8
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M                             (0x00000001)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J                             (0x00000002)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI                          (0x00000003)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M                              (0x00000004)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N                              (0x00000005)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN                             (0x00000006)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M                             (0x00000007)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J                             (0x00000008)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI                          (0x00000009)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M                              (0x0000000A)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N                              (0x0000000B)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN                             (0x0000000C)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60                            (0x0000000D)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50                            (0x0000000E)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50                            (0x0000000F)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60                            (0x00000010)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50                           (0x00000011)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60                           (0x00000012)
+#define NV887D_DAC_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000003F)
+#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD                           14:14
+#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE                     (0x00000000)
+#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE                      (0x00000001)
+#define NV887D_DAC_SET_POLARITY(a)                                              (0x00000404 + (a)*0x00000080)
+#define NV887D_DAC_SET_POLARITY_HSYNC                                           0:0
+#define NV887D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV887D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV887D_DAC_SET_POLARITY_VSYNC                                           1:1
+#define NV887D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE                             (0x00000000)
+#define NV887D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE                             (0x00000001)
+#define NV887D_DAC_SET_POLARITY_RESERVED                                        31:2
+#define NV887D_DAC_SET_ENCODE_QUALITY(a)                                        (0x00000420 + (a)*0x00000080)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS                     7:7
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375            (0x00000000)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75             (0x00000001)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN                                2:0
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0                           (0x00000000)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625                      (0x00000001)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125                       (0x00000002)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25                        (0x00000003)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5                         (0x00000004)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0                         (0x00000005)
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN                              6:4
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0                         (0x00000000)
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625                    (0x00000001)
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125                     (0x00000002)
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25                      (0x00000003)
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5                       (0x00000004)
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0                       (0x00000005)
+#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH                               15:8
+#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH                             23:16
+#define NV887D_DAC_SET_ENCODE_QUALITY_TINT                                      31:24
+#define NV887D_DAC_UPDATE_ENCODER_PRESET(a)                                     (0x0000047C + (a)*0x00000080)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL                               5:0
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT                       (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M                   (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J                   (0x00000002)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI                (0x00000003)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M                    (0x00000004)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N                    (0x00000005)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN                   (0x00000006)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M                   (0x00000007)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J                   (0x00000008)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI                (0x00000009)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M                    (0x0000000A)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N                    (0x0000000B)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN                   (0x0000000C)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60                  (0x0000000D)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50                  (0x0000000E)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50                  (0x0000000F)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60                  (0x00000010)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50                 (0x00000011)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60                 (0x00000012)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM                        (0x0000003F)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT                            6:6
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB                        (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV                        (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R                       7:7
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE               (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE                (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G                       8:8
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE               (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE                (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B                       9:9
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE               (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE                (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH                             12:10
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE                        (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358                  (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358                    (0x00000002)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443                  (0x00000003)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443                    (0x00000004)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW                       13:13
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6                (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4                (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER                            15:15
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW                     (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE                       (0x00000001)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER                            16:16
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW                     (0x00000000)
+#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE                       (0x00000001)
+
+#define NV887D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
+#define NV887D_SOR_SET_CONTROL_OWNER                                            3:0
+#define NV887D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
+#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
+#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
+#define NV887D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
+#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
+#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
+#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
+#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
+#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
+#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
+#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
+#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
+#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
+
+#define NV887D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
+#define NV887D_PIOR_SET_CONTROL_OWNER                                           3:0
+#define NV887D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
+#define NV887D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
+#define NV887D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
+#define NV887D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
+#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
+#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
+#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
+#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
+#define NV887D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV887D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV887D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
+#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
+#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
+#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
+#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH                                     19:16
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                             (0x00000000)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                          (0x00000001)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                          (0x00000002)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                          (0x00000003)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                          (0x00000004)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                          (0x00000005)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                          (0x00000006)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                          (0x00000007)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                          (0x00000008)
+#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                          (0x00000009)
+
+#define NV887D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000800 + (a)*0x00000400)
+#define NV887D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV887D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV887D_HEAD_SET_PIXEL_CLOCK(a)                                          (0x00000804 + (a)*0x00000400)
+#define NV887D_HEAD_SET_PIXEL_CLOCK_FREQUENCY                                   21:0
+#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE                                        23:22
+#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25                                 (0x00000000)
+#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28                                 (0x00000001)
+#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM                             (0x00000002)
+#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001                              24:24
+#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE                        (0x00000000)
+#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE                         (0x00000001)
+#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER                                  25:25
+#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE                            (0x00000000)
+#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE                             (0x00000001)
+#define NV887D_HEAD_SET_CONTROL(a)                                              (0x00000808 + (a)*0x00000400)
+#define NV887D_HEAD_SET_CONTROL_STRUCTURE                                       2:1
+#define NV887D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV887D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000810 + (a)*0x00000400)
+#define NV887D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV887D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV887D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV887D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000814 + (a)*0x00000400)
+#define NV887D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV887D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV887D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000818 + (a)*0x00000400)
+#define NV887D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV887D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV887D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000081C + (a)*0x00000400)
+#define NV887D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV887D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV887D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000820 + (a)*0x00000400)
+#define NV887D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV887D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV887D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000824 + (a)*0x00000400)
+#define NV887D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV887D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV887D_HEAD_SET_RASTER_VERT_BLANK_DMI(a)                                (0x00000828 + (a)*0x00000400)
+#define NV887D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION                          11:0
+#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000082C + (a)*0x00000400)
+#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV887D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000840 + (a)*0x00000400)
+#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV887D_HEAD_SET_BASE_LUT_LO_MODE                                        30:30
+#define NV887D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV887D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV887D_HEAD_SET_BASE_LUT_LO_ORIGIN                                      7:2
+#define NV887D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000844 + (a)*0x00000400)
+#define NV887D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000848 + (a)*0x00000400)
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      30:30
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN                                    7:2
+#define NV887D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000084C + (a)*0x00000400)
+#define NV887D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV887D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000085C + (a)*0x00000400)
+#define NV887D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV887D_HEAD_SET_OFFSET(a,b)                                             (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
+#define NV887D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV887D_HEAD_SET_SIZE(a)                                                 (0x00000868 + (a)*0x00000400)
+#define NV887D_HEAD_SET_SIZE_WIDTH                                              14:0
+#define NV887D_HEAD_SET_SIZE_HEIGHT                                             30:16
+#define NV887D_HEAD_SET_STORAGE(a)                                              (0x0000086C + (a)*0x00000400)
+#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV887D_HEAD_SET_STORAGE_PITCH                                           17:8
+#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   20:20
+#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV887D_HEAD_SET_PARAMS(a)                                               (0x00000870 + (a)*0x00000400)
+#define NV887D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV887D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV887D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV887D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV887D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV887D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV887D_HEAD_SET_PARAMS_RESERVED0                                        22:16
+#define NV887D_HEAD_SET_PARAMS_RESERVED1                                        24:24
+#define NV887D_HEAD_SET_CONTEXT_DMAS_ISO(a,b)                                   (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
+#define NV887D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV887D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000880 + (a)*0x00000400)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
+#define NV887D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
+#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER                                5:4
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE                           (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0                       (0x00000001)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1                       (0x00000002)
+#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH                           (0x00000003)
+#define NV887D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000884 + (a)*0x00000400)
+#define NV887D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
+#define NV887D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000089C + (a)*0x00000400)
+#define NV887D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
+#define NV887D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000008A0 + (a)*0x00000400)
+#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV887D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV887D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV887D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV887D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV887D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x000008A4 + (a)*0x00000400)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV887D_HEAD_SET_PROCAMP(a)                                              (0x000008A8 + (a)*0x00000400)
+#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV887D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV887D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV887D_HEAD_SET_PROCAMP_TRANSITION                                      4:3
+#define NV887D_HEAD_SET_PROCAMP_TRANSITION_HARD                                 (0x00000000)
+#define NV887D_HEAD_SET_PROCAMP_TRANSITION_NTSC                                 (0x00000001)
+#define NV887D_HEAD_SET_PROCAMP_TRANSITION_PAL                                  (0x00000002)
+#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV887D_HEAD_SET_VIEWPORT_POINT_IN(a,b)                                  (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV887D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV887D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000008C8 + (a)*0x00000400)
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000008D4 + (a)*0x00000400)
+#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000008D8 + (a)*0x00000400)
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000008DC + (a)*0x00000400)
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x00000900 + (a)*0x00000400)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x00000904 + (a)*0x00000400)
+#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV887D_HEAD_SET_PROCESSING(a)                                           (0x00000910 + (a)*0x00000400)
+#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV887D_HEAD_SET_CONVERSION(a)                                           (0x00000914 + (a)*0x00000400)
+#define NV887D_HEAD_SET_CONVERSION_GAIN                                         15:0
+#define NV887D_HEAD_SET_CONVERSION_OFS                                          31:16
+#define NV887D_HEAD_SET_SPARE(a)                                                (0x00000BBC + (a)*0x00000400)
+#define NV887D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV887D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004)
+#define NV887D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl887d_h
+
diff --git a/classes/display/cl907a.h b/classes/display/cl907a.h
new file mode 100644
index 0000000..c1a23c0
--- /dev/null
+++ b/classes/display/cl907a.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl907a_h_
+#define _cl907a_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV907A_CURSOR_CHANNEL_PIO                                               (0x0000907A)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetCursorHotSpotPointOut;                                             // 0x00000084 - 0x00000087
+    NvV32 Reserved02[0x3DE];
+} GF110DispCursorControlPio;
+
+#define NV907A_FREE                                                             (0x00000008)
+#define NV907A_FREE_COUNT                                                       5:0
+#define NV907A_UPDATE                                                           (0x00000080)
+#define NV907A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV907A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV907A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT                                    (0x00000084)
+#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
+#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl907a_h
+
diff --git a/classes/display/cl907b.h b/classes/display/cl907b.h
new file mode 100644
index 0000000..7450c59
--- /dev/null
+++ b/classes/display/cl907b.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl907b_h_
+#define _cl907b_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV907B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000907B)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetPointOut;                                                          // 0x00000084 - 0x00000087
+    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000088 - 0x0000008B
+    NvV32 Reserved02[0x3DD];
+} GF110DispOverlayImmControlPio;
+
+#define NV907B_FREE                                                             (0x00000008)
+#define NV907B_FREE_COUNT                                                       5:0
+#define NV907B_UPDATE                                                           (0x00000080)
+#define NV907B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV907B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV907B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV907B_SET_POINT_OUT                                                    (0x00000084)
+#define NV907B_SET_POINT_OUT_X                                                  15:0
+#define NV907B_SET_POINT_OUT_Y                                                  31:16
+#define NV907B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000088)
+#define NV907B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl907b_h
+
diff --git a/classes/display/cl907c.h b/classes/display/cl907c.h
new file mode 100644
index 0000000..9f280db
--- /dev/null
+++ b/classes/display/cl907c.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl907c_h_
+#define _cl907c_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV907C_BASE_CHANNEL_DMA                                                 (0x0000907C)
+
+#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
+#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
+#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
+
+
+// dma opcode instructions
+#define NV907C_DMA                                                         0x00000000 
+#define NV907C_DMA_OPCODE                                                       31:29 
+#define NV907C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV907C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV907C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV907C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV907C_DMA_OPCODE                                                       31:29 
+#define NV907C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV907C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV907C_DMA_METHOD_COUNT                                                 27:18 
+#define NV907C_DMA_METHOD_OFFSET                                                 11:2 
+#define NV907C_DMA_DATA                                                          31:0 
+#define NV907C_DMA_DATA_NOP                                                0x00000000 
+#define NV907C_DMA_OPCODE                                                       31:29 
+#define NV907C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV907C_DMA_JUMP_OFFSET                                                   11:2 
+#define NV907C_DMA_OPCODE                                                       31:29 
+#define NV907C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV907C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV907C_PUT                                                              (0x00000000)
+#define NV907C_PUT_PTR                                                          11:2
+#define NV907C_GET                                                              (0x00000004)
+#define NV907C_GET_PTR                                                          11:2
+#define NV907C_GET_SCANLINE                                                     (0x00000010)
+#define NV907C_GET_SCANLINE_LINE                                                15:0
+#define NV907C_UPDATE                                                           (0x00000080)
+#define NV907C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV907C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV907C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV907C_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV907C_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV907C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV907C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV907C_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV907C_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
+#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
+#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_AT_FRAME                          (0x00000003)
+#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               2:2
+#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
+#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
+#define NV907C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV907C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
+#define NV907C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
+#define NV907C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
+#define NV907C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV907C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
+#define NV907C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
+#define NV907C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
+#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
+#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
+#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
+#define NV907C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
+#define NV907C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV907C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
+#define NV907C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV907C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV907C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV907C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV907C_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV907C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV907C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV907C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV907C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
+#define NV907C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
+#define NV907C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
+#define NV907C_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV907C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV907C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV907C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV907C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV907C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
+#define NV907C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
+#define NV907C_SET_BASE_LUT_LO                                                  (0x000000E0)
+#define NV907C_SET_BASE_LUT_LO_ENABLE                                           31:30
+#define NV907C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
+#define NV907C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
+#define NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000002)
+#define NV907C_SET_BASE_LUT_LO_MODE                                             27:24
+#define NV907C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
+#define NV907C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
+#define NV907C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                      (0x00000003)
+#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE                (0x00000004)
+#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE               (0x00000005)
+#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE                (0x00000006)
+#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE                 (0x00000007)
+#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE                (0x00000008)
+#define NV907C_SET_BASE_LUT_HI                                                  (0x000000E4)
+#define NV907C_SET_BASE_LUT_HI_ORIGIN                                           31:0
+#define NV907C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
+#define NV907C_SET_OUTPUT_LUT_LO_ENABLE                                         31:30
+#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
+#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT                            (0x00000001)
+#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000002)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE                                           27:24
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                    (0x00000003)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE              (0x00000004)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE             (0x00000005)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE              (0x00000006)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE               (0x00000007)
+#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE              (0x00000008)
+#define NV907C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
+#define NV907C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
+#define NV907C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
+#define NV907C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV907C_SET_PROCESSING                                                   (0x00000110)
+#define NV907C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV907C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV907C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV907C_SET_CONVERSION_RED                                               (0x00000114)
+#define NV907C_SET_CONVERSION_RED_GAIN                                          15:0
+#define NV907C_SET_CONVERSION_RED_OFS                                           31:16
+#define NV907C_SET_CONVERSION_GRN                                               (0x00000118)
+#define NV907C_SET_CONVERSION_GRN_GAIN                                          15:0
+#define NV907C_SET_CONVERSION_GRN_OFS                                           31:16
+#define NV907C_SET_CONVERSION_BLU                                               (0x0000011C)
+#define NV907C_SET_CONVERSION_BLU_GAIN                                          15:0
+#define NV907C_SET_CONVERSION_BLU_OFS                                           31:16
+#define NV907C_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV907C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV907C_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV907C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV907C_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV907C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV907C_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV907C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV907C_SET_CSC_RED2RED                                                  (0x00000140)
+#define NV907C_SET_CSC_RED2RED_OWNER                                            31:31
+#define NV907C_SET_CSC_RED2RED_OWNER_CORE                                       (0x00000000)
+#define NV907C_SET_CSC_RED2RED_OWNER_BASE                                       (0x00000001)
+#define NV907C_SET_CSC_RED2RED_COEFF                                            18:0
+#define NV907C_SET_CSC_GRN2RED                                                  (0x00000144)
+#define NV907C_SET_CSC_GRN2RED_COEFF                                            18:0
+#define NV907C_SET_CSC_BLU2RED                                                  (0x00000148)
+#define NV907C_SET_CSC_BLU2RED_COEFF                                            18:0
+#define NV907C_SET_CSC_CONSTANT2RED                                             (0x0000014C)
+#define NV907C_SET_CSC_CONSTANT2RED_COEFF                                       18:0
+#define NV907C_SET_CSC_RED2GRN                                                  (0x00000150)
+#define NV907C_SET_CSC_RED2GRN_COEFF                                            18:0
+#define NV907C_SET_CSC_GRN2GRN                                                  (0x00000154)
+#define NV907C_SET_CSC_GRN2GRN_COEFF                                            18:0
+#define NV907C_SET_CSC_BLU2GRN                                                  (0x00000158)
+#define NV907C_SET_CSC_BLU2GRN_COEFF                                            18:0
+#define NV907C_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
+#define NV907C_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
+#define NV907C_SET_CSC_RED2BLU                                                  (0x00000160)
+#define NV907C_SET_CSC_RED2BLU_COEFF                                            18:0
+#define NV907C_SET_CSC_GRN2BLU                                                  (0x00000164)
+#define NV907C_SET_CSC_GRN2BLU_COEFF                                            18:0
+#define NV907C_SET_CSC_BLU2BLU                                                  (0x00000168)
+#define NV907C_SET_CSC_BLU2BLU_COEFF                                            18:0
+#define NV907C_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
+#define NV907C_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
+#define NV907C_SET_SPARE                                                        (0x000003BC)
+#define NV907C_SET_SPARE_UNUSED                                                 31:0
+#define NV907C_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV907C_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV907C_SURFACE_SET_OFFSET(a,b)                                          (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
+#define NV907C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV907C_SURFACE_SET_SIZE(a)                                              (0x00000408 + (a)*0x00000020)
+#define NV907C_SURFACE_SET_SIZE_WIDTH                                           15:0
+#define NV907C_SURFACE_SET_SIZE_HEIGHT                                          31:16
+#define NV907C_SURFACE_SET_STORAGE(a)                                           (0x0000040C + (a)*0x00000020)
+#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV907C_SURFACE_SET_STORAGE_PITCH                                        20:8
+#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
+#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV907C_SURFACE_SET_PARAMS(a)                                            (0x00000410 + (a)*0x00000020)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
+#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
+#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
+#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
+#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
+#define NV907C_SURFACE_SET_PARAMS_GAMMA                                         2:2
+#define NV907C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
+#define NV907C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
+#define NV907C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
+#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
+#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
+#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl907c_h
diff --git a/classes/display/cl907d.h b/classes/display/cl907d.h
new file mode 100644
index 0000000..d2bf4ab
--- /dev/null
+++ b/classes/display/cl907d.h
@@ -0,0 +1,1140 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl907d_h_
+#define _cl907d_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV907D_CORE_CHANNEL_DMA                                                 (0x0000907D)
+
+#define NV907D_CORE_NOTIFIER_3                                                      0x00000000
+#define NV907D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
+#define NV907D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
+#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
+#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
+#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
+#define NV907D_CORE_NOTIFIER_3__1                                                   0x00000001
+#define NV907D_CORE_NOTIFIER_3__1_R1                                                31:0
+#define NV907D_CORE_NOTIFIER_3__2                                                   0x00000002
+#define NV907D_CORE_NOTIFIER_3__2_R2                                                31:0
+#define NV907D_CORE_NOTIFIER_3__3                                                   0x00000003
+#define NV907D_CORE_NOTIFIER_3__3_R3                                                31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:27
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
+#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
+
+
+// dma opcode instructions
+#define NV907D_DMA                                                         0x00000000 
+#define NV907D_DMA_OPCODE                                                       31:29 
+#define NV907D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV907D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV907D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV907D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV907D_DMA_OPCODE                                                       31:29 
+#define NV907D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV907D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV907D_DMA_METHOD_COUNT                                                 27:18 
+#define NV907D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV907D_DMA_DATA                                                          31:0 
+#define NV907D_DMA_DATA_NOP                                                0x00000000 
+#define NV907D_DMA_OPCODE                                                       31:29 
+#define NV907D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV907D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV907D_DMA_OPCODE                                                       31:29 
+#define NV907D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV907D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV907D_PUT                                                              (0x00000000)
+#define NV907D_PUT_PTR                                                          11:2
+#define NV907D_GET                                                              (0x00000004)
+#define NV907D_GET_PTR                                                          11:2
+#define NV907D_UPDATE                                                           (0x00000080)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
+#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
+#define NV907D_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV907D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV907D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV907D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV907D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV907D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV907D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV907D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV907D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV907D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV907D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV907D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV907D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV907D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV907D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV907D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV907D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV907D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV907D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV907D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV907D_SET_SPARE                                                        (0x0000016C)
+#define NV907D_SET_SPARE_UNUSED                                                 31:0
+#define NV907D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
+#define NV907D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV907D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
+#define NV907D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV907D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV907D_DAC_SET_CONTROL_PROTOCOL                                         12:8
+#define NV907D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV907D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
+#define NV907D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
+#define NV907D_DAC_SET_SW_SPARE_A_CODE                                          31:0
+#define NV907D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
+#define NV907D_DAC_SET_SW_SPARE_B_CODE                                          31:0
+#define NV907D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
+#define NV907D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV907D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
+#define NV907D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV907D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV907D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV907D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV907D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV907D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV907D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
+#define NV907D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NV907D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
+#define NV907D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+#define NV907D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
+#define NV907D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV907D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
+#define NV907D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
+#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
+#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
+#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
+#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
+#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
+#define NV907D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV907D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV907D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV907D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
+#define NV907D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
+#define NV907D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
+#define NV907D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
+#define NV907D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
+#define NV907D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
+
+#define NV907D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
+#define NV907D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV907D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
+#define NV907D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
+#define NV907D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV907D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
+#define NV907D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV907D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV907D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV907D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
+#define NV907D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV907D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV907D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
+#define NV907D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV907D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV907D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
+#define NV907D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV907D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV907D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
+#define NV907D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV907D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV907D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
+#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
+#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV907D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
+#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
+#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
+#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
+#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
+#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
+#define NV907D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
+#define NV907D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
+#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
+#define NV907D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
+#define NV907D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NV907D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV907D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
+#define NV907D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV907D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
+#define NV907D_HEAD_SET_SIZE_WIDTH                                              15:0
+#define NV907D_HEAD_SET_SIZE_HEIGHT                                             31:16
+#define NV907D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
+#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV907D_HEAD_SET_STORAGE_PITCH                                           20:8
+#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
+#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV907D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
+#define NV907D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV907D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
+#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
+#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV907D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV907D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV907D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV907D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE                                     26:26
+#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               13:8
+#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               21:16
+#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV907D_HEAD_SET_OFFSET_CURSOR(a)                                        (0x00000484 + (a)*0x00000300)
+#define NV907D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
+#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR(a)                                   (0x0000048C + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
+#define NV907D_HEAD_SET_DITHER_CONTROL(a)                                       (0x00000490 + (a)*0x00000300)
+#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV907D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
+#define NV907D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NV907D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV907D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
+#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV907D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV907D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV907D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
+#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
+#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
+#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
+#define NV907D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
+#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV907D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
+#define NV907D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
+#define NV907D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
+#define NV907D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
+#define NV907D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
+#define NV907D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
+#define NV907D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
+#define NV907D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
+#define NV907D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NV907D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
+#define NV907D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NV907D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
+#define NV907D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NV907D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
+#define NV907D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NV907D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
+#define NV907D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NV907D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
+#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
+#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
+#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
+#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
+#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
+#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
+#define NV907D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
+#define NV907D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV907D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
+#define NV907D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl907d_h
diff --git a/classes/display/cl907e.h b/classes/display/cl907e.h
new file mode 100644
index 0000000..631fe6d
--- /dev/null
+++ b/classes/display/cl907e.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl907e_h_
+#define _cl907e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV907E_OVERLAY_CHANNEL_DMA                                              (0x0000907E)
+
+#define NV_DISP_NOTIFICATION_2                                                       0x00000000
+#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
+#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
+#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
+#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
+#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
+#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
+#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
+#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
+#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
+
+
+#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
+#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
+#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
+#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
+
+
+#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
+#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
+
+
+// dma opcode instructions
+#define NV907E_DMA                                                         0x00000000 
+#define NV907E_DMA_OPCODE                                                       31:29 
+#define NV907E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV907E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV907E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV907E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV907E_DMA_OPCODE                                                       31:29 
+#define NV907E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV907E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV907E_DMA_METHOD_COUNT                                                 27:18 
+#define NV907E_DMA_METHOD_OFFSET                                                 11:2 
+#define NV907E_DMA_DATA                                                          31:0 
+#define NV907E_DMA_DATA_NOP                                                0x00000000 
+#define NV907E_DMA_OPCODE                                                       31:29 
+#define NV907E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV907E_DMA_JUMP_OFFSET                                                   11:2 
+#define NV907E_DMA_OPCODE                                                       31:29 
+#define NV907E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV907E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV907E_PUT                                                              (0x00000000)
+#define NV907E_PUT_PTR                                                          11:2
+#define NV907E_GET                                                              (0x00000004)
+#define NV907E_GET_PTR                                                          11:2
+#define NV907E_UPDATE                                                           (0x00000080)
+#define NV907E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV907E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV907E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV907E_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV907E_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV907E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV907E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV907E_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV907E_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
+#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
+#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
+#define NV907E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV907E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
+#define NV907E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV907E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
+#define NV907E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV907E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
+#define NV907E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
+#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
+#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
+#define NV907E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV907E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV907E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV907E_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV907E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV907E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV907E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV907E_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV907E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV907E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV907E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV907E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV907E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
+#define NV907E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV907E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
+#define NV907E_SET_OVERLAY_LUT_LO_ENABLE                                        31:31
+#define NV907E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
+#define NV907E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE                                          27:24
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                   (0x00000003)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE             (0x00000004)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE            (0x00000005)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE             (0x00000006)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE              (0x00000007)
+#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE             (0x00000008)
+#define NV907E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
+#define NV907E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
+#define NV907E_SET_CONTEXT_DMA_ISO                                              (0x000000C0)
+#define NV907E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
+#define NV907E_SET_POINT_IN                                                     (0x000000E0)
+#define NV907E_SET_POINT_IN_X                                                   14:0
+#define NV907E_SET_POINT_IN_Y                                                   30:16
+#define NV907E_SET_SIZE_IN                                                      (0x000000E4)
+#define NV907E_SET_SIZE_IN_WIDTH                                                14:0
+#define NV907E_SET_SIZE_IN_HEIGHT                                               30:16
+#define NV907E_SET_SIZE_OUT                                                     (0x000000E8)
+#define NV907E_SET_SIZE_OUT_WIDTH                                               14:0
+#define NV907E_SET_COMPOSITION_CONTROL                                          (0x00000100)
+#define NV907E_SET_COMPOSITION_CONTROL_MODE                                     3:0
+#define NV907E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
+#define NV907E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
+#define NV907E_SET_COMPOSITION_CONTROL_MODE_OPAQUE                              (0x00000002)
+#define NV907E_SET_KEY_COLOR_LO                                                 (0x00000104)
+#define NV907E_SET_KEY_COLOR_LO_COLOR                                           31:0
+#define NV907E_SET_KEY_COLOR_HI                                                 (0x00000108)
+#define NV907E_SET_KEY_COLOR_HI_COLOR                                           31:0
+#define NV907E_SET_KEY_MASK_LO                                                  (0x0000010C)
+#define NV907E_SET_KEY_MASK_LO_MASK                                             31:0
+#define NV907E_SET_KEY_MASK_HI                                                  (0x00000110)
+#define NV907E_SET_KEY_MASK_HI_MASK                                             31:0
+#define NV907E_SET_PROCESSING                                                   (0x00000118)
+#define NV907E_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV907E_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV907E_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV907E_SET_CONVERSION_RED                                               (0x0000011C)
+#define NV907E_SET_CONVERSION_RED_GAIN                                          15:0
+#define NV907E_SET_CONVERSION_RED_OFS                                           31:16
+#define NV907E_SET_CONVERSION_GRN                                               (0x00000120)
+#define NV907E_SET_CONVERSION_GRN_GAIN                                          15:0
+#define NV907E_SET_CONVERSION_GRN_OFS                                           31:16
+#define NV907E_SET_CONVERSION_BLU                                               (0x00000124)
+#define NV907E_SET_CONVERSION_BLU_GAIN                                          15:0
+#define NV907E_SET_CONVERSION_BLU_OFS                                           31:16
+#define NV907E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV907E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV907E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV907E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV907E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV907E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV907E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV907E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV907E_SET_CSC_RED2RED                                                  (0x00000140)
+#define NV907E_SET_CSC_RED2RED_COEFF                                            18:0
+#define NV907E_SET_CSC_GRN2RED                                                  (0x00000144)
+#define NV907E_SET_CSC_GRN2RED_COEFF                                            18:0
+#define NV907E_SET_CSC_BLU2RED                                                  (0x00000148)
+#define NV907E_SET_CSC_BLU2RED_COEFF                                            18:0
+#define NV907E_SET_CSC_CONSTANT2RED                                             (0x0000014C)
+#define NV907E_SET_CSC_CONSTANT2RED_COEFF                                       18:0
+#define NV907E_SET_CSC_RED2GRN                                                  (0x00000150)
+#define NV907E_SET_CSC_RED2GRN_COEFF                                            18:0
+#define NV907E_SET_CSC_GRN2GRN                                                  (0x00000154)
+#define NV907E_SET_CSC_GRN2GRN_COEFF                                            18:0
+#define NV907E_SET_CSC_BLU2GRN                                                  (0x00000158)
+#define NV907E_SET_CSC_BLU2GRN_COEFF                                            18:0
+#define NV907E_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
+#define NV907E_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
+#define NV907E_SET_CSC_RED2BLU                                                  (0x00000160)
+#define NV907E_SET_CSC_RED2BLU_COEFF                                            18:0
+#define NV907E_SET_CSC_GRN2BLU                                                  (0x00000164)
+#define NV907E_SET_CSC_GRN2BLU_COEFF                                            18:0
+#define NV907E_SET_CSC_BLU2BLU                                                  (0x00000168)
+#define NV907E_SET_CSC_BLU2BLU_COEFF                                            18:0
+#define NV907E_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
+#define NV907E_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
+#define NV907E_SET_SPARE                                                        (0x000003BC)
+#define NV907E_SET_SPARE_UNUSED                                                 31:0
+#define NV907E_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV907E_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV907E_SURFACE_SET_OFFSET                                               (0x00000400)
+#define NV907E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV907E_SURFACE_SET_SIZE                                                 (0x00000408)
+#define NV907E_SURFACE_SET_SIZE_WIDTH                                           15:0
+#define NV907E_SURFACE_SET_SIZE_HEIGHT                                          31:16
+#define NV907E_SURFACE_SET_STORAGE                                              (0x0000040C)
+#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV907E_SURFACE_SET_STORAGE_PITCH                                        20:8
+#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
+#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV907E_SURFACE_SET_PARAMS                                               (0x00000410)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
+#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
+#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
+#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
+#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
+#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl907e_h
diff --git a/classes/display/cl917a.h b/classes/display/cl917a.h
new file mode 100644
index 0000000..b6d6239
--- /dev/null
+++ b/classes/display/cl917a.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl917a_h_
+#define _cl917a_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV917A_CURSOR_CHANNEL_PIO                                               (0x0000917A)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetCursorHotSpotPointsOut[2];                                         // 0x00000084 - 0x0000008B
+    NvV32 Reserved02[0x3DD];
+} GK104DispCursorControlPio;
+
+#define NV917A_FREE                                                             (0x00000008)
+#define NV917A_FREE_COUNT                                                       5:0
+#define NV917A_UPDATE                                                           (0x00000080)
+#define NV917A_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV917A_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV917A_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT(b)                                (0x00000084 + (b)*0x00000004)
+#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_X                                 15:0
+#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_Y                                 31:16
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl917a_h
+
diff --git a/classes/display/cl917b.h b/classes/display/cl917b.h
new file mode 100644
index 0000000..05270e2
--- /dev/null
+++ b/classes/display/cl917b.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl917b_h_
+#define _cl917b_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV917B_OVERLAY_IMM_CHANNEL_PIO                                          (0x0000917B)
+
+typedef volatile struct {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x1D];
+    NvV32 Update;                                                               // 0x00000080 - 0x00000083
+    NvV32 SetPointsOut[2];                                                      // 0x00000084 - 0x0000008B
+    NvV32 Reserved02[0x1];
+    NvV32 AwakenOnceFlippedTo;                                                  // 0x00000090 - 0x00000093
+    NvV32 Reserved03[0x3DB];
+} GK104DispOverlayImmControlPio;
+
+#define NV917B_FREE                                                             (0x00000008)
+#define NV917B_FREE_COUNT                                                       5:0
+#define NV917B_UPDATE                                                           (0x00000080)
+#define NV917B_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV917B_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV917B_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV917B_SET_POINTS_OUT(b)                                                (0x00000084 + (b)*0x00000004)
+#define NV917B_SET_POINTS_OUT_X                                                 15:0
+#define NV917B_SET_POINTS_OUT_Y                                                 31:16
+#define NV917B_AWAKEN_ONCE_FLIPPED_TO                                           (0x00000090)
+#define NV917B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT                              11:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl917b_h
+
diff --git a/classes/display/cl917c.h b/classes/display/cl917c.h
new file mode 100644
index 0000000..9870f36
--- /dev/null
+++ b/classes/display/cl917c.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl917c_h_
+#define _cl917c_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV917C_BASE_CHANNEL_DMA                                                 (0x0000917C)
+
+#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
+#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
+#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
+
+
+#define NV_DISP_NOTIFICATION_2                                                       0x00000000
+#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
+#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
+#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
+#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
+#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
+#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
+#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
+#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
+#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
+
+
+#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
+#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
+#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
+#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
+
+
+#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
+#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
+
+
+// dma opcode instructions
+#define NV917C_DMA                                                         0x00000000 
+#define NV917C_DMA_OPCODE                                                       31:29 
+#define NV917C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV917C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV917C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV917C_DMA_OPCODE                                                       31:29 
+#define NV917C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV917C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV917C_DMA_METHOD_COUNT                                                 27:18 
+#define NV917C_DMA_METHOD_OFFSET                                                 11:2 
+#define NV917C_DMA_DATA                                                          31:0 
+#define NV917C_DMA_DATA_NOP                                                0x00000000 
+#define NV917C_DMA_OPCODE                                                       31:29 
+#define NV917C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV917C_DMA_JUMP_OFFSET                                                   11:2 
+#define NV917C_DMA_OPCODE                                                       31:29 
+#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV917C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV917C_PUT                                                              (0x00000000)
+#define NV917C_PUT_PTR                                                          11:2
+#define NV917C_GET                                                              (0x00000004)
+#define NV917C_GET_PTR                                                          11:2
+#define NV917C_GET_SCANLINE                                                     (0x00000010)
+#define NV917C_GET_SCANLINE_LINE                                                15:0
+#define NV917C_UPDATE                                                           (0x00000080)
+#define NV917C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV917C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV917C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV917C_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV917C_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV917C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV917C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV917C_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV917C_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
+#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
+#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               2:2
+#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
+#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
+#define NV917C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV917C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
+#define NV917C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
+#define NV917C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
+#define NV917C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV917C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
+#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
+#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
+#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
+#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
+#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
+#define NV917C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
+#define NV917C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV917C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
+#define NV917C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV917C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV917C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV917C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV917C_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV917C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV917C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
+#define NV917C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
+#define NV917C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
+#define NV917C_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV917C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV917C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV917C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
+#define NV917C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
+#define NV917C_SET_BASE_LUT_LO                                                  (0x000000E0)
+#define NV917C_SET_BASE_LUT_LO_ENABLE                                           31:30
+#define NV917C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
+#define NV917C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
+#define NV917C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000002)
+#define NV917C_SET_BASE_LUT_LO_MODE                                             27:24
+#define NV917C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
+#define NV917C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
+#define NV917C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                      (0x00000003)
+#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE                (0x00000004)
+#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE               (0x00000005)
+#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE                (0x00000006)
+#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE                 (0x00000007)
+#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE                (0x00000008)
+#define NV917C_SET_BASE_LUT_HI                                                  (0x000000E4)
+#define NV917C_SET_BASE_LUT_HI_ORIGIN                                           31:0
+#define NV917C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
+#define NV917C_SET_OUTPUT_LUT_LO_ENABLE                                         31:30
+#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
+#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT                            (0x00000001)
+#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000002)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE                                           27:24
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                    (0x00000003)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE              (0x00000004)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE             (0x00000005)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE              (0x00000006)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE               (0x00000007)
+#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE              (0x00000008)
+#define NV917C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
+#define NV917C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
+#define NV917C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
+#define NV917C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV917C_SET_PROCESSING                                                   (0x00000110)
+#define NV917C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV917C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV917C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV917C_SET_CONVERSION_RED                                               (0x00000114)
+#define NV917C_SET_CONVERSION_RED_GAIN                                          15:0
+#define NV917C_SET_CONVERSION_RED_OFS                                           31:16
+#define NV917C_SET_CONVERSION_GRN                                               (0x00000118)
+#define NV917C_SET_CONVERSION_GRN_GAIN                                          15:0
+#define NV917C_SET_CONVERSION_GRN_OFS                                           31:16
+#define NV917C_SET_CONVERSION_BLU                                               (0x0000011C)
+#define NV917C_SET_CONVERSION_BLU_GAIN                                          15:0
+#define NV917C_SET_CONVERSION_BLU_OFS                                           31:16
+#define NV917C_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV917C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV917C_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV917C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV917C_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV917C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV917C_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV917C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV917C_SET_CSC_RED2RED                                                  (0x00000140)
+#define NV917C_SET_CSC_RED2RED_OWNER                                            31:31
+#define NV917C_SET_CSC_RED2RED_OWNER_CORE                                       (0x00000000)
+#define NV917C_SET_CSC_RED2RED_OWNER_BASE                                       (0x00000001)
+#define NV917C_SET_CSC_RED2RED_COEFF                                            18:0
+#define NV917C_SET_CSC_GRN2RED                                                  (0x00000144)
+#define NV917C_SET_CSC_GRN2RED_COEFF                                            18:0
+#define NV917C_SET_CSC_BLU2RED                                                  (0x00000148)
+#define NV917C_SET_CSC_BLU2RED_COEFF                                            18:0
+#define NV917C_SET_CSC_CONSTANT2RED                                             (0x0000014C)
+#define NV917C_SET_CSC_CONSTANT2RED_COEFF                                       18:0
+#define NV917C_SET_CSC_RED2GRN                                                  (0x00000150)
+#define NV917C_SET_CSC_RED2GRN_COEFF                                            18:0
+#define NV917C_SET_CSC_GRN2GRN                                                  (0x00000154)
+#define NV917C_SET_CSC_GRN2GRN_COEFF                                            18:0
+#define NV917C_SET_CSC_BLU2GRN                                                  (0x00000158)
+#define NV917C_SET_CSC_BLU2GRN_COEFF                                            18:0
+#define NV917C_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
+#define NV917C_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
+#define NV917C_SET_CSC_RED2BLU                                                  (0x00000160)
+#define NV917C_SET_CSC_RED2BLU_COEFF                                            18:0
+#define NV917C_SET_CSC_GRN2BLU                                                  (0x00000164)
+#define NV917C_SET_CSC_GRN2BLU_COEFF                                            18:0
+#define NV917C_SET_CSC_BLU2BLU                                                  (0x00000168)
+#define NV917C_SET_CSC_BLU2BLU_COEFF                                            18:0
+#define NV917C_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
+#define NV917C_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
+#define NV917C_SET_SPARE                                                        (0x000003BC)
+#define NV917C_SET_SPARE_UNUSED                                                 31:0
+#define NV917C_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV917C_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV917C_SURFACE_SET_OFFSET(a,b)                                          (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
+#define NV917C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV917C_SURFACE_SET_SIZE(a)                                              (0x00000408 + (a)*0x00000020)
+#define NV917C_SURFACE_SET_SIZE_WIDTH                                           15:0
+#define NV917C_SURFACE_SET_SIZE_HEIGHT                                          31:16
+#define NV917C_SURFACE_SET_STORAGE(a)                                           (0x0000040C + (a)*0x00000020)
+#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV917C_SURFACE_SET_STORAGE_PITCH                                        20:8
+#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
+#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV917C_SURFACE_SET_PARAMS(a)                                            (0x00000410 + (a)*0x00000020)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
+#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10                            (0x000000DF)
+#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
+#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
+#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
+#define NV917C_SURFACE_SET_PARAMS_GAMMA                                         2:2
+#define NV917C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
+#define NV917C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
+#define NV917C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
+#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
+#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
+#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl917c_h
diff --git a/classes/display/cl917d.h b/classes/display/cl917d.h
new file mode 100644
index 0000000..cf08d92
--- /dev/null
+++ b/classes/display/cl917d.h
@@ -0,0 +1,1176 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl917d_h_
+#define _cl917d_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV917D_CORE_CHANNEL_DMA                                                 (0x0000917D)
+
+#define NV917D_CORE_NOTIFIER_3                                                      0x00000000
+#define NV917D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
+#define NV917D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
+#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
+#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
+#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
+#define NV917D_CORE_NOTIFIER_3__1                                                   0x00000001
+#define NV917D_CORE_NOTIFIER_3__1_R1                                                31:0
+#define NV917D_CORE_NOTIFIER_3__2                                                   0x00000002
+#define NV917D_CORE_NOTIFIER_3__2_R2                                                31:0
+#define NV917D_CORE_NOTIFIER_3__3                                                   0x00000003
+#define NV917D_CORE_NOTIFIER_3__3_R3                                                31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:27
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
+#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
+
+
+// dma opcode instructions
+#define NV917D_DMA                                                         0x00000000 
+#define NV917D_DMA_OPCODE                                                       31:29 
+#define NV917D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV917D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV917D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV917D_DMA_OPCODE                                                       31:29 
+#define NV917D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV917D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV917D_DMA_METHOD_COUNT                                                 27:18 
+#define NV917D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV917D_DMA_DATA                                                          31:0 
+#define NV917D_DMA_DATA_NOP                                                0x00000000 
+#define NV917D_DMA_OPCODE                                                       31:29 
+#define NV917D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV917D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV917D_DMA_OPCODE                                                       31:29 
+#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV917D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV917D_PUT                                                              (0x00000000)
+#define NV917D_PUT_PTR                                                          11:2
+#define NV917D_GET                                                              (0x00000004)
+#define NV917D_GET_PTR                                                          11:2
+#define NV917D_UPDATE                                                           (0x00000080)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
+#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
+#define NV917D_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV917D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV917D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV917D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV917D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV917D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV917D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV917D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV917D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV917D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV917D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV917D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV917D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV917D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV917D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV917D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV917D_SET_SPARE                                                        (0x0000016C)
+#define NV917D_SET_SPARE_UNUSED                                                 31:0
+#define NV917D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
+#define NV917D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV917D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
+#define NV917D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV917D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV917D_DAC_SET_CONTROL_PROTOCOL                                         12:8
+#define NV917D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV917D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
+#define NV917D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
+#define NV917D_DAC_SET_SW_SPARE_A_CODE                                          31:0
+#define NV917D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
+#define NV917D_DAC_SET_SW_SPARE_B_CODE                                          31:0
+#define NV917D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
+#define NV917D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV917D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
+#define NV917D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV917D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV917D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
+#define NV917D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NV917D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
+#define NV917D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+#define NV917D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
+#define NV917D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV917D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
+#define NV917D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
+#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
+#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
+#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
+#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
+#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
+#define NV917D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV917D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
+#define NV917D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
+#define NV917D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
+#define NV917D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
+#define NV917D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
+#define NV917D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
+
+#define NV917D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
+#define NV917D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV917D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
+#define NV917D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
+#define NV917D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV917D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
+#define NV917D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV917D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV917D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV917D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
+#define NV917D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV917D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV917D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
+#define NV917D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV917D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV917D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
+#define NV917D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV917D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV917D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
+#define NV917D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV917D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV917D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
+#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
+#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV917D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
+#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
+#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
+#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
+#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
+#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
+#define NV917D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
+#define NV917D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
+#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
+#define NV917D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
+#define NV917D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NV917D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV917D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
+#define NV917D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV917D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
+#define NV917D_HEAD_SET_SIZE_WIDTH                                              15:0
+#define NV917D_HEAD_SET_SIZE_HEIGHT                                             31:16
+#define NV917D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
+#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV917D_HEAD_SET_STORAGE_PITCH                                           20:8
+#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
+#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV917D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
+#define NV917D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV917D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
+#define NV917D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
+#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV917D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV917D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV917D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV917D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
+#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
+#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
+#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV917D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
+#define NV917D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
+#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
+#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
+#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
+#define NV917D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
+#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV917D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV917D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV917D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
+#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV917D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
+#define NV917D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV917D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
+#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
+#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
+#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
+#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
+#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
+#define NV917D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
+#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV917D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
+#define NV917D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
+#define NV917D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
+#define NV917D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
+#define NV917D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
+#define NV917D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
+#define NV917D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
+#define NV917D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
+#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
+#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
+#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
+#define NV917D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
+#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
+#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
+#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
+#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
+#define NV917D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
+#define NV917D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NV917D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NV917D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NV917D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NV917D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NV917D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
+#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
+#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
+#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
+#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
+#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
+#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
+#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
+#define NV917D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
+#define NV917D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV917D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
+#define NV917D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl917d_h
diff --git a/classes/display/cl917e.h b/classes/display/cl917e.h
new file mode 100644
index 0000000..ad6423c
--- /dev/null
+++ b/classes/display/cl917e.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl917e_h_
+#define _cl917e_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV917E_OVERLAY_CHANNEL_DMA                                              (0x0000917E)
+
+#define NV_DISP_NOTIFICATION_2                                                       0x00000000
+#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
+#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
+#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
+#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
+#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
+#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
+#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
+#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
+#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
+
+
+#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
+#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
+#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
+#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
+
+
+#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
+#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
+
+
+// dma opcode instructions
+#define NV917E_DMA                                                         0x00000000 
+#define NV917E_DMA_OPCODE                                                       31:29 
+#define NV917E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV917E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV917E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV917E_DMA_OPCODE                                                       31:29 
+#define NV917E_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV917E_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV917E_DMA_METHOD_COUNT                                                 27:18 
+#define NV917E_DMA_METHOD_OFFSET                                                 11:2 
+#define NV917E_DMA_DATA                                                          31:0 
+#define NV917E_DMA_DATA_NOP                                                0x00000000 
+#define NV917E_DMA_OPCODE                                                       31:29 
+#define NV917E_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV917E_DMA_JUMP_OFFSET                                                   11:2 
+#define NV917E_DMA_OPCODE                                                       31:29 
+#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV917E_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV917E_PUT                                                              (0x00000000)
+#define NV917E_PUT_PTR                                                          11:2
+#define NV917E_GET                                                              (0x00000004)
+#define NV917E_GET_PTR                                                          11:2
+#define NV917E_UPDATE                                                           (0x00000080)
+#define NV917E_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV917E_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV917E_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV917E_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV917E_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV917E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV917E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV917E_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV917E_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE                                   1:0
+#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP                              (0x00000000)
+#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP                         (0x00000003)
+#define NV917E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV917E_SET_SEMAPHORE_ACQUIRE                                            (0x00000088)
+#define NV917E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV917E_SET_SEMAPHORE_RELEASE                                            (0x0000008C)
+#define NV917E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV917E_SET_SEMAPHORE_CONTROL                                            (0x00000090)
+#define NV917E_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
+#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
+#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
+#define NV917E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV917E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV917E_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV917E_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV917E_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV917E_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV917E_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV917E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV917E_SET_CONTEXT_DMA_LUT                                              (0x000000B0)
+#define NV917E_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV917E_SET_OVERLAY_LUT_LO                                               (0x000000B4)
+#define NV917E_SET_OVERLAY_LUT_LO_ENABLE                                        31:31
+#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE                                (0x00000000)
+#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE                                 (0x00000001)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE                                          27:24
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_LORES                                    (0x00000000)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_HIRES                                    (0x00000001)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                   (0x00000003)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE             (0x00000004)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE            (0x00000005)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE             (0x00000006)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE              (0x00000007)
+#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE             (0x00000008)
+#define NV917E_SET_OVERLAY_LUT_HI                                               (0x000000B8)
+#define NV917E_SET_OVERLAY_LUT_HI_ORIGIN                                        31:0
+#define NV917E_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
+#define NV917E_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
+#define NV917E_SET_POINT_IN                                                     (0x000000E0)
+#define NV917E_SET_POINT_IN_X                                                   14:0
+#define NV917E_SET_POINT_IN_Y                                                   30:16
+#define NV917E_SET_SIZE_IN                                                      (0x000000E4)
+#define NV917E_SET_SIZE_IN_WIDTH                                                14:0
+#define NV917E_SET_SIZE_IN_HEIGHT                                               30:16
+#define NV917E_SET_SIZE_OUT                                                     (0x000000E8)
+#define NV917E_SET_SIZE_OUT_WIDTH                                               14:0
+#define NV917E_SET_COMPOSITION_CONTROL                                          (0x00000100)
+#define NV917E_SET_COMPOSITION_CONTROL_MODE                                     3:0
+#define NV917E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING           (0x00000000)
+#define NV917E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING      (0x00000001)
+#define NV917E_SET_COMPOSITION_CONTROL_MODE_OPAQUE                              (0x00000002)
+#define NV917E_SET_KEY_COLOR_LO                                                 (0x00000104)
+#define NV917E_SET_KEY_COLOR_LO_COLOR                                           31:0
+#define NV917E_SET_KEY_COLOR_HI                                                 (0x00000108)
+#define NV917E_SET_KEY_COLOR_HI_COLOR                                           31:0
+#define NV917E_SET_KEY_MASK_LO                                                  (0x0000010C)
+#define NV917E_SET_KEY_MASK_LO_MASK                                             31:0
+#define NV917E_SET_KEY_MASK_HI                                                  (0x00000110)
+#define NV917E_SET_KEY_MASK_HI_MASK                                             31:0
+#define NV917E_SET_PROCESSING                                                   (0x00000118)
+#define NV917E_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV917E_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV917E_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV917E_SET_CONVERSION_RED                                               (0x0000011C)
+#define NV917E_SET_CONVERSION_RED_GAIN                                          15:0
+#define NV917E_SET_CONVERSION_RED_OFS                                           31:16
+#define NV917E_SET_CONVERSION_GRN                                               (0x00000120)
+#define NV917E_SET_CONVERSION_GRN_GAIN                                          15:0
+#define NV917E_SET_CONVERSION_GRN_OFS                                           31:16
+#define NV917E_SET_CONVERSION_BLU                                               (0x00000124)
+#define NV917E_SET_CONVERSION_BLU_GAIN                                          15:0
+#define NV917E_SET_CONVERSION_BLU_OFS                                           31:16
+#define NV917E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV917E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV917E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV917E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV917E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV917E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV917E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV917E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV917E_SET_CSC_RED2RED                                                  (0x00000140)
+#define NV917E_SET_CSC_RED2RED_COEFF                                            18:0
+#define NV917E_SET_CSC_GRN2RED                                                  (0x00000144)
+#define NV917E_SET_CSC_GRN2RED_COEFF                                            18:0
+#define NV917E_SET_CSC_BLU2RED                                                  (0x00000148)
+#define NV917E_SET_CSC_BLU2RED_COEFF                                            18:0
+#define NV917E_SET_CSC_CONSTANT2RED                                             (0x0000014C)
+#define NV917E_SET_CSC_CONSTANT2RED_COEFF                                       18:0
+#define NV917E_SET_CSC_RED2GRN                                                  (0x00000150)
+#define NV917E_SET_CSC_RED2GRN_COEFF                                            18:0
+#define NV917E_SET_CSC_GRN2GRN                                                  (0x00000154)
+#define NV917E_SET_CSC_GRN2GRN_COEFF                                            18:0
+#define NV917E_SET_CSC_BLU2GRN                                                  (0x00000158)
+#define NV917E_SET_CSC_BLU2GRN_COEFF                                            18:0
+#define NV917E_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
+#define NV917E_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
+#define NV917E_SET_CSC_RED2BLU                                                  (0x00000160)
+#define NV917E_SET_CSC_RED2BLU_COEFF                                            18:0
+#define NV917E_SET_CSC_GRN2BLU                                                  (0x00000164)
+#define NV917E_SET_CSC_GRN2BLU_COEFF                                            18:0
+#define NV917E_SET_CSC_BLU2BLU                                                  (0x00000168)
+#define NV917E_SET_CSC_BLU2BLU_COEFF                                            18:0
+#define NV917E_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
+#define NV917E_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
+#define NV917E_SET_SPARE                                                        (0x000003BC)
+#define NV917E_SET_SPARE_UNUSED                                                 31:0
+#define NV917E_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV917E_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV917E_SURFACE_SET_OFFSET(b)                                            (0x00000400 + (b)*0x00000004)
+#define NV917E_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV917E_SURFACE_SET_SIZE                                                 (0x00000408)
+#define NV917E_SURFACE_SET_SIZE_WIDTH                                           15:0
+#define NV917E_SURFACE_SET_SIZE_HEIGHT                                          31:16
+#define NV917E_SURFACE_SET_STORAGE                                              (0x0000040C)
+#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV917E_SURFACE_SET_STORAGE_PITCH                                        20:8
+#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
+#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV917E_SURFACE_SET_PARAMS                                               (0x00000410)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8                           (0x00000028)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8                           (0x00000029)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
+#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10                            (0x000000DF)
+#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE                                   1:0
+#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB                               (0x00000000)
+#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601                           (0x00000001)
+#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709                           (0x00000002)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl917e_h
diff --git a/classes/display/cl927c.h b/classes/display/cl927c.h
new file mode 100644
index 0000000..2cd1e47
--- /dev/null
+++ b/classes/display/cl927c.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl927c_h_
+#define _cl927c_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV927C_BASE_CHANNEL_DMA                                                 (0x0000927C)
+
+#define NV_DISP_BASE_NOTIFIER_1                                                      0x00000000
+#define NV_DISP_BASE_NOTIFIER_1_SIZEOF                                               0x00000004
+#define NV_DISP_BASE_NOTIFIER_1__0                                                   0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT                                15:0
+#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP                                         29:16
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS                                            31:30
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN                                  0x00000000
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN                                      0x00000001
+#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED                                   0x00000002
+
+
+#define NV_DISP_NOTIFICATION_2                                                       0x00000000
+#define NV_DISP_NOTIFICATION_2_SIZEOF                                                0x00000010
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0                                          0x00000000
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0                             31:0
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1                                          0x00000001
+#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1                             31:0
+#define NV_DISP_NOTIFICATION_2_INFO32_2                                              0x00000002
+#define NV_DISP_NOTIFICATION_2_INFO32_2_R0                                           31:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3                                              0x00000003
+#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT                                7:0
+#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD                                        8:8
+#define NV_DISP_NOTIFICATION_2_INFO16_3_R1                                           15:9
+#define NV_DISP_NOTIFICATION_2__3_STATUS                                             31:16
+#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN                                   0x00008000
+#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN                                       0x0000FFFF
+#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED                                    0x00000000
+
+
+#define NV_DISP_NOTIFICATION_INFO16                                                  0x00000000
+#define NV_DISP_NOTIFICATION_INFO16_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_INFO16__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT                                 7:0
+#define NV_DISP_NOTIFICATION_INFO16__0_FIELD                                         8:8
+#define NV_DISP_NOTIFICATION_INFO16__0_R1                                            15:9
+
+
+#define NV_DISP_NOTIFICATION_STATUS                                                  0x00000000
+#define NV_DISP_NOTIFICATION_STATUS_SIZEOF                                           0x00000002
+#define NV_DISP_NOTIFICATION_STATUS__0                                               0x00000000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS                                        15:0
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN                              0x00008000
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN                                  0x0000FFFF
+#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED                               0x00000000
+
+
+// dma opcode instructions
+#define NV927C_DMA                                                         0x00000000 
+#define NV927C_DMA_OPCODE                                                       31:29 
+#define NV927C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV927C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV927C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV927C_DMA_OPCODE                                                       31:29 
+#define NV927C_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV927C_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV927C_DMA_METHOD_COUNT                                                 27:18 
+#define NV927C_DMA_METHOD_OFFSET                                                 11:2 
+#define NV927C_DMA_DATA                                                          31:0 
+#define NV927C_DMA_DATA_NOP                                                0x00000000 
+#define NV927C_DMA_OPCODE                                                       31:29 
+#define NV927C_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV927C_DMA_JUMP_OFFSET                                                   11:2 
+#define NV927C_DMA_OPCODE                                                       31:29 
+#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV927C_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV927C_PUT                                                              (0x00000000)
+#define NV927C_PUT_PTR                                                          11:2
+#define NV927C_GET                                                              (0x00000004)
+#define NV927C_GET_PTR                                                          11:2
+#define NV927C_GET_SCANLINE                                                     (0x00000010)
+#define NV927C_GET_SCANLINE_LINE                                                15:0
+#define NV927C_UPDATE                                                           (0x00000080)
+#define NV927C_UPDATE_INTERLOCK_WITH_CORE                                       0:0
+#define NV927C_UPDATE_INTERLOCK_WITH_CORE_DISABLE                               (0x00000000)
+#define NV927C_UPDATE_INTERLOCK_WITH_CORE_ENABLE                                (0x00000001)
+#define NV927C_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV927C_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV927C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV927C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV927C_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV927C_SET_PRESENT_CONTROL                                              (0x00000084)
+#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE                                   9:8
+#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE                           (0x00000002)
+#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               2:2
+#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
+#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
+#define NV927C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         7:4
+#define NV927C_SET_PRESENT_CONTROL_BEGIN_LINE                                   30:16
+#define NV927C_SET_PRESENT_CONTROL_ON_LINE_MARGIN                               15:10
+#define NV927C_SET_SEMAPHORE_CONTROL                                            (0x00000088)
+#define NV927C_SET_SEMAPHORE_CONTROL_OFFSET                                     11:2
+#define NV927C_SET_SEMAPHORE_CONTROL_DELAY                                      26:26
+#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE                              (0x00000000)
+#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE                               (0x00000001)
+#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT                                     28:28
+#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY                              (0x00000000)
+#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD                           (0x00000001)
+#define NV927C_SET_SEMAPHORE_ACQUIRE                                            (0x0000008C)
+#define NV927C_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NV927C_SET_SEMAPHORE_RELEASE                                            (0x00000090)
+#define NV927C_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NV927C_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000094)
+#define NV927C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NV927C_SET_NOTIFIER_CONTROL                                             (0x000000A0)
+#define NV927C_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV927C_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV927C_SET_NOTIFIER_CONTROL_DELAY                                       26:26
+#define NV927C_SET_NOTIFIER_CONTROL_DELAY_DISABLE                               (0x00000000)
+#define NV927C_SET_NOTIFIER_CONTROL_DELAY_ENABLE                                (0x00000001)
+#define NV927C_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV927C_SET_CONTEXT_DMA_NOTIFIER                                         (0x000000A4)
+#define NV927C_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV927C_SET_CONTEXT_DMAS_ISO(b)                                          (0x000000C0 + (b)*0x00000004)
+#define NV927C_SET_CONTEXT_DMAS_ISO_HANDLE                                      31:0
+#define NV927C_SET_BASE_LUT_LO                                                  (0x000000E0)
+#define NV927C_SET_BASE_LUT_LO_ENABLE                                           31:30
+#define NV927C_SET_BASE_LUT_LO_ENABLE_DISABLE                                   (0x00000000)
+#define NV927C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT                              (0x00000001)
+#define NV927C_SET_BASE_LUT_LO_ENABLE_ENABLE                                    (0x00000002)
+#define NV927C_SET_BASE_LUT_LO_MODE                                             27:24
+#define NV927C_SET_BASE_LUT_LO_MODE_LORES                                       (0x00000000)
+#define NV927C_SET_BASE_LUT_LO_MODE_HIRES                                       (0x00000001)
+#define NV927C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                      (0x00000003)
+#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE                (0x00000004)
+#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE               (0x00000005)
+#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE                (0x00000006)
+#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE                 (0x00000007)
+#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE                (0x00000008)
+#define NV927C_SET_BASE_LUT_HI                                                  (0x000000E4)
+#define NV927C_SET_BASE_LUT_HI_ORIGIN                                           31:0
+#define NV927C_SET_OUTPUT_LUT_LO                                                (0x000000E8)
+#define NV927C_SET_OUTPUT_LUT_LO_ENABLE                                         31:30
+#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                                 (0x00000000)
+#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT                            (0x00000001)
+#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                                  (0x00000002)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE                                           27:24
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_LORES                                     (0x00000000)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_HIRES                                     (0x00000001)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                    (0x00000003)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE              (0x00000004)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE             (0x00000005)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE              (0x00000006)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE               (0x00000007)
+#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE              (0x00000008)
+#define NV927C_SET_OUTPUT_LUT_HI                                                (0x000000EC)
+#define NV927C_SET_OUTPUT_LUT_HI_ORIGIN                                         31:0
+#define NV927C_SET_CONTEXT_DMA_LUT                                              (0x000000FC)
+#define NV927C_SET_CONTEXT_DMA_LUT_HANDLE                                       31:0
+#define NV927C_SET_PROCESSING                                                   (0x00000110)
+#define NV927C_SET_PROCESSING_USE_GAIN_OFS                                      0:0
+#define NV927C_SET_PROCESSING_USE_GAIN_OFS_DISABLE                              (0x00000000)
+#define NV927C_SET_PROCESSING_USE_GAIN_OFS_ENABLE                               (0x00000001)
+#define NV927C_SET_CONVERSION_RED                                               (0x00000114)
+#define NV927C_SET_CONVERSION_RED_GAIN                                          15:0
+#define NV927C_SET_CONVERSION_RED_OFS                                           31:16
+#define NV927C_SET_CONVERSION_GRN                                               (0x00000118)
+#define NV927C_SET_CONVERSION_GRN_GAIN                                          15:0
+#define NV927C_SET_CONVERSION_GRN_OFS                                           31:16
+#define NV927C_SET_CONVERSION_BLU                                               (0x0000011C)
+#define NV927C_SET_CONVERSION_BLU_GAIN                                          15:0
+#define NV927C_SET_CONVERSION_BLU_OFS                                           31:16
+#define NV927C_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000130)
+#define NV927C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NV927C_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000134)
+#define NV927C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NV927C_SET_UPDATE_TIMESTAMP_LO                                          (0x00000138)
+#define NV927C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NV927C_SET_UPDATE_TIMESTAMP_HI                                          (0x0000013C)
+#define NV927C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NV927C_SET_CSC_RED2RED                                                  (0x00000140)
+#define NV927C_SET_CSC_RED2RED_OWNER                                            31:31
+#define NV927C_SET_CSC_RED2RED_OWNER_CORE                                       (0x00000000)
+#define NV927C_SET_CSC_RED2RED_OWNER_BASE                                       (0x00000001)
+#define NV927C_SET_CSC_RED2RED_COEFF                                            18:0
+#define NV927C_SET_CSC_GRN2RED                                                  (0x00000144)
+#define NV927C_SET_CSC_GRN2RED_COEFF                                            18:0
+#define NV927C_SET_CSC_BLU2RED                                                  (0x00000148)
+#define NV927C_SET_CSC_BLU2RED_COEFF                                            18:0
+#define NV927C_SET_CSC_CONSTANT2RED                                             (0x0000014C)
+#define NV927C_SET_CSC_CONSTANT2RED_COEFF                                       18:0
+#define NV927C_SET_CSC_RED2GRN                                                  (0x00000150)
+#define NV927C_SET_CSC_RED2GRN_COEFF                                            18:0
+#define NV927C_SET_CSC_GRN2GRN                                                  (0x00000154)
+#define NV927C_SET_CSC_GRN2GRN_COEFF                                            18:0
+#define NV927C_SET_CSC_BLU2GRN                                                  (0x00000158)
+#define NV927C_SET_CSC_BLU2GRN_COEFF                                            18:0
+#define NV927C_SET_CSC_CONSTANT2GRN                                             (0x0000015C)
+#define NV927C_SET_CSC_CONSTANT2GRN_COEFF                                       18:0
+#define NV927C_SET_CSC_RED2BLU                                                  (0x00000160)
+#define NV927C_SET_CSC_RED2BLU_COEFF                                            18:0
+#define NV927C_SET_CSC_GRN2BLU                                                  (0x00000164)
+#define NV927C_SET_CSC_GRN2BLU_COEFF                                            18:0
+#define NV927C_SET_CSC_BLU2BLU                                                  (0x00000168)
+#define NV927C_SET_CSC_BLU2BLU_COEFF                                            18:0
+#define NV927C_SET_CSC_CONSTANT2BLU                                             (0x0000016C)
+#define NV927C_SET_CSC_CONSTANT2BLU_COEFF                                       18:0
+#define NV927C_SET_SPARE                                                        (0x000003BC)
+#define NV927C_SET_SPARE_UNUSED                                                 31:0
+#define NV927C_SET_SPARE_NOOP(b)                                                (0x000003C0 + (b)*0x00000004)
+#define NV927C_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV927C_SURFACE_SET_OFFSET(a,b)                                          (0x00000400 + (a)*0x00000020 + (b)*0x00000004)
+#define NV927C_SURFACE_SET_OFFSET_ORIGIN                                        31:0
+#define NV927C_SURFACE_SET_SIZE(a)                                              (0x00000408 + (a)*0x00000020)
+#define NV927C_SURFACE_SET_SIZE_WIDTH                                           15:0
+#define NV927C_SURFACE_SET_SIZE_HEIGHT                                          31:16
+#define NV927C_SURFACE_SET_STORAGE(a)                                           (0x0000040C + (a)*0x00000020)
+#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT                                 3:0
+#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                         (0x00000000)
+#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                        (0x00000001)
+#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                       (0x00000002)
+#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                      (0x00000003)
+#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                    (0x00000004)
+#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                  (0x00000005)
+#define NV927C_SURFACE_SET_STORAGE_PITCH                                        20:8
+#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT                                24:24
+#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                    (0x00000000)
+#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH                          (0x00000001)
+#define NV927C_SURFACE_SET_PARAMS(a)                                            (0x00000410 + (a)*0x00000020)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT                                        15:8
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_I8                                     (0x0000001E)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID16                                 (0x0000001F)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID32                                 (0x0000002E)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                    (0x000000CA)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8                               (0x000000CF)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10                            (0x000000D1)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                  (0x00000022)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                   (0x00000024)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8                               (0x000000D5)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_R5G6B5                                 (0x000000E8)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5                               (0x000000E9)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16                        (0x000000C6)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                 (0x00000023)
+#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10                            (0x000000DF)
+#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE                                  1:0
+#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA                            (0x00000000)
+#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA                            (0x00000002)
+#define NV927C_SURFACE_SET_PARAMS_GAMMA                                         2:2
+#define NV927C_SURFACE_SET_PARAMS_GAMMA_LINEAR                                  (0x00000000)
+#define NV927C_SURFACE_SET_PARAMS_GAMMA_SRGB                                    (0x00000001)
+#define NV927C_SURFACE_SET_PARAMS_LAYOUT                                        5:4
+#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FRM                                    (0x00000000)
+#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD1                                   (0x00000001)
+#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD2                                   (0x00000002)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl927c_h
diff --git a/classes/display/cl927d.h b/classes/display/cl927d.h
new file mode 100644
index 0000000..4363a79
--- /dev/null
+++ b/classes/display/cl927d.h
@@ -0,0 +1,1181 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl927d_h_
+#define _cl927d_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV927D_CORE_CHANNEL_DMA                                                 (0x0000927D)
+
+#define NV927D_CORE_NOTIFIER_3                                                      0x00000000
+#define NV927D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
+#define NV927D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
+#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
+#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
+#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
+#define NV927D_CORE_NOTIFIER_3__1                                                   0x00000001
+#define NV927D_CORE_NOTIFIER_3__1_R1                                                31:0
+#define NV927D_CORE_NOTIFIER_3__2                                                   0x00000002
+#define NV927D_CORE_NOTIFIER_3__2_R2                                                31:0
+#define NV927D_CORE_NOTIFIER_3__3                                                   0x00000003
+#define NV927D_CORE_NOTIFIER_3__3_R3                                                31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:27
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
+#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
+
+
+// dma opcode instructions
+#define NV927D_DMA                                                         0x00000000 
+#define NV927D_DMA_OPCODE                                                       31:29 
+#define NV927D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV927D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV927D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV927D_DMA_OPCODE                                                       31:29 
+#define NV927D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV927D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV927D_DMA_METHOD_COUNT                                                 27:18 
+#define NV927D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV927D_DMA_DATA                                                          31:0 
+#define NV927D_DMA_DATA_NOP                                                0x00000000 
+#define NV927D_DMA_OPCODE                                                       31:29 
+#define NV927D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV927D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV927D_DMA_OPCODE                                                       31:29 
+#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV927D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV927D_PUT                                                              (0x00000000)
+#define NV927D_PUT_PTR                                                          11:2
+#define NV927D_GET                                                              (0x00000004)
+#define NV927D_GET_PTR                                                          11:2
+#define NV927D_UPDATE                                                           (0x00000080)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
+#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
+#define NV927D_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV927D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV927D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV927D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV927D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV927D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV927D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV927D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV927D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV927D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV927D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV927D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV927D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV927D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV927D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV927D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV927D_SET_SPARE                                                        (0x0000016C)
+#define NV927D_SET_SPARE_UNUSED                                                 31:0
+#define NV927D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
+#define NV927D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV927D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
+#define NV927D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV927D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV927D_DAC_SET_CONTROL_PROTOCOL                                         12:8
+#define NV927D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV927D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
+#define NV927D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
+#define NV927D_DAC_SET_SW_SPARE_A_CODE                                          31:0
+#define NV927D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
+#define NV927D_DAC_SET_SW_SPARE_B_CODE                                          31:0
+#define NV927D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
+#define NV927D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV927D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
+#define NV927D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV927D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV927D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV927D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV927D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV927D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV927D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
+#define NV927D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NV927D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
+#define NV927D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+#define NV927D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
+#define NV927D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV927D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
+#define NV927D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
+#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
+#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
+#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
+#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
+#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
+#define NV927D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV927D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
+#define NV927D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
+#define NV927D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
+#define NV927D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
+#define NV927D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
+#define NV927D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
+
+#define NV927D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
+#define NV927D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV927D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                20:13
+#define NV927D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
+#define NV927D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV927D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
+#define NV927D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV927D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV927D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV927D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
+#define NV927D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV927D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV927D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
+#define NV927D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV927D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV927D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
+#define NV927D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV927D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV927D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
+#define NV927D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV927D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV927D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
+#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
+#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV927D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
+#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
+#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
+#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
+#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
+#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
+#define NV927D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
+#define NV927D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
+#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
+#define NV927D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
+#define NV927D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NV927D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV927D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
+#define NV927D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV927D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
+#define NV927D_HEAD_SET_SIZE_WIDTH                                              15:0
+#define NV927D_HEAD_SET_SIZE_HEIGHT                                             31:16
+#define NV927D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
+#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV927D_HEAD_SET_STORAGE_PITCH                                           20:8
+#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
+#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV927D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
+#define NV927D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV927D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
+#define NV927D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
+#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV927D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV927D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV927D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV927D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
+#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
+#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
+#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV927D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
+#define NV927D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
+#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
+#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
+#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
+#define NV927D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
+#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV927D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV927D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV927D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
+#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV927D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
+#define NV927D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NV927D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV927D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
+#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
+#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
+#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
+#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
+#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
+#define NV927D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
+#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV927D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
+#define NV927D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
+#define NV927D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
+#define NV927D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
+#define NV927D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
+#define NV927D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
+#define NV927D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
+#define NV927D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
+#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
+#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
+#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
+#define NV927D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
+#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
+#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
+#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
+#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
+#define NV927D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
+#define NV927D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NV927D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NV927D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NV927D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NV927D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NV927D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
+#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
+#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
+#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
+#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
+#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
+#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
+#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
+#define NV927D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
+#define NV927D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV927D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
+#define NV927D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl927d_h
diff --git a/classes/display/cl947d.h b/classes/display/cl947d.h
new file mode 100644
index 0000000..66ae39b
--- /dev/null
+++ b/classes/display/cl947d.h
@@ -0,0 +1,1189 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl947d_h_
+#define _cl947d_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV947D_CORE_CHANNEL_DMA                                                 (0x0000947D)
+
+#define NV947D_CORE_NOTIFIER_3                                                      0x00000000
+#define NV947D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
+#define NV947D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
+#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
+#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
+#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
+#define NV947D_CORE_NOTIFIER_3__1                                                   0x00000001
+#define NV947D_CORE_NOTIFIER_3__1_R1                                                31:0
+#define NV947D_CORE_NOTIFIER_3__2                                                   0x00000002
+#define NV947D_CORE_NOTIFIER_3__2_R2                                                31:0
+#define NV947D_CORE_NOTIFIER_3__3                                                   0x00000003
+#define NV947D_CORE_NOTIFIER_3__3_R3                                                31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          12:12
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          15:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX           23:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8                          31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_REORDER_BANK_WIDTH_SIZE_MAX 13:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_REORDER_BANK_WIDTH_SIZE_MAX 13:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_REORDER_BANK_WIDTH_SIZE_MAX 13:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_REORDER_BANK_WIDTH_SIZE_MAX 13:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
+#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
+
+
+// dma opcode instructions
+#define NV947D_DMA                                                         0x00000000 
+#define NV947D_DMA_OPCODE                                                       31:29 
+#define NV947D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV947D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV947D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV947D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV947D_DMA_METHOD_COUNT                                                 27:18 
+#define NV947D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV947D_DMA_DATA                                                          31:0 
+#define NV947D_DMA_DATA_NOP                                                0x00000000 
+#define NV947D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV947D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV947D_PUT                                                              (0x00000000)
+#define NV947D_PUT_PTR                                                          11:2
+#define NV947D_GET                                                              (0x00000004)
+#define NV947D_GET_PTR                                                          11:2
+#define NV947D_UPDATE                                                           (0x00000080)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
+#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
+#define NV947D_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV947D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV947D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV947D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV947D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV947D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV947D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV947D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV947D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV947D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV947D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV947D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV947D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV947D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV947D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV947D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV947D_SET_SPARE                                                        (0x0000016C)
+#define NV947D_SET_SPARE_UNUSED                                                 31:0
+#define NV947D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
+#define NV947D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV947D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
+#define NV947D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV947D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV947D_DAC_SET_CONTROL_PROTOCOL                                         12:8
+#define NV947D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV947D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
+#define NV947D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
+#define NV947D_DAC_SET_SW_SPARE_A_CODE                                          31:0
+#define NV947D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
+#define NV947D_DAC_SET_SW_SPARE_B_CODE                                          31:0
+#define NV947D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
+#define NV947D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV947D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
+#define NV947D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV947D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV947D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV947D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV947D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV947D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV947D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
+#define NV947D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NV947D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
+#define NV947D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+#define NV947D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
+#define NV947D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV947D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
+#define NV947D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
+#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
+#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
+#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
+#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
+#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
+#define NV947D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV947D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
+#define NV947D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
+#define NV947D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
+#define NV947D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
+#define NV947D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
+#define NV947D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
+
+#define NV947D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
+#define NV947D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV947D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                20:13
+#define NV947D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
+#define NV947D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV947D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
+#define NV947D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV947D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV947D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV947D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
+#define NV947D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV947D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV947D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
+#define NV947D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV947D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV947D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
+#define NV947D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV947D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV947D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
+#define NV947D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV947D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV947D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
+#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
+#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV947D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
+#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
+#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
+#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
+#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
+#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
+#define NV947D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
+#define NV947D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
+#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
+#define NV947D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
+#define NV947D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NV947D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV947D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
+#define NV947D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV947D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
+#define NV947D_HEAD_SET_SIZE_WIDTH                                              15:0
+#define NV947D_HEAD_SET_SIZE_HEIGHT                                             31:16
+#define NV947D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
+#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV947D_HEAD_SET_STORAGE_PITCH                                           20:8
+#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
+#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV947D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
+#define NV947D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV947D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
+#define NV947D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
+#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV947D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV947D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV947D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV947D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
+#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
+#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
+#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV947D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
+#define NV947D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
+#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
+#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
+#define NV947D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
+#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV947D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV947D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV947D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
+#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV947D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
+#define NV947D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NV947D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV947D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
+#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
+#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
+#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
+#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
+#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
+#define NV947D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
+#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV947D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
+#define NV947D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
+#define NV947D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
+#define NV947D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
+#define NV947D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
+#define NV947D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
+#define NV947D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
+#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
+#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
+#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
+#define NV947D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
+#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
+#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
+#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
+#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
+#define NV947D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
+#define NV947D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NV947D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NV947D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NV947D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NV947D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NV947D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
+#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
+#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
+#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
+#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
+#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
+#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
+#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
+#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
+#define NV947D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
+#define NV947D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV947D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
+#define NV947D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl947d_h
diff --git a/classes/display/cl957d.h b/classes/display/cl957d.h
new file mode 100644
index 0000000..cc6452f
--- /dev/null
+++ b/classes/display/cl957d.h
@@ -0,0 +1,1185 @@
+/*
+ * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl957d_h_
+#define _cl957d_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV957D_CORE_CHANNEL_DMA                                                 (0x0000957D)
+
+#define NV957D_CORE_NOTIFIER_3                                                      0x00000000
+#define NV957D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
+#define NV957D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
+#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
+#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
+#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
+#define NV957D_CORE_NOTIFIER_3__1                                                   0x00000001
+#define NV957D_CORE_NOTIFIER_3__1_R1                                                31:0
+#define NV957D_CORE_NOTIFIER_3__2                                                   0x00000002
+#define NV957D_CORE_NOTIFIER_3__2_R2                                                31:0
+#define NV957D_CORE_NOTIFIER_3__3                                                   0x00000003
+#define NV957D_CORE_NOTIFIER_3__3_R3                                                31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          13:12
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          16:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX                23:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX                31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44                             0x0000002C
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45                             0x0000002D
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46                             0x0000002E
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47                             0x0000002F
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48                             0x00000030
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49                             0x00000031
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50                             0x00000032
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51                             0x00000033
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1                          31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
+#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
+
+
+// dma opcode instructions
+#define NV957D_DMA                                                         0x00000000 
+#define NV957D_DMA_OPCODE                                                       31:29 
+#define NV957D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV957D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV957D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV957D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV957D_DMA_METHOD_COUNT                                                 27:18 
+#define NV957D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV957D_DMA_DATA                                                          31:0 
+#define NV957D_DMA_DATA_NOP                                                0x00000000 
+#define NV957D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV957D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV957D_PUT                                                              (0x00000000)
+#define NV957D_PUT_PTR                                                          11:2
+#define NV957D_GET                                                              (0x00000004)
+#define NV957D_GET_PTR                                                          11:2
+#define NV957D_UPDATE                                                           (0x00000080)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
+#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
+#define NV957D_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV957D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV957D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV957D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV957D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV957D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV957D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV957D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV957D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV957D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV957D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV957D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV957D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV957D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV957D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV957D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV957D_SET_SPARE                                                        (0x0000016C)
+#define NV957D_SET_SPARE_UNUSED                                                 31:0
+#define NV957D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
+#define NV957D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV957D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
+#define NV957D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV957D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV957D_DAC_SET_CONTROL_PROTOCOL                                         12:8
+#define NV957D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV957D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
+#define NV957D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
+#define NV957D_DAC_SET_SW_SPARE_A_CODE                                          31:0
+#define NV957D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
+#define NV957D_DAC_SET_SW_SPARE_B_CODE                                          31:0
+#define NV957D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
+#define NV957D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV957D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
+#define NV957D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV957D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV957D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV957D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV957D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV957D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV957D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
+#define NV957D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NV957D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
+#define NV957D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+#define NV957D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
+#define NV957D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV957D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
+#define NV957D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
+#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
+#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
+#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
+#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
+#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
+#define NV957D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV957D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
+#define NV957D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
+#define NV957D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
+#define NV957D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
+#define NV957D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
+#define NV957D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
+
+#define NV957D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
+#define NV957D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV957D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                20:13
+#define NV957D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
+#define NV957D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV957D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
+#define NV957D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV957D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV957D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV957D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
+#define NV957D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV957D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV957D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
+#define NV957D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV957D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV957D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
+#define NV957D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV957D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV957D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
+#define NV957D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV957D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV957D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
+#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
+#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV957D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
+#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
+#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
+#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
+#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
+#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
+#define NV957D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
+#define NV957D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
+#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
+#define NV957D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
+#define NV957D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NV957D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV957D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
+#define NV957D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV957D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
+#define NV957D_HEAD_SET_SIZE_WIDTH                                              15:0
+#define NV957D_HEAD_SET_SIZE_HEIGHT                                             31:16
+#define NV957D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
+#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV957D_HEAD_SET_STORAGE_PITCH                                           20:8
+#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
+#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV957D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
+#define NV957D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV957D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
+#define NV957D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
+#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV957D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV957D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV957D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV957D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
+#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
+#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
+#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV957D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
+#define NV957D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
+#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
+#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
+#define NV957D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
+#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV957D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV957D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV957D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
+#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV957D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
+#define NV957D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NV957D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV957D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
+#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
+#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
+#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
+#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
+#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
+#define NV957D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
+#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV957D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
+#define NV957D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
+#define NV957D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
+#define NV957D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
+#define NV957D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
+#define NV957D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
+#define NV957D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
+#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
+#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
+#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
+#define NV957D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
+#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
+#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
+#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
+#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
+#define NV957D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
+#define NV957D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NV957D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NV957D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NV957D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NV957D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NV957D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
+#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
+#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
+#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
+#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
+#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
+#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
+#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
+#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
+#define NV957D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
+#define NV957D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV957D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
+#define NV957D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl957d_h
diff --git a/classes/display/cl977d.h b/classes/display/cl977d.h
new file mode 100644
index 0000000..b609c8d
--- /dev/null
+++ b/classes/display/cl977d.h
@@ -0,0 +1,1170 @@
+/*
+ * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl977d_h_
+#define _cl977d_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV977D_CORE_CHANNEL_DMA                                                 (0x0000977D)
+
+#define NV977D_CORE_NOTIFIER_3                                                      0x00000000
+#define NV977D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
+#define NV977D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
+#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
+#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
+#define NV977D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
+#define NV977D_CORE_NOTIFIER_3__1                                                   0x00000001
+#define NV977D_CORE_NOTIFIER_3__1_R1                                                31:0
+#define NV977D_CORE_NOTIFIER_3__2                                                   0x00000002
+#define NV977D_CORE_NOTIFIER_3__2_R2                                                31:0
+#define NV977D_CORE_NOTIFIER_3__3                                                   0x00000003
+#define NV977D_CORE_NOTIFIER_3__3_R3                                                31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          13:12
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          16:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX                23:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX                31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:7
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:7
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:7
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:7
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
+#define NV977D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
+
+
+// dma opcode instructions
+#define NV977D_DMA                                                         0x00000000 
+#define NV977D_DMA_OPCODE                                                       31:29 
+#define NV977D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV977D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV977D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV977D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV977D_DMA_METHOD_COUNT                                                 27:18 
+#define NV977D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV977D_DMA_DATA                                                          31:0 
+#define NV977D_DMA_DATA_NOP                                                0x00000000 
+#define NV977D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV977D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV977D_PUT                                                              (0x00000000)
+#define NV977D_PUT_PTR                                                          11:2
+#define NV977D_GET                                                              (0x00000004)
+#define NV977D_GET_PTR                                                          11:2
+#define NV977D_UPDATE                                                           (0x00000080)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
+#define NV977D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
+#define NV977D_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV977D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV977D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV977D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV977D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV977D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV977D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV977D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV977D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV977D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV977D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV977D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV977D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV977D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV977D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV977D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV977D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV977D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV977D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV977D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV977D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV977D_SET_SPARE                                                        (0x0000016C)
+#define NV977D_SET_SPARE_UNUSED                                                 31:0
+#define NV977D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
+#define NV977D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV977D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
+#define NV977D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV977D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV977D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV977D_DAC_SET_CONTROL_PROTOCOL                                         12:8
+#define NV977D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV977D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
+#define NV977D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
+#define NV977D_DAC_SET_SW_SPARE_A_CODE                                          31:0
+#define NV977D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
+#define NV977D_DAC_SET_SW_SPARE_B_CODE                                          31:0
+#define NV977D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
+#define NV977D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV977D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
+#define NV977D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV977D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV977D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV977D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV977D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV977D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV977D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV977D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV977D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV977D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV977D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV977D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
+#define NV977D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NV977D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
+#define NV977D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+#define NV977D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
+#define NV977D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV977D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
+#define NV977D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
+#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
+#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
+#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
+#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
+#define NV977D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
+#define NV977D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV977D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV977D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV977D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
+#define NV977D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
+#define NV977D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
+#define NV977D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
+#define NV977D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
+#define NV977D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
+
+#define NV977D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
+#define NV977D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV977D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV977D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                24:13
+#define NV977D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
+#define NV977D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV977D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
+#define NV977D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV977D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV977D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV977D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
+#define NV977D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV977D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV977D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
+#define NV977D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV977D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV977D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
+#define NV977D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV977D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV977D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
+#define NV977D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV977D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV977D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
+#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV977D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
+#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV977D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV977D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
+#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV977D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
+#define NV977D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
+#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
+#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
+#define NV977D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
+#define NV977D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
+#define NV977D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
+#define NV977D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
+#define NV977D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
+#define NV977D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NV977D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NV977D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV977D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
+#define NV977D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV977D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
+#define NV977D_HEAD_SET_SIZE_WIDTH                                              15:0
+#define NV977D_HEAD_SET_SIZE_HEIGHT                                             31:16
+#define NV977D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
+#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV977D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV977D_HEAD_SET_STORAGE_PITCH                                           20:8
+#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
+#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV977D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV977D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
+#define NV977D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV977D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
+#define NV977D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
+#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV977D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV977D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV977D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV977D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV977D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
+#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
+#define NV977D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
+#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV977D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
+#define NV977D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
+#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
+#define NV977D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
+#define NV977D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
+#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV977D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020                            (0x00000003)
+#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV977D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV977D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV977D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV977D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV977D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV977D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
+#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV977D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV977D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV977D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
+#define NV977D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV977D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NV977D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV977D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
+#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV977D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
+#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV977D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
+#define NV977D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
+#define NV977D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
+#define NV977D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
+#define NV977D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
+#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV977D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV977D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
+#define NV977D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
+#define NV977D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
+#define NV977D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
+#define NV977D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
+#define NV977D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
+#define NV977D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
+#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
+#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
+#define NV977D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
+#define NV977D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
+#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
+#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
+#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
+#define NV977D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
+#define NV977D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
+#define NV977D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NV977D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NV977D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NV977D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NV977D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NV977D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
+#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
+#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
+#define NV977D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
+#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
+#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
+#define NV977D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
+#define NV977D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
+#define NV977D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
+#define NV977D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
+#define NV977D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV977D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
+#define NV977D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl977d_h
diff --git a/classes/display/cl987d.h b/classes/display/cl987d.h
new file mode 100644
index 0000000..cbf4a7b
--- /dev/null
+++ b/classes/display/cl987d.h
@@ -0,0 +1,1173 @@
+/*
+ * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _cl987d_h_
+#define _cl987d_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NV987D_CORE_CHANNEL_DMA                                                 (0x0000987D)
+
+#define NV987D_CORE_NOTIFIER_3                                                      0x00000000
+#define NV987D_CORE_NOTIFIER_3_SIZEOF                                               0x00000150
+#define NV987D_CORE_NOTIFIER_3_COMPLETION_0                                         0x00000000
+#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE                                    0:0
+#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE                              0x00000000
+#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE                               0x00000001
+#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_R0                                      15:1
+#define NV987D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP                               29:16
+#define NV987D_CORE_NOTIFIER_3__1                                                   0x00000001
+#define NV987D_CORE_NOTIFIER_3__1_R1                                                31:0
+#define NV987D_CORE_NOTIFIER_3__2                                                   0x00000002
+#define NV987D_CORE_NOTIFIER_3__2_R2                                                31:0
+#define NV987D_CORE_NOTIFIER_3__3                                                   0x00000003
+#define NV987D_CORE_NOTIFIER_3__3_R3                                                31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4                                       0x00000004
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE                                  0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE                            0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE                             0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO                         1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE                   0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE                    0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO                        2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R0                                    19:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA                        20:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_4_R1                                    29:21
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_5                                       0x00000005
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_6                                       0x00000006
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7                                       0x00000007
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX                           7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_7_R4                                    31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8                                       0x00000008
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_8_R5                                    31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9                                       0x00000009
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_9_R6                                    31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10                                      0x0000000A
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_10_R7                                   31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11                                      0x0000000B
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_11_R8                                   31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12                             0x0000000C
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE                  0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE            0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE             0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE                   1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE                3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0                          31:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13                             0x0000000D
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX                 7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1                          31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14                             0x0000000E
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE                  0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE            0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE             0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE                   1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE                3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0                          31:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15                             0x0000000F
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX                 7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1                          31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16                             0x00000010
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE                  0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE            0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE             0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE                   1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE                3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0                          31:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17                             0x00000011
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX                 7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1                          31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18                             0x00000012
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE                  0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE            0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE             0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE                   1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE                3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0                          31:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19                             0x00000013
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX                 7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1                          31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20                             0x00000014
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21                             0x00000015
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22                             0x00000016
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23                             0x00000017
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24                             0x00000018
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25                             0x00000019
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26                             0x0000001A
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27                             0x0000001B
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28                             0x0000001C
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29                             0x0000001D
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30                             0x0000001E
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31                             0x0000001F
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32                             0x00000020
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33                             0x00000021
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34                             0x00000022
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24               1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18                 2:2
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24                 3:3
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0                          7:4
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A               8:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B               9:9
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1                          10:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS                   11:11
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE             0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE              0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2                          13:12
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3                          16:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4                          19:17
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5                          23:20
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A                        24:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B                        25:25
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE                  0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE                   0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE                26:26
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE          0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE           0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6                          31:28
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35                             0x00000023
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX                  7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7                          15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX                23:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX                31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36                            0x00000024
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC                 1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0                         31:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37                            0x00000025
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX            7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1                         15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2                         31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38                            0x00000026
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC                 1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0                         31:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39                            0x00000027
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX            7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1                         15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2                         31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40                            0x00000028
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC                 1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0                         31:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41                            0x00000029
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX            7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1                         15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2                         31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42                            0x0000002A
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC               0:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE         0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE          0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC                 1:1
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE           0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE            0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED      6:6
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0                         31:10
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43                            0x0000002B
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX            7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1                         15:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2                         31:24
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52                            0x00000034
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0                         31:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53                            0x00000035
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54                            0x00000036
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55                            0x00000037
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56                            0x00000038
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX                   7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7                         31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57                            0x00000039
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58                            0x0000003A
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59                            0x0000003B
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10                        31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60                            0x0000003C
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0                         31:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61                            0x0000003D
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62                            0x0000003E
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63                            0x0000003F
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64                            0x00000040
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX                   7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7                         31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65                            0x00000041
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66                            0x00000042
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67                            0x00000043
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10                        31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68                            0x00000044
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0                         31:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69                            0x00000045
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70                            0x00000046
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71                            0x00000047
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72                            0x00000048
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX                   7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7                         31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73                            0x00000049
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74                            0x0000004A
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75                            0x0000004B
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10                        31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76                            0x0000004C
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0                         31:14
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77                            0x0000004D
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78                            0x0000004E
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79                            0x0000004F
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444          14:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5                         15:15
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422          30:16
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6                         31:31
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80                            0x00000050
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX                   7:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7                         31:8
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81                            0x00000051
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82                            0x00000052
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9                         31:0
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83                            0x00000053
+#define NV987D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10                        31:0
+
+
+// dma opcode instructions
+#define NV987D_DMA                                                         0x00000000 
+#define NV987D_DMA_OPCODE                                                       31:29 
+#define NV987D_DMA_OPCODE_METHOD                                           0x00000000 
+#define NV987D_DMA_OPCODE_JUMP                                             0x00000001 
+#define NV987D_DMA_OPCODE_NONINC_METHOD                                    0x00000002 
+#define NV987D_DMA_OPCODE_SET_SUBDEVICE_MASK                               0x00000003 
+#define NV987D_DMA_METHOD_COUNT                                                 27:18 
+#define NV987D_DMA_METHOD_OFFSET                                                 11:2 
+#define NV987D_DMA_DATA                                                          31:0 
+#define NV987D_DMA_DATA_NOP                                                0x00000000 
+#define NV987D_DMA_JUMP_OFFSET                                                   11:2 
+#define NV987D_DMA_SET_SUBDEVICE_MASK_VALUE                                      11:0 
+
+// class methods
+#define NV987D_PUT                                                              (0x00000000)
+#define NV987D_PUT_PTR                                                          11:2
+#define NV987D_GET                                                              (0x00000004)
+#define NV987D_GET_PTR                                                          11:2
+#define NV987D_UPDATE                                                           (0x00000080)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR(i)                                  (0 +(i)*4):(0 +(i)*4)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1                             4
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE                             (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE                              (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0                                    0:0
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE                            (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE                             (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1                                    4:4
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE                            (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE                             (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2                                    8:8
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE                            (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE                             (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3                                    12:12
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE                            (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE                             (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE(i)                                    (1 +(i)*4):(1 +(i)*4)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1                               4
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE_DISABLE                               (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE_ENABLE                                (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE0                                      1:1
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE                              (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE                               (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE1                                      5:5
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE                              (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE                               (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE2                                      9:9
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE                              (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE                               (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE3                                      13:13
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE                              (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE                               (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY(i)                                 (2 +(i)*4):(2 +(i)*4)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1                            4
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE                            (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE                             (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0                                   2:2
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE                           (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE                            (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1                                   6:6
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE                           (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE                            (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2                                   10:10
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE                           (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE                            (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3                                   14:14
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE                           (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE                            (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i)                             (3 +(i)*4):(3 +(i)*4)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1                        4
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE                        (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE                         (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0                               3:3
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE                       (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE                        (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1                               7:7
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE                       (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE                        (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2                               11:11
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE                       (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE                        (0x00000001)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3                               15:15
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE                       (0x00000000)
+#define NV987D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE                        (0x00000001)
+#define NV987D_UPDATE_SPECIAL_HANDLING                                          25:24
+#define NV987D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NV987D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NV987D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NV987D_UPDATE_SPECIAL_HANDLING_REASON                                   23:16
+#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY                                       31:31
+#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE                                 (0x00000000)
+#define NV987D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE                                  (0x00000001)
+#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY                                     30:30
+#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE                               (0x00000000)
+#define NV987D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE                                (0x00000001)
+#define NV987D_UPDATE_INHIBIT_INTERRUPTS                                        29:29
+#define NV987D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NV987D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NV987D_SET_NOTIFIER_CONTROL                                             (0x00000084)
+#define NV987D_SET_NOTIFIER_CONTROL_MODE                                        30:30
+#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NV987D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NV987D_SET_NOTIFIER_CONTROL_OFFSET                                      11:2
+#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY                                      31:31
+#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NV987D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NV987D_SET_NOTIFIER_CONTROL_FORMAT                                      28:28
+#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY                               (0x00000000)
+#define NV987D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD                            (0x00000001)
+#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE                              0:0
+#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_FALSE                        (0x00000000)
+#define NV987D_SET_NOTIFIER_CONTROL_NO_WAIT_ACTIVE_TRUE                         (0x00000001)
+#define NV987D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000088)
+#define NV987D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NV987D_GET_CAPABILITIES                                                 (0x0000008C)
+#define NV987D_GET_CAPABILITIES_DUMMY                                           31:0
+#define NV987D_SET_SPARE                                                        (0x0000016C)
+#define NV987D_SET_SPARE_UNUSED                                                 31:0
+#define NV987D_SET_SPARE_NOOP(b)                                                (0x00000170 + (b)*0x00000004)
+#define NV987D_SET_SPARE_NOOP_UNUSED                                            31:0
+
+#define NV987D_DAC_SET_CONTROL(a)                                               (0x00000180 + (a)*0x00000020)
+#define NV987D_DAC_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV987D_DAC_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV987D_DAC_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV987D_DAC_SET_CONTROL_PROTOCOL                                         12:8
+#define NV987D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT                                 (0x00000000)
+#define NV987D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT                                 (0x00000013)
+#define NV987D_DAC_SET_SW_SPARE_A(a)                                            (0x00000184 + (a)*0x00000020)
+#define NV987D_DAC_SET_SW_SPARE_A_CODE                                          31:0
+#define NV987D_DAC_SET_SW_SPARE_B(a)                                            (0x00000188 + (a)*0x00000020)
+#define NV987D_DAC_SET_SW_SPARE_B_CODE                                          31:0
+#define NV987D_DAC_SET_CUSTOM_REASON(a)                                         (0x00000190 + (a)*0x00000020)
+#define NV987D_DAC_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV987D_SOR_SET_CONTROL(a)                                               (0x00000200 + (a)*0x00000020)
+#define NV987D_SOR_SET_CONTROL_OWNER_MASK                                       3:0
+#define NV987D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NV987D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NV987D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NV987D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NV987D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NV987D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NV987D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NV987D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
+#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NV987D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NV987D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NV987D_SOR_SET_SW_SPARE_A(a)                                            (0x00000204 + (a)*0x00000020)
+#define NV987D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NV987D_SOR_SET_SW_SPARE_B(a)                                            (0x00000208 + (a)*0x00000020)
+#define NV987D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+#define NV987D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000210 + (a)*0x00000020)
+#define NV987D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+
+#define NV987D_PIOR_SET_CONTROL(a)                                              (0x00000300 + (a)*0x00000020)
+#define NV987D_PIOR_SET_CONTROL_OWNER_MASK                                      3:0
+#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_NONE                                 (0x00000000)
+#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0                                (0x00000001)
+#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1                                (0x00000002)
+#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2                                (0x00000004)
+#define NV987D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3                                (0x00000008)
+#define NV987D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
+#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
+#define NV987D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
+#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
+#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
+#define NV987D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
+#define NV987D_PIOR_SET_SW_SPARE_A(a)                                           (0x00000304 + (a)*0x00000020)
+#define NV987D_PIOR_SET_SW_SPARE_A_CODE                                         31:0
+#define NV987D_PIOR_SET_SW_SPARE_B(a)                                           (0x00000308 + (a)*0x00000020)
+#define NV987D_PIOR_SET_SW_SPARE_B_CODE                                         31:0
+#define NV987D_PIOR_SET_CUSTOM_REASON(a)                                        (0x00000310 + (a)*0x00000020)
+#define NV987D_PIOR_SET_CUSTOM_REASON_CODE                                      31:0
+
+#define NV987D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x00000400 + (a)*0x00000300)
+#define NV987D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                    3:0
+#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         8:8
+#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NV987D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NV987D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00000404 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  3:3
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  4:4
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     9:6
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT             (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000002)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000003)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000004)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000005)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000006)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000007)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000008)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000009)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            12:12
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                24:13
+#define NV987D_HEAD_SET_CONTROL(a)                                              (0x00000408 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTROL_STRUCTURE                                       0:0
+#define NV987D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE                           (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED                            (0x00000001)
+#define NV987D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00000410 + (a)*0x00000300)
+#define NV987D_HEAD_SET_OVERSCAN_COLOR_RED                                      9:0
+#define NV987D_HEAD_SET_OVERSCAN_COLOR_GRN                                      19:10
+#define NV987D_HEAD_SET_OVERSCAN_COLOR_BLU                                      29:20
+#define NV987D_HEAD_SET_RASTER_SIZE(a)                                          (0x00000414 + (a)*0x00000300)
+#define NV987D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NV987D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NV987D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00000418 + (a)*0x00000300)
+#define NV987D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NV987D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NV987D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000041C + (a)*0x00000300)
+#define NV987D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NV987D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NV987D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00000420 + (a)*0x00000300)
+#define NV987D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NV987D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NV987D_HEAD_SET_RASTER_VERT_BLANK2(a)                                   (0x00000424 + (a)*0x00000300)
+#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YSTART                               14:0
+#define NV987D_HEAD_SET_RASTER_VERT_BLANK2_YEND                                 30:16
+#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR(a)                                   (0x0000042C + (a)*0x00000300)
+#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_RED                                  9:0
+#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN                                19:10
+#define NV987D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE                                 29:20
+#define NV987D_HEAD_SET_BASE_LUT_LO(a)                                          (0x00000440 + (a)*0x00000300)
+#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE                                      31:31
+#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE                              (0x00000000)
+#define NV987D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE                               (0x00000001)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE                                        27:24
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_LORES                                  (0x00000000)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_HIRES                                  (0x00000001)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE                 (0x00000003)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE           (0x00000004)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE          (0x00000005)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE           (0x00000006)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE            (0x00000007)
+#define NV987D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE           (0x00000008)
+#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE                         20:20
+#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE                 (0x00000000)
+#define NV987D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                  (0x00000001)
+#define NV987D_HEAD_SET_BASE_LUT_HI(a)                                          (0x00000444 + (a)*0x00000300)
+#define NV987D_HEAD_SET_BASE_LUT_HI_ORIGIN                                      31:0
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO(a)                                        (0x00000448 + (a)*0x00000300)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE                                    31:31
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE                            (0x00000000)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE                             (0x00000001)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE                                      27:24
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES                                (0x00000000)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES                                (0x00000001)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE               (0x00000003)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE         (0x00000004)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE        (0x00000005)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE         (0x00000006)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE          (0x00000007)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE         (0x00000008)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE                       20:20
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE               (0x00000000)
+#define NV987D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE                (0x00000001)
+#define NV987D_HEAD_SET_OUTPUT_LUT_HI(a)                                        (0x0000044C + (a)*0x00000300)
+#define NV987D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN                                    31:0
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x00000450 + (a)*0x00000300)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x00000454 + (a)*0x00000300)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE                          21:20
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25                   (0x00000000)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28                   (0x00000001)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM               (0x00000002)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    24:24
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING                25:25
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE          (0x00000000)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE           (0x00000001)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  26:26
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00000458 + (a)*0x00000300)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NV987D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NV987D_HEAD_SET_CONTEXT_DMA_LUT(a)                                      (0x0000045C + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE                                  31:0
+#define NV987D_HEAD_SET_OFFSET(a)                                               (0x00000460 + (a)*0x00000300)
+#define NV987D_HEAD_SET_OFFSET_ORIGIN                                           31:0
+#define NV987D_HEAD_SET_SIZE(a)                                                 (0x00000468 + (a)*0x00000300)
+#define NV987D_HEAD_SET_SIZE_WIDTH                                              15:0
+#define NV987D_HEAD_SET_SIZE_HEIGHT                                             31:16
+#define NV987D_HEAD_SET_STORAGE(a)                                              (0x0000046C + (a)*0x00000300)
+#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT                                    3:0
+#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB                            (0x00000000)
+#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS                           (0x00000001)
+#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS                          (0x00000002)
+#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS                         (0x00000003)
+#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS                       (0x00000004)
+#define NV987D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS                     (0x00000005)
+#define NV987D_HEAD_SET_STORAGE_PITCH                                           20:8
+#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT                                   24:24
+#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                       (0x00000000)
+#define NV987D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH                             (0x00000001)
+#define NV987D_HEAD_SET_PARAMS(a)                                               (0x00000470 + (a)*0x00000300)
+#define NV987D_HEAD_SET_PARAMS_FORMAT                                           15:8
+#define NV987D_HEAD_SET_PARAMS_FORMAT_I8                                        (0x0000001E)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID16                                    (0x0000001F)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_VOID32                                    (0x0000002E)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                       (0x000000CA)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8                                  (0x000000CF)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10                               (0x000000D1)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                     (0x00000022)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                      (0x00000024)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8                                  (0x000000D5)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_R5G6B5                                    (0x000000E8)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5                                  (0x000000E9)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16                           (0x000000C6)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                    (0x00000023)
+#define NV987D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10                               (0x000000DF)
+#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE                                     1:0
+#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA                               (0x00000000)
+#define NV987D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA                               (0x00000002)
+#define NV987D_HEAD_SET_PARAMS_GAMMA                                            2:2
+#define NV987D_HEAD_SET_PARAMS_GAMMA_LINEAR                                     (0x00000000)
+#define NV987D_HEAD_SET_PARAMS_GAMMA_SRGB                                       (0x00000001)
+#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO(a)                                     (0x00000474 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE                                 31:0
+#define NV987D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x00000480 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   25:24
+#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE                                     27:26
+#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               15:8
+#define NV987D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               23:16
+#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION                              29:28
+#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND                  (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND          (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR                          (0x00000002)
+#define NV987D_HEAD_SET_OFFSETS_CURSOR(a,b)                                     (0x00000484 + (a)*0x00000300 + (b)*0x00000004)
+#define NV987D_HEAD_SET_OFFSETS_CURSOR_ORIGIN                                   31:0
+#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b)                                (0x0000048C + (a)*0x00000300 + (b)*0x00000004)
+#define NV987D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE                              31:0
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER(a)                                (0x00000494 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS                     2:0
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1              (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2              (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3              (0x00000002)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE     (0x00000003)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5              (0x00000004)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS                   4:3
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1            (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2            (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8            (0x00000002)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS                    23:16
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS                    31:24
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422                          8:8
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE                  (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE                   (0x00000001)
+#define NV987D_HEAD_SET_PROCAMP(a)                                              (0x00000498 + (a)*0x00000300)
+#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NV987D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020                            (0x00000003)
+#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF                                      2:2
+#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO                                 (0x00000000)
+#define NV987D_HEAD_SET_PROCAMP_CHROMA_LPF_ON                                   (0x00000001)
+#define NV987D_HEAD_SET_PROCAMP_SAT_COS                                         19:8
+#define NV987D_HEAD_SET_PROCAMP_SAT_SINE                                        31:20
+#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   5:5
+#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NV987D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               6:6
+#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NV987D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NV987D_HEAD_SET_DITHER_CONTROL(a)                                       (0x000004A0 + (a)*0x00000300)
+#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NV987D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NV987D_HEAD_SET_DITHER_CONTROL_BITS                                     2:1
+#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS                    (0x00000000)
+#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS                    (0x00000001)
+#define NV987D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS                   (0x00000002)
+#define NV987D_HEAD_SET_DITHER_CONTROL_MODE                                     6:3
+#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NV987D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NV987D_HEAD_SET_DITHER_CONTROL_PHASE                                    8:7
+#define NV987D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x000004B0 + (a)*0x00000300)
+#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NV987D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x000004B8 + (a)*0x00000300)
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x000004BC + (a)*0x00000300)
+#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NV987D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x000004C0 + (a)*0x00000300)
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a)                                (0x000004C4 + (a)*0x00000300)
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH                             14:0
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT                            30:16
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a)                                (0x000004C8 + (a)*0x00000300)
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH                             14:0
+#define NV987D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT                            30:16
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a)                            (0x000004D0 + (a)*0x00000300)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE                        0:0
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE                  (0x00000000)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE                   (0x00000001)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH                   11:8
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8             (0x00000000)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16            (0x00000001)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32            (0x00000003)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64            (0x00000005)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE                  13:12
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA            (0x00000000)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA            (0x00000002)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT                      17:16
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE           (0x00000000)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257            (0x00000001)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025           (0x00000002)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT                    21:20
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE         (0x00000000)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257          (0x00000001)
+#define NV987D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025         (0x00000002)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a)                                 (0x000004D4 + (a)*0x00000300)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE                             0:0
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE                       (0x00000000)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE                        (0x00000001)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH                        11:8
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16                 (0x00000001)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32                 (0x00000003)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64                 (0x00000005)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT                        13:12
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE             (0x00000000)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257              (0x00000001)
+#define NV987D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025             (0x00000002)
+#define NV987D_HEAD_SET_PROCESSING(a)                                           (0x000004E0 + (a)*0x00000300)
+#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS                                 0:0
+#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE                         (0x00000000)
+#define NV987D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE                          (0x00000001)
+#define NV987D_HEAD_SET_CONVERSION_RED(a)                                       (0x000004E4 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONVERSION_RED_GAIN                                     15:0
+#define NV987D_HEAD_SET_CONVERSION_RED_OFS                                      31:16
+#define NV987D_HEAD_SET_CONVERSION_GRN(a)                                       (0x000004E8 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONVERSION_GRN_GAIN                                     15:0
+#define NV987D_HEAD_SET_CONVERSION_GRN_OFS                                      31:16
+#define NV987D_HEAD_SET_CONVERSION_BLU(a)                                       (0x000004EC + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONVERSION_BLU_GAIN                                     15:0
+#define NV987D_HEAD_SET_CONVERSION_BLU_OFS                                      31:16
+#define NV987D_HEAD_SET_HDMI_CTRL(a)                                            (0x00000520 + (a)*0x00000300)
+#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
+#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
+#define NV987D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
+#define NV987D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
+#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR(a)                                  (0x00000524 + (a)*0x00000300)
+#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR                              9:0
+#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y                               19:10
+#define NV987D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB                              29:20
+#define NV987D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x0000052C + (a)*0x00000300 + (b)*0x00000004)
+#define NV987D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NV987D_HEAD_SET_SW_SPARE_A(a)                                           (0x0000054C + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NV987D_HEAD_SET_SW_SPARE_B(a)                                           (0x00000550 + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NV987D_HEAD_SET_SW_SPARE_C(a)                                           (0x00000554 + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NV987D_HEAD_SET_SW_SPARE_D(a)                                           (0x00000558 + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NV987D_HEAD_SET_GET_BLANKING_CTRL(a)                                    (0x0000055C + (a)*0x00000300)
+#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK                                 0:0
+#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                       (0x00000000)
+#define NV987D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE                          (0x00000001)
+#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK                               1:1
+#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                     (0x00000000)
+#define NV987D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                        (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION(a)                                  (0x00000560 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE                              0:0
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE                      (0x00000000)
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE                       (0x00000001)
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH                     12:1
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH                      24:13
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA(a)                               (0x00000564 + (a)*0x00000300)
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1                           7:4
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2                           11:8
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3                           15:12
+#define NV987D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE                       23:16
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a)                              (0x000006D0 + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED                          31:0
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a)                              (0x000006D4 + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED                          31:0
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a)                              (0x000006D8 + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED                          31:0
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a)                              (0x000006DC + (a)*0x00000300)
+#define NV987D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED                          31:0
+#define NV987D_HEAD_SET_SPARE(a)                                                (0x000006EC + (a)*0x00000300)
+#define NV987D_HEAD_SET_SPARE_UNUSED                                            31:0
+#define NV987D_HEAD_SET_SPARE_NOOP(a,b)                                         (0x000006F0 + (a)*0x00000300 + (b)*0x00000004)
+#define NV987D_HEAD_SET_SPARE_NOOP_UNUSED                                       31:0
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _cl987d_h
diff --git a/classes/display/clc37a.h b/classes/display/clc37a.h
new file mode 100644
index 0000000..3ea9e41
--- /dev/null
+++ b/classes/display/clc37a.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _clc37a__h_
+#define _clc37a__h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NVC37A_CURSOR_IMM_CHANNEL_PIO                                           (0x0000C37A)
+
+typedef volatile struct _clc37a_tag0 {
+    NvV32 Reserved00[0x2];
+    NvV32 Free;                                                                 // 0x00000008 - 0x0000000B
+    NvV32 Reserved01[0x7D];
+    NvV32 Update;                                                               // 0x00000200 - 0x00000203
+    NvV32 SetInterlockFlags;                                                    // 0x00000204 - 0x00000207
+    NvV32 SetCursorHotSpotPointOut[2];                                          // 0x00000208 - 0x0000020F
+    NvV32 SetWindowInterlockFlags;                                              // 0x00000210 - 0x00000213
+    NvV32 Reserved02[0x37B];
+} NVC37ADispCursorImmControlPio;
+
+#define NVC37A_FREE                                                             (0x00000008)
+#define NVC37A_FREE_COUNT                                                       5:0
+#define NVC37A_UPDATE                                                           (0x00000200)
+#define NVC37A_SET_INTERLOCK_FLAGS                                              (0x00000204)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0                       0:0
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1                       1:1
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2                       2:2
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3                       3:3
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4                       4:4
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5                       5:5
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6                       6:6
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7                       7:7
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE               (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE                (0x00000001)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE                          16:16
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE                  (0x00000000)
+#define NVC37A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE                   (0x00000001)
+#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT(b)                                 (0x00000208 + (b)*0x00000004)
+#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_X                                  15:0
+#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y                                  31:16
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS                                       (0x00000210)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0                0:0
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1                1:1
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2                2:2
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3                3:3
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4                4:4
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5                5:5
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6                6:6
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7                7:7
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8                8:8
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9                9:9
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE        (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE         (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10               10:10
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11               11:11
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12               12:12
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13               13:13
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14               14:14
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15               15:15
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16               16:16
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17               17:17
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18               18:18
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19               19:19
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20               20:20
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21               21:21
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22               22:22
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23               23:23
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24               24:24
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25               25:25
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26               26:26
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27               27:27
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28               28:28
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29               29:29
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30               30:30
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE        (0x00000001)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31               31:31
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE       (0x00000000)
+#define NVC37A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE        (0x00000001)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _clc37a_h
+
diff --git a/classes/display/clc37b.h b/classes/display/clc37b.h
new file mode 100644
index 0000000..b26e44d
--- /dev/null
+++ b/classes/display/clc37b.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _clC37b_h_
+#define _clC37b_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NVC37B_WINDOW_IMM_CHANNEL_DMA                                           (0x0000C37B)
+
+// dma opcode instructions
+#define NVC37B_DMA                                                                     
+#define NVC37B_DMA_OPCODE                                                        31:29 
+#define NVC37B_DMA_OPCODE_METHOD                                            0x00000000 
+#define NVC37B_DMA_OPCODE_JUMP                                              0x00000001 
+#define NVC37B_DMA_OPCODE_NONINC_METHOD                                     0x00000002 
+#define NVC37B_DMA_OPCODE_SET_SUBDEVICE_MASK                                0x00000003 
+#define NVC37B_DMA_METHOD_COUNT                                                  27:18 
+#define NVC37B_DMA_METHOD_OFFSET                                                  13:2 
+#define NVC37B_DMA_DATA                                                           31:0 
+#define NVC37B_DMA_DATA_NOP                                                 0x00000000 
+#define NVC37B_DMA_JUMP_OFFSET                                                    11:2 
+#define NVC37B_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 
+
+// class methods
+#define NVC37B_PUT                                                              (0x00000000)
+#define NVC37B_PUT_PTR                                                          9:0
+#define NVC37B_GET                                                              (0x00000004)
+#define NVC37B_GET_PTR                                                          9:0
+#define NVC37B_UPDATE                                                           (0x00000200)
+#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW                                     1:1
+#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE                             (0x00000000)
+#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE                              (0x00000001)
+#define NVC37B_SET_POINT_OUT(b)                                                 (0x00000208 + (b)*0x00000004)
+#define NVC37B_SET_POINT_OUT_X                                                  15:0
+#define NVC37B_SET_POINT_OUT_Y                                                  31:16
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _clC37b_h
diff --git a/classes/display/clc37d.h b/classes/display/clc37d.h
new file mode 100644
index 0000000..4b9e3ba
--- /dev/null
+++ b/classes/display/clc37d.h
@@ -0,0 +1,625 @@
+/*
+ * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _clC37d_h_
+#define _clC37d_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NVC37D_CORE_CHANNEL_DMA                                                 (0x0000C37D)
+
+#define NV_DISP_NOTIFIER                                                             0x00000000
+#define NV_DISP_NOTIFIER_SIZEOF                                                      0x00000010
+#define NV_DISP_NOTIFIER__0                                                          0x00000000
+#define NV_DISP_NOTIFIER__0_PRESENT_COUNT                                            7:0
+#define NV_DISP_NOTIFIER__0_FIELD                                                    8:8
+#define NV_DISP_NOTIFIER__0_FLIP_TYPE                                                9:9
+#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING                                    0x00000000
+#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE                                      0x00000001
+#define NV_DISP_NOTIFIER__0_R1                                                       15:10
+#define NV_DISP_NOTIFIER__0_R2                                                       23:16
+#define NV_DISP_NOTIFIER__0_R3                                                       29:24
+#define NV_DISP_NOTIFIER__0_STATUS                                                   31:30
+#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN                                         0x00000000
+#define NV_DISP_NOTIFIER__0_STATUS_BEGUN                                             0x00000001
+#define NV_DISP_NOTIFIER__0_STATUS_FINISHED                                          0x00000002
+#define NV_DISP_NOTIFIER__1                                                          0x00000001
+#define NV_DISP_NOTIFIER__1_R4                                                       31:0
+#define NV_DISP_NOTIFIER__2                                                          0x00000002
+#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO                                             31:0
+#define NV_DISP_NOTIFIER__3                                                          0x00000003
+#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI                                             31:0
+
+
+// dma opcode instructions
+#define NVC37D_DMA                                                                     
+#define NVC37D_DMA_OPCODE                                                        31:29 
+#define NVC37D_DMA_OPCODE_METHOD                                            0x00000000 
+#define NVC37D_DMA_OPCODE_JUMP                                              0x00000001 
+#define NVC37D_DMA_OPCODE_NONINC_METHOD                                     0x00000002 
+#define NVC37D_DMA_OPCODE_SET_SUBDEVICE_MASK                                0x00000003 
+#define NVC37D_DMA_METHOD_COUNT                                                  27:18 
+#define NVC37D_DMA_METHOD_OFFSET                                                  13:2 
+#define NVC37D_DMA_DATA                                                           31:0 
+#define NVC37D_DMA_DATA_NOP                                                 0x00000000 
+#define NVC37D_DMA_JUMP_OFFSET                                                    11:2 
+#define NVC37D_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 
+
+// if cap SUPPORT_FLEXIBLE_WIN_MAPPING is FALSE, this define can be used to obtain which head a window is mapped to
+#define NVC37D_WINDOW_MAPPED_TO_HEAD(w) ((w)>>1)
+#define NVC37D_GET_VALID_WINDOWMASK_FOR_HEAD(h) ((1<<((h)*2)) | (1<<((h)*2+1)))
+
+// class methods
+#define NVC37D_PUT                                                              (0x00000000)
+#define NVC37D_PUT_PTR                                                          9:0
+#define NVC37D_GET                                                              (0x00000004)
+#define NVC37D_GET_PTR                                                          9:0
+#define NVC37D_UPDATE                                                           (0x00000200)
+#define NVC37D_UPDATE_SPECIAL_HANDLING                                          21:20
+#define NVC37D_UPDATE_SPECIAL_HANDLING_NONE                                     (0x00000000)
+#define NVC37D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM                             (0x00000001)
+#define NVC37D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH                              (0x00000002)
+#define NVC37D_UPDATE_SPECIAL_HANDLING_REASON                                   19:12
+#define NVC37D_UPDATE_INHIBIT_INTERRUPTS                                        24:24
+#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_FALSE                                  (0x00000000)
+#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_TRUE                                   (0x00000001)
+#define NVC37D_SET_CONTEXT_DMA_NOTIFIER                                         (0x00000208)
+#define NVC37D_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NVC37D_SET_NOTIFIER_CONTROL                                             (0x0000020C)
+#define NVC37D_SET_NOTIFIER_CONTROL_MODE                                        0:0
+#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NVC37D_SET_NOTIFIER_CONTROL_OFFSET                                      11:4
+#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY                                      12:12
+#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE                              (0x00000000)
+#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE                               (0x00000001)
+#define NVC37D_SET_CONTROL                                                      (0x00000210)
+#define NVC37D_SET_INTERLOCK_FLAGS                                              (0x00000218)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i)                     ((i)+0):((i)+0)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1                8
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE                (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE                 (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0                       0:0
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1                       1:1
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2                       2:2
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3                       3:3
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4                       4:4
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5                       5:5
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6                       6:6
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7                       7:7
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE               (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE                (0x00000001)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE                          16:16
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE                  (0x00000000)
+#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE                   (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS                                       (0x0000021C)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i)              ((i)+0):((i)+0)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1         32
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE         (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE          (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0                0:0
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1                1:1
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2                2:2
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3                3:3
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4                4:4
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5                5:5
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6                6:6
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7                7:7
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8                8:8
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9                9:9
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE        (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE         (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10               10:10
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11               11:11
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12               12:12
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13               13:13
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14               14:14
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15               15:15
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16               16:16
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17               17:17
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18               18:18
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19               19:19
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20               20:20
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21               21:21
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22               22:22
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23               23:23
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24               24:24
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25               25:25
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26               26:26
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27               27:27
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28               28:28
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29               29:29
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30               30:30
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE        (0x00000001)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31               31:31
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE       (0x00000000)
+#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE        (0x00000001)
+#define NVC37D_GET_RG_SCAN_LINE(b)                                              (0x00000220 + (b)*0x00000004)
+#define NVC37D_GET_RG_SCAN_LINE_LINE                                            15:0
+#define NVC37D_GET_RG_SCAN_LINE_VBLANK                                          16:16
+#define NVC37D_GET_RG_SCAN_LINE_VBLANK_FALSE                                    (0x00000000)
+#define NVC37D_GET_RG_SCAN_LINE_VBLANK_TRUE                                     (0x00000001)
+#define NVC37D_SET_GET_BLANKING_CTRL(b)                                         (0x00000240 + (b)*0x00000004)
+#define NVC37D_SET_GET_BLANKING_CTRL_BLANK                                      0:0
+#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE                            (0x00000000)
+#define NVC37D_SET_GET_BLANKING_CTRL_BLANK_ENABLE                               (0x00000001)
+#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK                                    1:1
+#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE                          (0x00000000)
+#define NVC37D_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE                             (0x00000001)
+
+#define NVC37D_SOR_SET_CONTROL(a)                                               (0x00000300 + (a)*0x00000020)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK                                       7:0
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_NONE                                  (0x00000000)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD0                                 (0x00000001)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD1                                 (0x00000002)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD2                                 (0x00000004)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD3                                 (0x00000008)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD4                                 (0x00000010)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD5                                 (0x00000020)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD6                                 (0x00000040)
+#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD7                                 (0x00000080)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL                                         11:8
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DSI                                     (0x0000000A)
+#define NVC37D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
+#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 16:16
+#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
+#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
+#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE                             21:20
+#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF                         (0x00000000)
+#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2                          (0x00000001)
+#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4                          (0x00000002)
+#define NVC37D_SOR_SET_CUSTOM_REASON(a)                                         (0x00000304 + (a)*0x00000020)
+#define NVC37D_SOR_SET_CUSTOM_REASON_CODE                                       31:0
+#define NVC37D_SOR_SET_SW_SPARE_A(a)                                            (0x00000308 + (a)*0x00000020)
+#define NVC37D_SOR_SET_SW_SPARE_A_CODE                                          31:0
+#define NVC37D_SOR_SET_SW_SPARE_B(a)                                            (0x0000030C + (a)*0x00000020)
+#define NVC37D_SOR_SET_SW_SPARE_B_CODE                                          31:0
+
+#define NVC37D_WINDOW_SET_CONTROL(a)                                            (0x00001000 + (a)*0x00000080)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER                                         3:0
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD(i)                                 (0x00000000 +(i))
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1                            8
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD0                                   (0x00000000)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD1                                   (0x00000001)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD2                                   (0x00000002)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD3                                   (0x00000003)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD4                                   (0x00000004)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD5                                   (0x00000005)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD6                                   (0x00000006)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD7                                   (0x00000007)
+#define NVC37D_WINDOW_SET_CONTROL_OWNER_NONE                                    (0x0000000F)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a)                         (0x00001004 + (a)*0x00000080)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP             0:0
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE       (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE        (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP             1:1
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE       (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE        (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP             2:2
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE       (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE        (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP             3:3
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE       (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE        (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422              4:4
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE        (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE         (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420              5:5
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE        (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE         (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444              6:6
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE        (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE         (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420         7:7
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE   (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE    (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422         8:8
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE   (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE    (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R        9:9
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE  (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE   (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444         10:10
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE   (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE    (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420          11:11
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE    (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE     (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444          12:12
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE    (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE     (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420     13:13
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422     14:14
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R    15:15
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444     16:16
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a)                 (0x00001008 + (a)*0x00000080)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP     0:0
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP     1:1
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP     2:2
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP     3:3
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422      4:4
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420      5:5
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444      6:6
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420  11:11
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444  12:12
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
+#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR(a)                             (0x0000100C + (a)*0x00000080)
+#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_HORIZONTAL                     15:0
+#define NVC37D_WINDOW_SET_MAX_INPUT_SCALE_FACTOR_VERTICAL                       31:16
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a)                                (0x00001010 + (a)*0x00000080)
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE       14:0
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT                         17:16
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_NONE              (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_257               (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_1025              (0x00000002)
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS                 22:20
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2          (0x00000001)
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5          (0x00000004)
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED                 24:24
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE           (0x00000000)
+#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE            (0x00000001)
+
+#define NVC37D_HEAD_SET_PROCAMP(a)                                              (0x00002000 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE                                     1:0
+#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB                                 (0x00000000)
+#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601                             (0x00000001)
+#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709                             (0x00000002)
+#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020                            (0x00000003)
+#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF                                      3:3
+#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE                              (0x00000000)
+#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE                               (0x00000001)
+#define NVC37D_HEAD_SET_PROCAMP_SAT_COS                                         15:4
+#define NVC37D_HEAD_SET_PROCAMP_SAT_SINE                                        27:16
+#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE                                   28:28
+#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA                              (0x00000000)
+#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA                               (0x00000001)
+#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION                               29:29
+#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE                       (0x00000000)
+#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE                        (0x00000001)
+#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL                                     31:30
+#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_AUTO                                (0x00000000)
+#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_VIDEO                               (0x00000001)
+#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_GRAPHICS                            (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a)                              (0x00002004 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY                  2:2
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY                  3:3
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE    (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE    (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH                     7:4
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422          (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444          (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422          (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422          (0x00000003)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444          (0x00000004)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444          (0x00000005)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422          (0x00000006)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444          (0x00000007)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444          (0x00000008)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE            24:24
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE    (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE     (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG                23:12
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a)                                (0x0000200C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ                             30:0
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001                    31:31
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE              (0x00000000)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE               (0x00000001)
+#define NVC37D_HEAD_SET_DITHER_CONTROL(a)                                       (0x00002018 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE                                   0:0
+#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE                           (0x00000000)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE                            (0x00000001)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS                                     5:4
+#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS                           (0x00000000)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS                           (0x00000001)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS                          (0x00000002)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS                          (0x00000003)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE                            2:2
+#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE                    (0x00000000)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE                     (0x00000001)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE                                     10:8
+#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC                     (0x00000000)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC                      (0x00000001)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2                         (0x00000002)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2                          (0x00000003)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL                            (0x00000004)
+#define NVC37D_HEAD_SET_DITHER_CONTROL_PHASE                                    13:12
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a)                            (0x0000201C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER                    0:0
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE              (0x00000000)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE               (0x00000001)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING                       4:4
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE               (0x00000000)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE                (0x00000001)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE                  9:8
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK           (0x00000000)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK           (0x00000001)
+#define NVC37D_HEAD_SET_DISPLAY_ID(a,b)                                         (0x00002020 + (a)*0x00000400 + (b)*0x00000004)
+#define NVC37D_HEAD_SET_DISPLAY_ID_CODE                                         31:0
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a)                            (0x00002028 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ                         30:0
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001                31:31
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE          (0x00000000)
+#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE           (0x00000001)
+#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR(a)                              (0x0000202C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_HORIZONTAL                      15:0
+#define NVC37D_HEAD_SET_MAX_OUTPUT_SCALE_FACTOR_VERTICAL                        31:16
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS(a)                                    (0x00002030 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR                                2:0
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE                     (0x00000000)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32                  (0x00000001)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64                  (0x00000002)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128                (0x00000003)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256                (0x00000004)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT                            5:4
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE                 (0x00000000)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257                  (0x00000001)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025                 (0x00000002)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED                     8:8
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE               (0x00000000)
+#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE                (0x00000001)
+#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN(a)                                    (0x00002048 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_X                                     14:0
+#define NVC37D_HEAD_SET_VIEWPORT_POINT_IN_Y                                     30:16
+#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN(a)                                     (0x0000204C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH                                  14:0
+#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT                                 30:16
+#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT(a)                                    (0x00002058 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH                                 14:0
+#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT                                30:16
+#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a)                            (0x0000205C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X                             15:0
+#define NVC37D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y                             31:16
+#define NVC37D_HEAD_SET_DESKTOP_COLOR(a)                                        (0x00002060 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_DESKTOP_COLOR_ALPHA                                     7:0
+#define NVC37D_HEAD_SET_DESKTOP_COLOR_RED                                       15:8
+#define NVC37D_HEAD_SET_DESKTOP_COLOR_GREEN                                     23:16
+#define NVC37D_HEAD_SET_DESKTOP_COLOR_BLUE                                      31:24
+#define NVC37D_HEAD_SET_RASTER_SIZE(a)                                          (0x00002064 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_RASTER_SIZE_WIDTH                                       14:0
+#define NVC37D_HEAD_SET_RASTER_SIZE_HEIGHT                                      30:16
+#define NVC37D_HEAD_SET_RASTER_SYNC_END(a)                                      (0x00002068 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_RASTER_SYNC_END_X                                       14:0
+#define NVC37D_HEAD_SET_RASTER_SYNC_END_Y                                       30:16
+#define NVC37D_HEAD_SET_RASTER_BLANK_END(a)                                     (0x0000206C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_RASTER_BLANK_END_X                                      14:0
+#define NVC37D_HEAD_SET_RASTER_BLANK_END_Y                                      30:16
+#define NVC37D_HEAD_SET_RASTER_BLANK_START(a)                                   (0x00002070 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_RASTER_BLANK_START_X                                    14:0
+#define NVC37D_HEAD_SET_RASTER_BLANK_START_Y                                    30:16
+#define NVC37D_HEAD_SET_OVERSCAN_COLOR(a)                                       (0x00002078 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_OVERSCAN_COLOR_RED_CR                                   9:0
+#define NVC37D_HEAD_SET_OVERSCAN_COLOR_GREEN_Y                                  19:10
+#define NVC37D_HEAD_SET_OVERSCAN_COLOR_BLUE_CB                                  29:20
+#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR(a)                           (0x0000207C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_RED_CR                       9:0
+#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_GREEN_Y                      19:10
+#define NVC37D_HEAD_SET_FRAME_PACKED_VACTIVE_COLOR_BLUE_CB                      29:20
+#define NVC37D_HEAD_SET_HDMI_CTRL(a)                                            (0x00002080 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT                                  2:0
+#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL                           (0x00000000)
+#define NVC37D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED                         (0x00000001)
+#define NVC37D_HEAD_SET_HDMI_CTRL_HDMI_VIC                                      11:4
+#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b)                                 (0x00002088 + (a)*0x00000400 + (b)*0x00000004)
+#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE                               31:0
+#define NVC37D_HEAD_SET_OFFSET_CURSOR(a,b)                                      (0x00002090 + (a)*0x00000400 + (b)*0x00000004)
+#define NVC37D_HEAD_SET_OFFSET_CURSOR_ORIGIN                                    31:0
+#define NVC37D_HEAD_SET_CONTROL_CURSOR(a)                                       (0x0000209C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE                                   31:31
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE                           (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE                            (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT                                   7:0
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5                          (0x000000E9)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8                          (0x000000CF)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE                                     9:8
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32                             (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64                             (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128                           (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256                           (0x00000003)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X                               19:12
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y                               27:20
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA                                 29:28
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_NONE                            (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_SRGB                            (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV8_10                         (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV12                           (0x00000003)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a)                           (0x000020A0 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1                           7:0
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT   11:8
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE                         16:16
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND                   (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR                     (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT(a)                                   (0x000020A4 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE                                 1:0
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257                        (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025                       (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE                                5:4
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY                          (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XRBIAS                         (0x00000001)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XVYCC                          (0x00000002)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE                          9:8
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INDEX                    (0x00000000)
+#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE              (0x00000001)
+#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT(a)                                    (0x000020A8 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT_ORIGIN                                31:0
+#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(a)                               (0x000020AC + (a)*0x00000400)
+#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT_HANDLE                           31:0
+#define NVC37D_HEAD_SET_PRESENT_CONTROL(a)                                      (0x0000218C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD                         0:0
+#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE                 (0x00000000)
+#define NVC37D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE                  (0x00000001)
+#define NVC37D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD                             6:4
+#define NVC37D_HEAD_SET_SW_SPARE_A(a)                                           (0x00002194 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_SW_SPARE_A_CODE                                         31:0
+#define NVC37D_HEAD_SET_SW_SPARE_B(a)                                           (0x00002198 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_SW_SPARE_B_CODE                                         31:0
+#define NVC37D_HEAD_SET_SW_SPARE_C(a)                                           (0x0000219C + (a)*0x00000400)
+#define NVC37D_HEAD_SET_SW_SPARE_C_CODE                                         31:0
+#define NVC37D_HEAD_SET_SW_SPARE_D(a)                                           (0x000021A0 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_SW_SPARE_D_CODE                                         31:0
+#define NVC37D_HEAD_SET_MIN_FRAME_IDLE(a)                                       (0x00002218 + (a)*0x00000400)
+#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_LEADING_RASTER_LINES                     14:0
+#define NVC37D_HEAD_SET_MIN_FRAME_IDLE_TRAILING_RASTER_LINES                    30:16
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _clC37d_h
diff --git a/classes/display/clc37e.h b/classes/display/clc37e.h
new file mode 100644
index 0000000..f5fec92
--- /dev/null
+++ b/classes/display/clc37e.h
@@ -0,0 +1,446 @@
+/*
+ * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef _clC37e_h_
+#define _clC37e_h_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NVC37E_WINDOW_CHANNEL_DMA                                               (0x0000C37E)
+
+// dma opcode instructions
+#define NVC37E_DMA                                                                     
+#define NVC37E_DMA_OPCODE                                                        31:29 
+#define NVC37E_DMA_OPCODE_METHOD                                            0x00000000 
+#define NVC37E_DMA_OPCODE_JUMP                                              0x00000001 
+#define NVC37E_DMA_OPCODE_NONINC_METHOD                                     0x00000002 
+#define NVC37E_DMA_OPCODE_SET_SUBDEVICE_MASK                                0x00000003 
+#define NVC37E_DMA_METHOD_COUNT                                                  27:18 
+#define NVC37E_DMA_METHOD_OFFSET                                                  13:2 
+#define NVC37E_DMA_DATA                                                           31:0 
+#define NVC37E_DMA_DATA_NOP                                                 0x00000000 
+#define NVC37E_DMA_JUMP_OFFSET                                                    11:2 
+#define NVC37E_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 
+
+// class methods
+#define NVC37E_PUT                                                              (0x00000000)
+#define NVC37E_PUT_PTR                                                          9:0
+#define NVC37E_GET                                                              (0x00000004)
+#define NVC37E_GET_PTR                                                          9:0
+#define NVC37E_UPDATE                                                           (0x00000200)
+#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM                                    12:12
+#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE                            (0x00000000)
+#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE                             (0x00000001)
+#define NVC37E_GET_LINE                                                         (0x00000208)
+#define NVC37E_GET_LINE_LINE                                                    15:0
+#define NVC37E_SET_SEMAPHORE_CONTROL                                            (0x0000020C)
+#define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET                                     7:0
+#define NVC37E_SET_SEMAPHORE_ACQUIRE                                            (0x00000210)
+#define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE                                      31:0
+#define NVC37E_SET_SEMAPHORE_RELEASE                                            (0x00000214)
+#define NVC37E_SET_SEMAPHORE_RELEASE_VALUE                                      31:0
+#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE                                        (0x00000218)
+#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE                                 31:0
+#define NVC37E_SET_CONTEXT_DMA_NOTIFIER                                         (0x0000021C)
+#define NVC37E_SET_CONTEXT_DMA_NOTIFIER_HANDLE                                  31:0
+#define NVC37E_SET_NOTIFIER_CONTROL                                             (0x00000220)
+#define NVC37E_SET_NOTIFIER_CONTROL_MODE                                        0:0
+#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE                                  (0x00000000)
+#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN                           (0x00000001)
+#define NVC37E_SET_NOTIFIER_CONTROL_OFFSET                                      11:4
+#define NVC37E_SET_SIZE                                                         (0x00000224)
+#define NVC37E_SET_SIZE_WIDTH                                                   15:0
+#define NVC37E_SET_SIZE_HEIGHT                                                  31:16
+#define NVC37E_SET_STORAGE                                                      (0x00000228)
+#define NVC37E_SET_STORAGE_BLOCK_HEIGHT                                         3:0
+#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB                (0x00000000)
+#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS               (0x00000001)
+#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS              (0x00000002)
+#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS             (0x00000003)
+#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS           (0x00000004)
+#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS         (0x00000005)
+#define NVC37E_SET_STORAGE_MEMORY_LAYOUT                                        4:4
+#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR                            (0x00000000)
+#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_PITCH                                  (0x00000001)
+#define NVC37E_SET_PARAMS                                                       (0x0000022C)
+#define NVC37E_SET_PARAMS_FORMAT                                                7:0
+#define NVC37E_SET_PARAMS_FORMAT_I8                                             (0x0000001E)
+#define NVC37E_SET_PARAMS_FORMAT_R4G4B4A4                                       (0x0000002F)
+#define NVC37E_SET_PARAMS_FORMAT_R5G6B5                                         (0x000000E8)
+#define NVC37E_SET_PARAMS_FORMAT_A1R5G5B5                                       (0x000000E9)
+#define NVC37E_SET_PARAMS_FORMAT_R5G5B5A1                                       (0x0000002E)
+#define NVC37E_SET_PARAMS_FORMAT_A8R8G8B8                                       (0x000000CF)
+#define NVC37E_SET_PARAMS_FORMAT_X8R8G8B8                                       (0x000000E6)
+#define NVC37E_SET_PARAMS_FORMAT_A8B8G8R8                                       (0x000000D5)
+#define NVC37E_SET_PARAMS_FORMAT_X8B8G8R8                                       (0x000000F9)
+#define NVC37E_SET_PARAMS_FORMAT_A2R10G10B10                                    (0x000000DF)
+#define NVC37E_SET_PARAMS_FORMAT_A2B10G10R10                                    (0x000000D1)
+#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS                          (0x00000022)
+#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC                           (0x00000024)
+#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS                         (0x00000023)
+#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16                                (0x000000C6)
+#define NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16                            (0x000000CA)
+#define NVC37E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422                              (0x00000028)
+#define NVC37E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422                              (0x00000029)
+#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N444                                 (0x00000035)
+#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422                                 (0x00000036)
+#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422R                                (0x00000037)
+#define NVC37E_SET_PARAMS_FORMAT_Y8___V8U8_N420                                 (0x00000038)
+#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N444                              (0x0000003A)
+#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N420                              (0x0000003B)
+#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N444                              (0x00000055)
+#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422                              (0x00000056)
+#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422R                             (0x00000057)
+#define NVC37E_SET_PARAMS_FORMAT_Y10___V10U10_N420                              (0x00000058)
+#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N444                           (0x0000005A)
+#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N420                           (0x0000005B)
+#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N444                              (0x00000075)
+#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422                              (0x00000076)
+#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422R                             (0x00000077)
+#define NVC37E_SET_PARAMS_FORMAT_Y12___V12U12_N420                              (0x00000078)
+#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N444                           (0x0000007A)
+#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N420                           (0x0000007B)
+#define NVC37E_SET_PARAMS_COLOR_SPACE                                           9:8
+#define NVC37E_SET_PARAMS_COLOR_SPACE_RGB                                       (0x00000000)
+#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_601                                   (0x00000001)
+#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_709                                   (0x00000002)
+#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_2020                                  (0x00000003)
+#define NVC37E_SET_PARAMS_INPUT_RANGE                                           13:12
+#define NVC37E_SET_PARAMS_INPUT_RANGE_BYPASS                                    (0x00000000)
+#define NVC37E_SET_PARAMS_INPUT_RANGE_LIMITED                                   (0x00000001)
+#define NVC37E_SET_PARAMS_INPUT_RANGE_FULL                                      (0x00000002)
+#define NVC37E_SET_PARAMS_UNDERREPLICATE                                        16:16
+#define NVC37E_SET_PARAMS_UNDERREPLICATE_DISABLE                                (0x00000000)
+#define NVC37E_SET_PARAMS_UNDERREPLICATE_ENABLE                                 (0x00000001)
+#define NVC37E_SET_PARAMS_DE_GAMMA                                              21:20
+#define NVC37E_SET_PARAMS_DE_GAMMA_NONE                                         (0x00000000)
+#define NVC37E_SET_PARAMS_DE_GAMMA_SRGB                                         (0x00000001)
+#define NVC37E_SET_PARAMS_DE_GAMMA_YUV8_10                                      (0x00000002)
+#define NVC37E_SET_PARAMS_DE_GAMMA_YUV12                                        (0x00000003)
+#define NVC37E_SET_PARAMS_CSC                                                   17:17
+#define NVC37E_SET_PARAMS_CSC_DISABLE                                           (0x00000000)
+#define NVC37E_SET_PARAMS_CSC_ENABLE                                            (0x00000001)
+#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND                                    18:18
+#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE                            (0x00000000)
+#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE                             (0x00000001)
+#define NVC37E_SET_PARAMS_SWAP_UV                                               19:19
+#define NVC37E_SET_PARAMS_SWAP_UV_DISABLE                                       (0x00000000)
+#define NVC37E_SET_PARAMS_SWAP_UV_ENABLE                                        (0x00000001)
+#define NVC37E_SET_PLANAR_STORAGE(b)                                            (0x00000230 + (b)*0x00000004)
+#define NVC37E_SET_PLANAR_STORAGE_PITCH                                         12:0
+#define NVC37E_SET_CONTEXT_DMA_ISO(b)                                           (0x00000240 + (b)*0x00000004)
+#define NVC37E_SET_CONTEXT_DMA_ISO_HANDLE                                       31:0
+#define NVC37E_SET_OFFSET(b)                                                    (0x00000260 + (b)*0x00000004)
+#define NVC37E_SET_OFFSET_ORIGIN                                                31:0
+#define NVC37E_SET_PROCESSING                                                   (0x00000280)
+#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS                                  0:0
+#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_DISABLE                          (0x00000000)
+#define NVC37E_SET_PROCESSING_USE_GAIN_OFFSETS_ENABLE                           (0x00000001)
+#define NVC37E_SET_CONVERSION_RED                                               (0x00000284)
+#define NVC37E_SET_CONVERSION_RED_GAIN                                          15:0
+#define NVC37E_SET_CONVERSION_RED_OFFSET                                        31:16
+#define NVC37E_SET_CONVERSION_GREEN                                             (0x00000288)
+#define NVC37E_SET_CONVERSION_GREEN_GAIN                                        15:0
+#define NVC37E_SET_CONVERSION_GREEN_OFFSET                                      31:16
+#define NVC37E_SET_CONVERSION_BLUE                                              (0x0000028C)
+#define NVC37E_SET_CONVERSION_BLUE_GAIN                                         15:0
+#define NVC37E_SET_CONVERSION_BLUE_OFFSET                                       31:16
+#define NVC37E_SET_POINT_IN(b)                                                  (0x00000290 + (b)*0x00000004)
+#define NVC37E_SET_POINT_IN_X                                                   15:0
+#define NVC37E_SET_POINT_IN_Y                                                   31:16
+#define NVC37E_SET_SIZE_IN                                                      (0x00000298)
+#define NVC37E_SET_SIZE_IN_WIDTH                                                14:0
+#define NVC37E_SET_SIZE_IN_HEIGHT                                               30:16
+#define NVC37E_SET_SIZE_OUT                                                     (0x000002A4)
+#define NVC37E_SET_SIZE_OUT_WIDTH                                               14:0
+#define NVC37E_SET_SIZE_OUT_HEIGHT                                              30:16
+#define NVC37E_SET_CONTROL_INPUT_LUT                                            (0x000002B0)
+#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE                                       1:0
+#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257                              (0x00000000)
+#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025                             (0x00000002)
+#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE                                      5:4
+#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY                                (0x00000000)
+#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XRBIAS                               (0x00000001)
+#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XVYCC                                (0x00000002)
+#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE                                9:8
+#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INDEX                          (0x00000000)
+#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE                    (0x00000001)
+#define NVC37E_SET_OFFSET_INPUT_LUT                                             (0x000002B4)
+#define NVC37E_SET_OFFSET_INPUT_LUT_ORIGIN                                      31:0
+#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT                                        (0x000002B8)
+#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT_HANDLE                                 31:0
+#define NVC37E_SET_CSC_RED2RED                                                  (0x000002BC)
+#define NVC37E_SET_CSC_RED2RED_COEFF                                            18:0
+#define NVC37E_SET_CSC_GREEN2RED                                                (0x000002C0)
+#define NVC37E_SET_CSC_GREEN2RED_COEFF                                          18:0
+#define NVC37E_SET_CSC_BLUE2RED                                                 (0x000002C4)
+#define NVC37E_SET_CSC_BLUE2RED_COEFF                                           18:0
+#define NVC37E_SET_CSC_CONSTANT2RED                                             (0x000002C8)
+#define NVC37E_SET_CSC_CONSTANT2RED_COEFF                                       18:0
+#define NVC37E_SET_CSC_RED2GREEN                                                (0x000002CC)
+#define NVC37E_SET_CSC_RED2GREEN_COEFF                                          18:0
+#define NVC37E_SET_CSC_GREEN2GREEN                                              (0x000002D0)
+#define NVC37E_SET_CSC_GREEN2GREEN_COEFF                                        18:0
+#define NVC37E_SET_CSC_BLUE2GREEN                                               (0x000002D4)
+#define NVC37E_SET_CSC_BLUE2GREEN_COEFF                                         18:0
+#define NVC37E_SET_CSC_CONSTANT2GREEN                                           (0x000002D8)
+#define NVC37E_SET_CSC_CONSTANT2GREEN_COEFF                                     18:0
+#define NVC37E_SET_CSC_RED2BLUE                                                 (0x000002DC)
+#define NVC37E_SET_CSC_RED2BLUE_COEFF                                           18:0
+#define NVC37E_SET_CSC_GREEN2BLUE                                               (0x000002E0)
+#define NVC37E_SET_CSC_GREEN2BLUE_COEFF                                         18:0
+#define NVC37E_SET_CSC_BLUE2BLUE                                                (0x000002E4)
+#define NVC37E_SET_CSC_BLUE2BLUE_COEFF                                          18:0
+#define NVC37E_SET_CSC_CONSTANT2BLUE                                            (0x000002E8)
+#define NVC37E_SET_CSC_CONSTANT2BLUE_COEFF                                      18:0
+#define NVC37E_SET_COMPOSITION_CONTROL                                          (0x000002EC)
+#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT                         1:0
+#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE                 (0x00000000)
+#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC                     (0x00000001)
+#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST                     (0x00000002)
+#define NVC37E_SET_COMPOSITION_CONTROL_DEPTH                                    11:4
+#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA                                   (0x000002F0)
+#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K1                                7:0
+#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K2                                15:8
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT                                    (0x000002F4)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT      3:0
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE  (0x00000001)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1   (0x00000002)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT   7:4
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT      11:8
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE  (0x00000001)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1   (0x00000002)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2   (0x00000003)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT   15:12
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT      19:16
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1   (0x00000002)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2   (0x00000003)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT   23:20
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT      27:24
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE  (0x00000001)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2   (0x00000003)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT   31:28
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
+#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
+#define NVC37E_SET_KEY_ALPHA                                                    (0x000002F8)
+#define NVC37E_SET_KEY_ALPHA_MIN                                                15:0
+#define NVC37E_SET_KEY_ALPHA_MAX                                                31:16
+#define NVC37E_SET_KEY_RED_CR                                                   (0x000002FC)
+#define NVC37E_SET_KEY_RED_CR_MIN                                               15:0
+#define NVC37E_SET_KEY_RED_CR_MAX                                               31:16
+#define NVC37E_SET_KEY_GREEN_Y                                                  (0x00000300)
+#define NVC37E_SET_KEY_GREEN_Y_MIN                                              15:0
+#define NVC37E_SET_KEY_GREEN_Y_MAX                                              31:16
+#define NVC37E_SET_KEY_BLUE_CB                                                  (0x00000304)
+#define NVC37E_SET_KEY_BLUE_CB_MIN                                              15:0
+#define NVC37E_SET_KEY_BLUE_CB_MAX                                              31:16
+#define NVC37E_SET_PRESENT_CONTROL                                              (0x00000308)
+#define NVC37E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL                         3:0
+#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE                                   6:4
+#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING                       (0x00000000)
+#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE                         (0x00000001)
+#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE                               8:8
+#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE                       (0x00000000)
+#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE                        (0x00000001)
+#define NVC37E_SET_TIMESTAMP_ORIGIN_LO                                          (0x00000340)
+#define NVC37E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO                             31:0
+#define NVC37E_SET_TIMESTAMP_ORIGIN_HI                                          (0x00000344)
+#define NVC37E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI                             31:0
+#define NVC37E_SET_UPDATE_TIMESTAMP_LO                                          (0x00000348)
+#define NVC37E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO                             31:0
+#define NVC37E_SET_UPDATE_TIMESTAMP_HI                                          (0x0000034C)
+#define NVC37E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI                             31:0
+#define NVC37E_SET_INTERLOCK_FLAGS                                              (0x00000370)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE                          0:0
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE                  (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE                   (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i)                     ((i)+1):((i)+1)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1                8
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE                (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE                 (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0                       1:1
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE                (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1                       2:2
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE                (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2                       3:3
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE                (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3                       4:4
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE                (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4                       5:5
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE                (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5                       6:6
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE                (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6                       7:7
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE                (0x00000001)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7                       8:8
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE               (0x00000000)
+#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE                (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS                                       (0x00000374)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i)              ((i)+0):((i)+0)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1         32
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE         (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE          (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0                0:0
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1                1:1
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2                2:2
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3                3:3
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4                4:4
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5                5:5
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6                6:6
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7                7:7
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8                8:8
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9                9:9
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE        (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE         (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10               10:10
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11               11:11
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12               12:12
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13               13:13
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14               14:14
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15               15:15
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16               16:16
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17               17:17
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18               18:18
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19               19:19
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20               20:20
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21               21:21
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22               22:22
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23               23:23
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24               24:24
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25               25:25
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26               26:26
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27               27:27
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28               28:28
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29               29:29
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30               30:30
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE        (0x00000001)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31               31:31
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE       (0x00000000)
+#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE        (0x00000001)
+
+#ifdef __cplusplus
+};     /* extern "C" */
+#endif
+#endif // _clC37e_h
diff --git a/classes/display/index.html b/classes/display/index.html
new file mode 100644
index 0000000..56c6e29
--- /dev/null
+++ b/classes/display/index.html
@@ -0,0 +1,46 @@
+<html>
+    <head><title>display</title></head>
+    <body>
+        <h1>display</h1>
+        <a href="README.txt">README.txt</a><br/>
+        <a href="cl507a.h">cl507a.h</a><br/>
+        <a href="cl507b.h">cl507b.h</a><br/>
+        <a href="cl507c.h">cl507c.h</a><br/>
+        <a href="cl507d.h">cl507d.h</a><br/>
+        <a href="cl507e.h">cl507e.h</a><br/>
+        <a href="cl827a.h">cl827a.h</a><br/>
+        <a href="cl827b.h">cl827b.h</a><br/>
+        <a href="cl827c.h">cl827c.h</a><br/>
+        <a href="cl827d.h">cl827d.h</a><br/>
+        <a href="cl827e.h">cl827e.h</a><br/>
+        <a href="cl837c.h">cl837c.h</a><br/>
+        <a href="cl837d.h">cl837d.h</a><br/>
+        <a href="cl837e.h">cl837e.h</a><br/>
+        <a href="cl857a.h">cl857a.h</a><br/>
+        <a href="cl857b.h">cl857b.h</a><br/>
+        <a href="cl857c.h">cl857c.h</a><br/>
+        <a href="cl857d.h">cl857d.h</a><br/>
+        <a href="cl857e.h">cl857e.h</a><br/>
+        <a href="cl887d.h">cl887d.h</a><br/>
+        <a href="cl907a.h">cl907a.h</a><br/>
+        <a href="cl907b.h">cl907b.h</a><br/>
+        <a href="cl907c.h">cl907c.h</a><br/>
+        <a href="cl907d.h">cl907d.h</a><br/>
+        <a href="cl907e.h">cl907e.h</a><br/>
+        <a href="cl917a.h">cl917a.h</a><br/>
+        <a href="cl917b.h">cl917b.h</a><br/>
+        <a href="cl917c.h">cl917c.h</a><br/>
+        <a href="cl917d.h">cl917d.h</a><br/>
+        <a href="cl917e.h">cl917e.h</a><br/>
+        <a href="cl927c.h">cl927c.h</a><br/>
+        <a href="cl927d.h">cl927d.h</a><br/>
+        <a href="cl947d.h">cl947d.h</a><br/>
+        <a href="cl957d.h">cl957d.h</a><br/>
+        <a href="cl977d.h">cl977d.h</a><br/>
+        <a href="cl987d.h">cl987d.h</a><br/>
+        <a href="clc37a.h">clc37a.h</a><br/>
+        <a href="clc37b.h">clc37b.h</a><br/>
+        <a href="clc37d.h">clc37d.h</a><br/>
+        <a href="clc37e.h">clc37e.h</a><br/>
+    </body>
+</html>
diff --git a/classes/index.html b/classes/index.html
new file mode 100644
index 0000000..7766646
--- /dev/null
+++ b/classes/index.html
@@ -0,0 +1,8 @@
+<html>
+    <head><title>classes</title></head>
+    <body>
+        <h1>classes</h1>
+        <a href="compute">compute</a><br/>
+        <a href="display">display</a><br/>
+    </body>
+</html>
diff --git a/index.html b/index.html
index cc09589..dead71e 100644
--- a/index.html
+++ b/index.html
@@ -3,16 +3,15 @@
     <body>
         <h1>open-gpu-doc</h1>
         <a href="BIOS-Information-Table">BIOS-Information-Table</a><br/>
-        <a href="Compute-Class-Methods">Compute-Class-Methods</a><br/>
         <a href="Compute-QMD">Compute-QMD</a><br/>
         <a href="DCB">DCB</a><br/>
         <a href="Devinit">Devinit</a><br/>
-        <a href="Display-Class-Methods">Display-Class-Methods</a><br/>
         <a href="Falcon-Security">Falcon-Security</a><br/>
         <a href="MemoryClockTable">MemoryClockTable</a><br/>
         <a href="MemoryTweakTable">MemoryTweakTable</a><br/>
         <a href="README.md">README.md</a><br/>
         <a href="Shader-Program-Header">Shader-Program-Header</a><br/>
+        <a href="classes">classes</a><br/>
         <a href="gk104-disable-graphics-power-gating">gk104-disable-graphics-power-gating</a><br/>
         <a href="gk104-disable-underflow-reporting">gk104-disable-underflow-reporting</a><br/>
         <a href="manuals">manuals</a><br/>
-- 
cgit v1.2.3