From 4de9b1af2ebcf610d8201af4ad07f7f2fb83b0f8 Mon Sep 17 00:00:00 2001 From: John Hubbard Date: Sun, 16 Jun 2019 19:17:18 -0700 Subject: Move QMD files into classes/compute directory The QMD files really are just class files. Reviewed by: Maneet Singh --- Compute-QMD/clc3c0qmd.h | 245 ---------------- Compute-QMD/clc5c0qmd.h | 247 ---------------- Compute-QMD/index.html | 8 - classes/compute/cla0c0qmd.h | 660 +++++++++++++++++++++++++++++++++++++++++++ classes/compute/cla1c0qmd.h | 451 ++++++++++++++++++++++++++++++ classes/compute/clb0c0qmd.h | 454 ++++++++++++++++++++++++++++++ classes/compute/clb1c0qmd.h | 454 ++++++++++++++++++++++++++++++ classes/compute/clc0c0qmd.h | 665 ++++++++++++++++++++++++++++++++++++++++++++ classes/compute/clc1c0qmd.h | 665 ++++++++++++++++++++++++++++++++++++++++++++ classes/compute/clc3c0qmd.h | 245 ++++++++++++++++ classes/compute/clc5c0qmd.h | 247 ++++++++++++++++ classes/compute/index.html | 8 + index.html | 2 - qmd/cla0c0qmd.h | 660 ------------------------------------------- qmd/cla1c0qmd.h | 451 ------------------------------ qmd/clb0c0qmd.h | 454 ------------------------------ qmd/clb1c0qmd.h | 454 ------------------------------ qmd/clc0c0qmd.h | 665 -------------------------------------------- qmd/clc1c0qmd.h | 665 -------------------------------------------- qmd/index.html | 12 - 20 files changed, 3849 insertions(+), 3863 deletions(-) delete mode 100644 Compute-QMD/clc3c0qmd.h delete mode 100644 Compute-QMD/clc5c0qmd.h delete mode 100644 Compute-QMD/index.html create mode 100644 classes/compute/cla0c0qmd.h create mode 100644 classes/compute/cla1c0qmd.h create mode 100644 classes/compute/clb0c0qmd.h create mode 100644 classes/compute/clb1c0qmd.h create mode 100644 classes/compute/clc0c0qmd.h create mode 100644 classes/compute/clc1c0qmd.h create mode 100644 classes/compute/clc3c0qmd.h create mode 100644 classes/compute/clc5c0qmd.h delete mode 100644 qmd/cla0c0qmd.h delete mode 100644 qmd/cla1c0qmd.h delete mode 100644 qmd/clb0c0qmd.h delete mode 100644 qmd/clb1c0qmd.h delete mode 100644 qmd/clc0c0qmd.h delete mode 100644 qmd/clc1c0qmd.h delete mode 100644 qmd/index.html diff --git a/Compute-QMD/clc3c0qmd.h b/Compute-QMD/clc3c0qmd.h deleted file mode 100644 index 588cc63..0000000 --- a/Compute-QMD/clc3c0qmd.h +++ /dev/null @@ -1,245 +0,0 @@ -/******************************************************************************* - Copyright (c) 2001-2010 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLC3C0QMD_H__ -#define __CLC3C0QMD_H__ - -/* -** Queue Meta Data, Version 02_02 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVC3C0_QMDV02_02_OUTER_PUT MW(30:0) -#define NVC3C0_QMDV02_02_OUTER_OVERFLOW MW(31:31) -#define NVC3C0_QMDV02_02_OUTER_GET MW(62:32) -#define NVC3C0_QMDV02_02_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC3C0_QMDV02_02_INNER_GET MW(94:64) -#define NVC3C0_QMDV02_02_INNER_OVERFLOW MW(95:95) -#define NVC3C0_QMDV02_02_INNER_PUT MW(126:96) -#define NVC3C0_QMDV02_02_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC3C0_QMDV02_02_QMD_GROUP_ID MW(133:128) -#define NVC3C0_QMDV02_02_SM_GLOBAL_CACHING_ENABLE MW(134:134) -#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) -#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_IS_QUEUE MW(136:136) -#define NVC3C0_QMDV02_02_IS_QUEUE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_IS_QUEUE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) -#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) -#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) -#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS MW(140:140) -#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE MW(142:142) -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY MW(143:143) -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_QMD_RESERVED_B MW(159:144) -#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVC3C0_QMDV02_02_QMD_RESERVED_C MW(185:185) -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE MW(189:189) -#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE MW(190:190) -#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) -#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH_RESUME MW(223:192) -#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT_RESUME MW(239:224) -#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH_RESUME MW(255:240) -#define NVC3C0_QMDV02_02_PROGRAM_OFFSET MW(287:256) -#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC3C0_QMDV02_02_QMD_RESERVED_D MW(335:328) -#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE MW(369:368) -#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC3C0_QMDV02_02_SAMPLER_INDEX MW(382:382) -#define NVC3C0_QMDV02_02_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC3C0_QMDV02_02_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH MW(415:384) -#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT MW(431:416) -#define NVC3C0_QMDV02_02_QMD_RESERVED13A MW(447:432) -#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH MW(463:448) -#define NVC3C0_QMDV02_02_QMD_RESERVED14A MW(479:464) -#define NVC3C0_QMDV02_02_DEPENDENT_QMD_POINTER MW(511:480) -#define NVC3C0_QMDV02_02_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVC3C0_QMDV02_02_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC3C0_QMDV02_02_SHARED_MEMORY_SIZE MW(561:544) -#define NVC3C0_QMDV02_02_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) -#define NVC3C0_QMDV02_02_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) -#define NVC3C0_QMDV02_02_QMD_VERSION MW(579:576) -#define NVC3C0_QMDV02_02_QMD_MAJOR_VERSION MW(583:580) -#define NVC3C0_QMDV02_02_QMD_RESERVED_H MW(591:584) -#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_REGISTER_COUNT_V MW(656:648) -#define NVC3C0_QMDV02_02_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) -#define NVC3C0_QMDV02_02_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) -#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC3C0_QMDV02_02_QMD_RESERVED_J MW(783:776) -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC3C0_QMDV02_02_QMD_RESERVED_K MW(791:791) -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE0_PAYLOAD MW(831:800) -#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC3C0_QMDV02_02_QMD_RESERVED_L MW(879:872) -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC3C0_QMDV02_02_QMD_RESERVED_M MW(887:887) -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC3C0_QMDV02_02_RELEASE1_PAYLOAD MW(927:896) -#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC3C0_QMDV02_02_QMD_RESERVED_N MW(954:952) -#define NVC3C0_QMDV02_02_BARRIER_COUNT MW(959:955) -#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC3C0_QMDV02_02_REGISTER_COUNT MW(991:984) -#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) -#define NVC3C0_QMDV02_02_SASS_VERSION MW(1023:1016) -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_LOWER MW(1567:1536) -#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_UPPER MW(1584:1568) -#define NVC3C0_QMDV02_02_QMD_RESERVED_S MW(1599:1585) -#define NVC3C0_QMDV02_02_HW_ONLY_INNER_GET MW(1630:1600) -#define NVC3C0_QMDV02_02_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) -#define NVC3C0_QMDV02_02_HW_ONLY_INNER_PUT MW(1662:1632) -#define NVC3C0_QMDV02_02_HW_ONLY_SCG_TYPE MW(1663:1663) -#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) -#define NVC3C0_QMDV02_02_QMD_RESERVED_Q MW(1694:1694) -#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) -#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC3C0_QMDV02_02_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) -#define NVC3C0_QMDV02_02_QMD_SPARE_G MW(1759:1728) -#define NVC3C0_QMDV02_02_QMD_SPARE_H MW(1791:1760) -#define NVC3C0_QMDV02_02_QMD_SPARE_I MW(1823:1792) -#define NVC3C0_QMDV02_02_QMD_SPARE_J MW(1855:1824) -#define NVC3C0_QMDV02_02_QMD_SPARE_K MW(1887:1856) -#define NVC3C0_QMDV02_02_QMD_SPARE_L MW(1919:1888) -#define NVC3C0_QMDV02_02_QMD_SPARE_M MW(1951:1920) -#define NVC3C0_QMDV02_02_QMD_SPARE_N MW(1983:1952) -#define NVC3C0_QMDV02_02_DEBUG_ID_UPPER MW(2015:1984) -#define NVC3C0_QMDV02_02_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLC3C0QMD_H__ diff --git a/Compute-QMD/clc5c0qmd.h b/Compute-QMD/clc5c0qmd.h deleted file mode 100644 index 180a491..0000000 --- a/Compute-QMD/clc5c0qmd.h +++ /dev/null @@ -1,247 +0,0 @@ -/******************************************************************************* - Copyright (c) 2001-2010 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLC5C0QMD_H__ -#define __CLC5C0QMD_H__ - -/* -** Queue Meta Data, Version 02_03 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVC5C0_QMDV02_03_OUTER_PUT MW(30:0) -#define NVC5C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) -#define NVC5C0_QMDV02_03_OUTER_GET MW(62:32) -#define NVC5C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC5C0_QMDV02_03_INNER_GET MW(94:64) -#define NVC5C0_QMDV02_03_INNER_OVERFLOW MW(95:95) -#define NVC5C0_QMDV02_03_INNER_PUT MW(126:96) -#define NVC5C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC5C0_QMDV02_03_QMD_GROUP_ID MW(133:128) -#define NVC5C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) -#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) -#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_IS_QUEUE MW(136:136) -#define NVC5C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) -#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) -#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) -#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) -#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_QMD_RESERVED_B MW(159:144) -#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVC5C0_QMDV02_03_QMD_RESERVED_C MW(185:185) -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) -#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) -#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) -#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) -#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) -#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) -#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) -#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC5C0_QMDV02_03_QMD_RESERVED_D MW(335:328) -#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) -#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC5C0_QMDV02_03_SAMPLER_INDEX MW(382:382) -#define NVC5C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC5C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) -#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) -#define NVC5C0_QMDV02_03_QMD_RESERVED13A MW(447:432) -#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) -#define NVC5C0_QMDV02_03_QMD_RESERVED14A MW(479:464) -#define NVC5C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) -#define NVC5C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC5C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) -#define NVC5C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) -#define NVC5C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) -#define NVC5C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) -#define NVC5C0_QMDV02_03_QMD_VERSION MW(579:576) -#define NVC5C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) -#define NVC5C0_QMDV02_03_QMD_RESERVED_H MW(591:584) -#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) -#define NVC5C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) -#define NVC5C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) -#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC5C0_QMDV02_03_QMD_RESERVED_J MW(783:776) -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC5C0_QMDV02_03_QMD_RESERVED_K MW(791:791) -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) -#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC5C0_QMDV02_03_QMD_RESERVED_L MW(879:872) -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC5C0_QMDV02_03_QMD_RESERVED_M MW(887:887) -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC5C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) -#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC5C0_QMDV02_03_QMD_RESERVED_N MW(954:952) -#define NVC5C0_QMDV02_03_BARRIER_COUNT MW(959:955) -#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC5C0_QMDV02_03_REGISTER_COUNT MW(991:984) -#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) -#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) -#define NVC5C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) -#define NVC5C0_QMDV02_03_SASS_VERSION MW(1023:1016) -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) -#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) -#define NVC5C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) -#define NVC5C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) -#define NVC5C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) -#define NVC5C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) -#define NVC5C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) -#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) -#define NVC5C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) -#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) -#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC5C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) -#define NVC5C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) -#define NVC5C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) -#define NVC5C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) -#define NVC5C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) -#define NVC5C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) -#define NVC5C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) -#define NVC5C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) -#define NVC5C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) -#define NVC5C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) -#define NVC5C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLC5C0QMD_H__ diff --git a/Compute-QMD/index.html b/Compute-QMD/index.html deleted file mode 100644 index 0b2e9d3..0000000 --- a/Compute-QMD/index.html +++ /dev/null @@ -1,8 +0,0 @@ - - Compute-QMD - -

Compute-QMD

- clc3c0qmd.h
- clc5c0qmd.h
- - diff --git a/classes/compute/cla0c0qmd.h b/classes/compute/cla0c0qmd.h new file mode 100644 index 0000000..c0829f1 --- /dev/null +++ b/classes/compute/cla0c0qmd.h @@ -0,0 +1,660 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLA0C0QMD_H__ +#define __CLA0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_06 + */ + +#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_06_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512) +#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599) +#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600) +#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607) +#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610) +#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618) +#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA0C0QMD_H__ diff --git a/classes/compute/cla1c0qmd.h b/classes/compute/cla1c0qmd.h new file mode 100644 index 0000000..b322988 --- /dev/null +++ b/classes/compute/cla1c0qmd.h @@ -0,0 +1,451 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLA1C0QMD_H__ +#define __CLA1C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA1C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA1C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA1C0_QMDV01_07_QMD_RESERVED_A MW(199:198) +#define NVA1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVA1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA1C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA1C0QMD_H__ diff --git a/classes/compute/clb0c0qmd.h b/classes/compute/clb0c0qmd.h new file mode 100644 index 0000000..c68e893 --- /dev/null +++ b/classes/compute/clb0c0qmd.h @@ -0,0 +1,454 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB0C0QMD_H__ +#define __CLB0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVB0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVB0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVB0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVB0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVB0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVB0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVB0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVB0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVB0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVB0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVB0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVB0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVB0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVB0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVB0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVB0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVB0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVB0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVB0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVB0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVB0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVB0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVB0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVB0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVB0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVB0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVB0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVB0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVB0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVB0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVB0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVB0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVB0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVB0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVB0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVB0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVB0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVB0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVB0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVB0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVB0C0_QMDV01_07_QMD_RESERVED_A MW(198:198) +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVB0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVB0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVB0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVB0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVB0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVB0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVB0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVB0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVB0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVB0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVB0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVB0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVB0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVB0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVB0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVB0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVB0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVB0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVB0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVB0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVB0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVB0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVB0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVB0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVB0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVB0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVB0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVB0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVB0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVB0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLB0C0QMD_H__ diff --git a/classes/compute/clb1c0qmd.h b/classes/compute/clb1c0qmd.h new file mode 100644 index 0000000..ca98206 --- /dev/null +++ b/classes/compute/clb1c0qmd.h @@ -0,0 +1,454 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB1C0QMD_H__ +#define __CLB1C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVB1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVB1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVB1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVB1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVB1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_THROTTLED MW(372:372) +#define NVB1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVB1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVB1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVB1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVB1C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVB1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVB1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVB1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVB1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB1C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVB1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVB1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVB1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVB1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVB1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVB1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVB1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVB1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVB1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVB1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVB1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVB1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVB1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVB1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVB1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVB1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVB1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVB1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVB1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVB1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVB1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVB1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVB1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVB1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVB1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVB1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVB1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVB1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVB1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVB1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVB1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVB1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVB1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVB1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVB1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVB1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVB1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVB1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVB1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVB1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVB1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVB1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVB1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVB1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVB1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVB1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVB1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVB1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVB1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVB1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVB1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVB1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVB1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVB1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVB1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVB1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVB1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLB1C0QMD_H__ diff --git a/classes/compute/clc0c0qmd.h b/classes/compute/clc0c0qmd.h new file mode 100644 index 0000000..040bdcd --- /dev/null +++ b/classes/compute/clc0c0qmd.h @@ -0,0 +1,665 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC0C0QMD_H__ +#define __CLC0C0QMD_H__ + +/* +** Queue Meta Data, Version 01_07 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVC0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVC0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVC0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVC0C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVC0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVC0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVC0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVC0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVC0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVC0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVC0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVC0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVC0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVC0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC0C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVC0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVC0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_00 + */ + +#define NVC0C0_QMDV02_00_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV02_00_OUTER_GET MW(62:32) +#define NVC0C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV02_00_INNER_GET MW(94:64) +#define NVC0C0_QMDV02_00_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV02_00_INNER_PUT MW(126:96) +#define NVC0C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC0C0_QMDV02_00_QMD_GROUP_ID MW(197:192) +#define NVC0C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_IS_QUEUE MW(200:200) +#define NVC0C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_QMD_RESERVED_B MW(223:208) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC0C0_QMDV02_00_QMD_RESERVED_C MW(249:249) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV02_00_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_THROTTLED MW(372:372) +#define NVC0C0_QMDV02_00_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV02_00_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV02_00_QMD_RESERVED13A MW(447:432) +#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC0C0_QMDV02_00_QMD_RESERVED14A MW(479:464) +#define NVC0C0_QMDV02_00_QMD_RESERVED15A MW(511:480) +#define NVC0C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV02_00_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV02_00_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV02_00_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_QMD_RESERVED_I MW(671:648) +#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV02_00_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_00_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV02_00_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_00_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC0C0_QMDV02_00_QMD_RESERVED_N MW(954:952) +#define NVC0C0_QMDV02_00_BARRIER_COUNT MW(959:955) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC0C0_QMDV02_00_REGISTER_COUNT MW(991:984) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC0C0_QMDV02_00_SASS_VERSION MW(1023:1016) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC0C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC0C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC0C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC0C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC0C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) +#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) +#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) +#define NVC0C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_01 + */ + +#define NVC0C0_QMDV02_01_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV02_01_OUTER_GET MW(62:32) +#define NVC0C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV02_01_INNER_GET MW(94:64) +#define NVC0C0_QMDV02_01_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV02_01_INNER_PUT MW(126:96) +#define NVC0C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV02_01_QMD_GROUP_ID MW(133:128) +#define NVC0C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_IS_QUEUE MW(136:136) +#define NVC0C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_QMD_RESERVED_B MW(159:144) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC0C0_QMDV02_01_QMD_RESERVED_C MW(185:185) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC0C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV02_01_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_THROTTLED MW(372:372) +#define NVC0C0_QMDV02_01_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV02_01_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV02_01_QMD_RESERVED13A MW(447:432) +#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) +#define NVC0C0_QMDV02_01_QMD_RESERVED14A MW(479:464) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC0C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV02_01_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV02_01_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV02_01_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_QMD_RESERVED_I MW(671:648) +#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV02_01_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_01_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV02_01_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_01_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC0C0_QMDV02_01_QMD_RESERVED_N MW(954:952) +#define NVC0C0_QMDV02_01_BARRIER_COUNT MW(959:955) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC0C0_QMDV02_01_REGISTER_COUNT MW(991:984) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC0C0_QMDV02_01_SASS_VERSION MW(1023:1016) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC0C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) +#define NVC0C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) +#define NVC0C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC0C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC0C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC0C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC0C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC0C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC0C0QMD_H__ diff --git a/classes/compute/clc1c0qmd.h b/classes/compute/clc1c0qmd.h new file mode 100644 index 0000000..41f68a4 --- /dev/null +++ b/classes/compute/clc1c0qmd.h @@ -0,0 +1,665 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC1C0QMD_H__ +#define __CLC1C0QMD_H__ + +/* +** Queue Meta Data, Version 01_07 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVC1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVC1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVC1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVC1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVC1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVC1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVC1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVC1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVC1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVC1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVC1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVC1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVC1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVC1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVC1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVC1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_00 + */ + +#define NVC1C0_QMDV02_00_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV02_00_OUTER_GET MW(62:32) +#define NVC1C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV02_00_INNER_GET MW(94:64) +#define NVC1C0_QMDV02_00_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV02_00_INNER_PUT MW(126:96) +#define NVC1C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC1C0_QMDV02_00_QMD_GROUP_ID MW(197:192) +#define NVC1C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_IS_QUEUE MW(200:200) +#define NVC1C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_QMD_RESERVED_B MW(223:208) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC1C0_QMDV02_00_QMD_RESERVED_C MW(249:249) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV02_00_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_THROTTLED MW(372:372) +#define NVC1C0_QMDV02_00_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV02_00_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV02_00_QMD_RESERVED13A MW(447:432) +#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC1C0_QMDV02_00_QMD_RESERVED14A MW(479:464) +#define NVC1C0_QMDV02_00_QMD_RESERVED15A MW(511:480) +#define NVC1C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV02_00_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV02_00_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV02_00_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_QMD_RESERVED_I MW(671:648) +#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV02_00_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_00_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV02_00_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_00_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC1C0_QMDV02_00_QMD_RESERVED_N MW(954:952) +#define NVC1C0_QMDV02_00_BARRIER_COUNT MW(959:955) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC1C0_QMDV02_00_REGISTER_COUNT MW(991:984) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC1C0_QMDV02_00_SASS_VERSION MW(1023:1016) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC1C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC1C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC1C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC1C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC1C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) +#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) +#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) +#define NVC1C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_01 + */ + +#define NVC1C0_QMDV02_01_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV02_01_OUTER_GET MW(62:32) +#define NVC1C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV02_01_INNER_GET MW(94:64) +#define NVC1C0_QMDV02_01_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV02_01_INNER_PUT MW(126:96) +#define NVC1C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV02_01_QMD_GROUP_ID MW(133:128) +#define NVC1C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_IS_QUEUE MW(136:136) +#define NVC1C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_QMD_RESERVED_B MW(159:144) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC1C0_QMDV02_01_QMD_RESERVED_C MW(185:185) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC1C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV02_01_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_THROTTLED MW(372:372) +#define NVC1C0_QMDV02_01_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV02_01_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV02_01_QMD_RESERVED13A MW(447:432) +#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) +#define NVC1C0_QMDV02_01_QMD_RESERVED14A MW(479:464) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC1C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV02_01_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV02_01_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV02_01_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_QMD_RESERVED_I MW(671:648) +#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV02_01_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_01_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV02_01_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_01_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC1C0_QMDV02_01_QMD_RESERVED_N MW(954:952) +#define NVC1C0_QMDV02_01_BARRIER_COUNT MW(959:955) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC1C0_QMDV02_01_REGISTER_COUNT MW(991:984) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC1C0_QMDV02_01_SASS_VERSION MW(1023:1016) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC1C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) +#define NVC1C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) +#define NVC1C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC1C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC1C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC1C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC1C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC1C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC1C0QMD_H__ diff --git a/classes/compute/clc3c0qmd.h b/classes/compute/clc3c0qmd.h new file mode 100644 index 0000000..588cc63 --- /dev/null +++ b/classes/compute/clc3c0qmd.h @@ -0,0 +1,245 @@ +/******************************************************************************* + Copyright (c) 2001-2010 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC3C0QMD_H__ +#define __CLC3C0QMD_H__ + +/* +** Queue Meta Data, Version 02_02 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC3C0_QMDV02_02_OUTER_PUT MW(30:0) +#define NVC3C0_QMDV02_02_OUTER_OVERFLOW MW(31:31) +#define NVC3C0_QMDV02_02_OUTER_GET MW(62:32) +#define NVC3C0_QMDV02_02_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC3C0_QMDV02_02_INNER_GET MW(94:64) +#define NVC3C0_QMDV02_02_INNER_OVERFLOW MW(95:95) +#define NVC3C0_QMDV02_02_INNER_PUT MW(126:96) +#define NVC3C0_QMDV02_02_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC3C0_QMDV02_02_QMD_GROUP_ID MW(133:128) +#define NVC3C0_QMDV02_02_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_IS_QUEUE MW(136:136) +#define NVC3C0_QMDV02_02_IS_QUEUE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_IS_QUEUE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_QMD_RESERVED_B MW(159:144) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC3C0_QMDV02_02_QMD_RESERVED_C MW(185:185) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC3C0_QMDV02_02_PROGRAM_OFFSET MW(287:256) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC3C0_QMDV02_02_QMD_RESERVED_D MW(335:328) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE MW(369:368) +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC3C0_QMDV02_02_SAMPLER_INDEX MW(382:382) +#define NVC3C0_QMDV02_02_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC3C0_QMDV02_02_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH MW(415:384) +#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT MW(431:416) +#define NVC3C0_QMDV02_02_QMD_RESERVED13A MW(447:432) +#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH MW(463:448) +#define NVC3C0_QMDV02_02_QMD_RESERVED14A MW(479:464) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC3C0_QMDV02_02_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC3C0_QMDV02_02_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC3C0_QMDV02_02_SHARED_MEMORY_SIZE MW(561:544) +#define NVC3C0_QMDV02_02_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC3C0_QMDV02_02_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC3C0_QMDV02_02_QMD_VERSION MW(579:576) +#define NVC3C0_QMDV02_02_QMD_MAJOR_VERSION MW(583:580) +#define NVC3C0_QMDV02_02_QMD_RESERVED_H MW(591:584) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_REGISTER_COUNT_V MW(656:648) +#define NVC3C0_QMDV02_02_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC3C0_QMDV02_02_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC3C0_QMDV02_02_QMD_RESERVED_J MW(783:776) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_QMDV02_02_QMD_RESERVED_K MW(791:791) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_PAYLOAD MW(831:800) +#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC3C0_QMDV02_02_QMD_RESERVED_L MW(879:872) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_QMDV02_02_QMD_RESERVED_M MW(887:887) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_PAYLOAD MW(927:896) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC3C0_QMDV02_02_QMD_RESERVED_N MW(954:952) +#define NVC3C0_QMDV02_02_BARRIER_COUNT MW(959:955) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC3C0_QMDV02_02_REGISTER_COUNT MW(991:984) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC3C0_QMDV02_02_SASS_VERSION MW(1023:1016) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC3C0_QMDV02_02_QMD_RESERVED_S MW(1599:1585) +#define NVC3C0_QMDV02_02_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC3C0_QMDV02_02_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC3C0_QMDV02_02_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC3C0_QMDV02_02_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC3C0_QMDV02_02_QMD_RESERVED_Q MW(1694:1694) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC3C0_QMDV02_02_QMD_SPARE_G MW(1759:1728) +#define NVC3C0_QMDV02_02_QMD_SPARE_H MW(1791:1760) +#define NVC3C0_QMDV02_02_QMD_SPARE_I MW(1823:1792) +#define NVC3C0_QMDV02_02_QMD_SPARE_J MW(1855:1824) +#define NVC3C0_QMDV02_02_QMD_SPARE_K MW(1887:1856) +#define NVC3C0_QMDV02_02_QMD_SPARE_L MW(1919:1888) +#define NVC3C0_QMDV02_02_QMD_SPARE_M MW(1951:1920) +#define NVC3C0_QMDV02_02_QMD_SPARE_N MW(1983:1952) +#define NVC3C0_QMDV02_02_DEBUG_ID_UPPER MW(2015:1984) +#define NVC3C0_QMDV02_02_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC3C0QMD_H__ diff --git a/classes/compute/clc5c0qmd.h b/classes/compute/clc5c0qmd.h new file mode 100644 index 0000000..180a491 --- /dev/null +++ b/classes/compute/clc5c0qmd.h @@ -0,0 +1,247 @@ +/******************************************************************************* + Copyright (c) 2001-2010 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC5C0QMD_H__ +#define __CLC5C0QMD_H__ + +/* +** Queue Meta Data, Version 02_03 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC5C0_QMDV02_03_OUTER_PUT MW(30:0) +#define NVC5C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) +#define NVC5C0_QMDV02_03_OUTER_GET MW(62:32) +#define NVC5C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC5C0_QMDV02_03_INNER_GET MW(94:64) +#define NVC5C0_QMDV02_03_INNER_OVERFLOW MW(95:95) +#define NVC5C0_QMDV02_03_INNER_PUT MW(126:96) +#define NVC5C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC5C0_QMDV02_03_QMD_GROUP_ID MW(133:128) +#define NVC5C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_IS_QUEUE MW(136:136) +#define NVC5C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_QMD_RESERVED_B MW(159:144) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC5C0_QMDV02_03_QMD_RESERVED_C MW(185:185) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC5C0_QMDV02_03_QMD_RESERVED_D MW(335:328) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC5C0_QMDV02_03_SAMPLER_INDEX MW(382:382) +#define NVC5C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC5C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) +#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) +#define NVC5C0_QMDV02_03_QMD_RESERVED13A MW(447:432) +#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) +#define NVC5C0_QMDV02_03_QMD_RESERVED14A MW(479:464) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC5C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC5C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC5C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) +#define NVC5C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC5C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC5C0_QMDV02_03_QMD_VERSION MW(579:576) +#define NVC5C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) +#define NVC5C0_QMDV02_03_QMD_RESERVED_H MW(591:584) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) +#define NVC5C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC5C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC5C0_QMDV02_03_QMD_RESERVED_J MW(783:776) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_QMDV02_03_QMD_RESERVED_K MW(791:791) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) +#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC5C0_QMDV02_03_QMD_RESERVED_L MW(879:872) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_QMDV02_03_QMD_RESERVED_M MW(887:887) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) +#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC5C0_QMDV02_03_QMD_RESERVED_N MW(954:952) +#define NVC5C0_QMDV02_03_BARRIER_COUNT MW(959:955) +#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC5C0_QMDV02_03_REGISTER_COUNT MW(991:984) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) +#define NVC5C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) +#define NVC5C0_QMDV02_03_SASS_VERSION MW(1023:1016) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC5C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) +#define NVC5C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC5C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC5C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC5C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC5C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC5C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) +#define NVC5C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) +#define NVC5C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) +#define NVC5C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) +#define NVC5C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) +#define NVC5C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) +#define NVC5C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) +#define NVC5C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) +#define NVC5C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) +#define NVC5C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC5C0QMD_H__ diff --git a/classes/compute/index.html b/classes/compute/index.html index 19aa93f..e1310fa 100644 --- a/classes/compute/index.html +++ b/classes/compute/index.html @@ -7,12 +7,20 @@ cl90c0.h
cl91c0.h
cla0c0.h
+ cla0c0qmd.h
cla1c0.h
+ cla1c0qmd.h
clb0c0.h
+ clb0c0qmd.h
clb1c0.h
+ clb1c0qmd.h
clc0c0.h
+ clc0c0qmd.h
clc1c0.h
+ clc1c0qmd.h
clc3c0.h
+ clc3c0qmd.h
clc5c0.h
+ clc5c0qmd.h
diff --git a/index.html b/index.html index dead71e..a59e59f 100644 --- a/index.html +++ b/index.html @@ -3,7 +3,6 @@

open-gpu-doc

BIOS-Information-Table
- Compute-QMD
DCB
Devinit
Falcon-Security
@@ -16,7 +15,6 @@ gk104-disable-underflow-reporting
manuals
pascal
- qmd
virtual-p-state-table
diff --git a/qmd/cla0c0qmd.h b/qmd/cla0c0qmd.h deleted file mode 100644 index c0829f1..0000000 --- a/qmd/cla0c0qmd.h +++ /dev/null @@ -1,660 +0,0 @@ -/******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLA0C0QMD_H__ -#define __CLA0C0QMD_H__ - -/* -** Queue Meta Data, Version 00_06 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) -#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) -#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) -#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) -#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) -#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) -#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) -#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_THROTTLED MW(372:372) -#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) -#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) -#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) -#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) -#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) -#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) -#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) -#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) -#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) -#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) -#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576) -#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) -#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) -#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) -#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) -#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) -#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) -#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) -#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) -#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) -#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) -#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528) -#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) -#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) -#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) -#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) -#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) -#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) -#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) -#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) -#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) -#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) -#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) -#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) -#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) -#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) -#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) -#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 01_06 - */ - -#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0) -#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31) -#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32) -#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVA0C0_QMDV01_06_INNER_GET MW(94:64) -#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95) -#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96) -#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127) -#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128) -#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160) -#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192) -#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198) -#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200) -#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205) -#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208) -#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223) -#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249) -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256) -#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328) -#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368) -#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_THROTTLED MW(372:372) -#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376) -#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377) -#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 -#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382) -#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383) -#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 -#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 -#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384) -#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416) -#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432) -#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512) -#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536) -#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543) -#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544) -#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562) -#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576) -#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580) -#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584) -#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648) -#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669) -#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776) -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788) -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791) -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800) -#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872) -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884) -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887) -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896) -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464) -#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467) -#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496) -#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528) -#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536) -#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599) -#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600) -#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607) -#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610) -#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618) -#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632) -#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664) -#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696) -#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728) -#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760) -#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792) -#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824) -#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856) -#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888) -#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920) -#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952) -#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984) -#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 01_07 - */ - -#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0) -#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) -#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32) -#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVA0C0_QMDV01_07_INNER_GET MW(94:64) -#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) -#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96) -#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) -#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) -#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) -#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198) -#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) -#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) -#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) -#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) -#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_THROTTLED MW(372:372) -#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) -#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) -#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 -#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) -#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) -#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 -#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 -#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) -#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) -#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) -#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) -#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) -#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) -#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576) -#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) -#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) -#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) -#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) -#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) -#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) -#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) -#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) -#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528) -#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) -#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) -#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) -#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) -#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) -#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) -#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) -#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) -#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) -#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) -#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) -#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) -#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) -#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) -#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLA0C0QMD_H__ diff --git a/qmd/cla1c0qmd.h b/qmd/cla1c0qmd.h deleted file mode 100644 index b322988..0000000 --- a/qmd/cla1c0qmd.h +++ /dev/null @@ -1,451 +0,0 @@ -/******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLA1C0QMD_H__ -#define __CLA1C0QMD_H__ - -/* -** Queue Meta Data, Version 00_06 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) -#define NVA1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) -#define NVA1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) -#define NVA1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) -#define NVA1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) -#define NVA1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) -#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) -#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_THROTTLED MW(372:372) -#define NVA1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) -#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) -#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVA1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) -#define NVA1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVA1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVA1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) -#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) -#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) -#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) -#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) -#define NVA1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) -#define NVA1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) -#define NVA1C0_QMDV00_06_QMD_VERSION MW(579:576) -#define NVA1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) -#define NVA1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) -#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) -#define NVA1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) -#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) -#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) -#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVA1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) -#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVA1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVA1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) -#define NVA1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) -#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVA1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) -#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVA1C0_QMDV00_06_SASS_VERSION MW(1535:1528) -#define NVA1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) -#define NVA1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) -#define NVA1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) -#define NVA1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) -#define NVA1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) -#define NVA1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) -#define NVA1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) -#define NVA1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) -#define NVA1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) -#define NVA1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) -#define NVA1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) -#define NVA1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) -#define NVA1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) -#define NVA1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) -#define NVA1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) -#define NVA1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 01_07 - */ - -#define NVA1C0_QMDV01_07_OUTER_PUT MW(30:0) -#define NVA1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) -#define NVA1C0_QMDV01_07_OUTER_GET MW(62:32) -#define NVA1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVA1C0_QMDV01_07_INNER_GET MW(94:64) -#define NVA1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) -#define NVA1C0_QMDV01_07_INNER_PUT MW(126:96) -#define NVA1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) -#define NVA1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) -#define NVA1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) -#define NVA1C0_QMDV01_07_QMD_RESERVED_A MW(199:198) -#define NVA1C0_QMDV01_07_IS_QUEUE MW(200:200) -#define NVA1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) -#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVA1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) -#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVA1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) -#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) -#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_THROTTLED MW(372:372) -#define NVA1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) -#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) -#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 -#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVA1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) -#define NVA1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVA1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) -#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 -#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 -#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) -#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) -#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) -#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVA1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVA1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) -#define NVA1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) -#define NVA1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) -#define NVA1C0_QMDV01_07_QMD_VERSION MW(579:576) -#define NVA1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) -#define NVA1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) -#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) -#define NVA1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) -#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVA1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) -#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVA1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVA1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) -#define NVA1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) -#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVA1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) -#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVA1C0_QMDV01_07_SASS_VERSION MW(1535:1528) -#define NVA1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) -#define NVA1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVA1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVA1C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) -#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVA1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) -#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVA1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVA1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) -#define NVA1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) -#define NVA1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) -#define NVA1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) -#define NVA1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) -#define NVA1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) -#define NVA1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) -#define NVA1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) -#define NVA1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) -#define NVA1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) -#define NVA1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) -#define NVA1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLA1C0QMD_H__ diff --git a/qmd/clb0c0qmd.h b/qmd/clb0c0qmd.h deleted file mode 100644 index c68e893..0000000 --- a/qmd/clb0c0qmd.h +++ /dev/null @@ -1,454 +0,0 @@ -/******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLB0C0QMD_H__ -#define __CLB0C0QMD_H__ - -/* -** Queue Meta Data, Version 00_06 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) -#define NVB0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) -#define NVB0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) -#define NVB0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) -#define NVB0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) -#define NVB0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) -#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) -#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_THROTTLED MW(372:372) -#define NVB0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) -#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) -#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVB0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) -#define NVB0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVB0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVB0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) -#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) -#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) -#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) -#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) -#define NVB0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) -#define NVB0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) -#define NVB0C0_QMDV00_06_QMD_VERSION MW(579:576) -#define NVB0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) -#define NVB0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) -#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) -#define NVB0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) -#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) -#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) -#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVB0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) -#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVB0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVB0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) -#define NVB0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) -#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVB0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) -#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVB0C0_QMDV00_06_SASS_VERSION MW(1535:1528) -#define NVB0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) -#define NVB0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) -#define NVB0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) -#define NVB0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) -#define NVB0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) -#define NVB0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) -#define NVB0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) -#define NVB0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) -#define NVB0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) -#define NVB0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) -#define NVB0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) -#define NVB0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) -#define NVB0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) -#define NVB0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) -#define NVB0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) -#define NVB0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 01_07 - */ - -#define NVB0C0_QMDV01_07_OUTER_PUT MW(30:0) -#define NVB0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) -#define NVB0C0_QMDV01_07_OUTER_GET MW(62:32) -#define NVB0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVB0C0_QMDV01_07_INNER_GET MW(94:64) -#define NVB0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) -#define NVB0C0_QMDV01_07_INNER_PUT MW(126:96) -#define NVB0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) -#define NVB0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) -#define NVB0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) -#define NVB0C0_QMDV01_07_QMD_RESERVED_A MW(198:198) -#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) -#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_IS_QUEUE MW(200:200) -#define NVB0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) -#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVB0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) -#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVB0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) -#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) -#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_THROTTLED MW(372:372) -#define NVB0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) -#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) -#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 -#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVB0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) -#define NVB0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVB0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) -#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 -#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 -#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) -#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) -#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) -#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVB0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVB0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) -#define NVB0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) -#define NVB0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) -#define NVB0C0_QMDV01_07_QMD_VERSION MW(579:576) -#define NVB0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) -#define NVB0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) -#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) -#define NVB0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) -#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVB0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) -#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVB0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVB0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) -#define NVB0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) -#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVB0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) -#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVB0C0_QMDV01_07_SASS_VERSION MW(1535:1528) -#define NVB0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) -#define NVB0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVB0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVB0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) -#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVB0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) -#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVB0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVB0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) -#define NVB0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) -#define NVB0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) -#define NVB0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) -#define NVB0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) -#define NVB0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) -#define NVB0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) -#define NVB0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) -#define NVB0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) -#define NVB0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) -#define NVB0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) -#define NVB0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLB0C0QMD_H__ diff --git a/qmd/clb1c0qmd.h b/qmd/clb1c0qmd.h deleted file mode 100644 index ca98206..0000000 --- a/qmd/clb1c0qmd.h +++ /dev/null @@ -1,454 +0,0 @@ -/******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLB1C0QMD_H__ -#define __CLB1C0QMD_H__ - -/* -** Queue Meta Data, Version 00_06 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) -#define NVB1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) -#define NVB1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) -#define NVB1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) -#define NVB1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) -#define NVB1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) -#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) -#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_THROTTLED MW(372:372) -#define NVB1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) -#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) -#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVB1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) -#define NVB1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVB1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVB1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) -#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) -#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) -#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) -#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) -#define NVB1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) -#define NVB1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) -#define NVB1C0_QMDV00_06_QMD_VERSION MW(579:576) -#define NVB1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) -#define NVB1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) -#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) -#define NVB1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) -#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) -#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) -#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVB1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) -#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVB1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVB1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) -#define NVB1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) -#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVB1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) -#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVB1C0_QMDV00_06_SASS_VERSION MW(1535:1528) -#define NVB1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) -#define NVB1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) -#define NVB1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) -#define NVB1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) -#define NVB1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) -#define NVB1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) -#define NVB1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) -#define NVB1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) -#define NVB1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) -#define NVB1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) -#define NVB1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) -#define NVB1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) -#define NVB1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) -#define NVB1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) -#define NVB1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) -#define NVB1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 01_07 - */ - -#define NVB1C0_QMDV01_07_OUTER_PUT MW(30:0) -#define NVB1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) -#define NVB1C0_QMDV01_07_OUTER_GET MW(62:32) -#define NVB1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVB1C0_QMDV01_07_INNER_GET MW(94:64) -#define NVB1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) -#define NVB1C0_QMDV01_07_INNER_PUT MW(126:96) -#define NVB1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) -#define NVB1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) -#define NVB1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) -#define NVB1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) -#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) -#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_IS_QUEUE MW(200:200) -#define NVB1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) -#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVB1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) -#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVB1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) -#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) -#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_THROTTLED MW(372:372) -#define NVB1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) -#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) -#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 -#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVB1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) -#define NVB1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVB1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) -#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 -#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 -#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) -#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) -#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) -#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVB1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVB1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) -#define NVB1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) -#define NVB1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) -#define NVB1C0_QMDV01_07_QMD_VERSION MW(579:576) -#define NVB1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) -#define NVB1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) -#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) -#define NVB1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) -#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVB1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) -#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVB1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVB1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) -#define NVB1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) -#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVB1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) -#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVB1C0_QMDV01_07_SASS_VERSION MW(1535:1528) -#define NVB1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) -#define NVB1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVB1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVB1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) -#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVB1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) -#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVB1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVB1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) -#define NVB1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) -#define NVB1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) -#define NVB1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) -#define NVB1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) -#define NVB1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) -#define NVB1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) -#define NVB1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) -#define NVB1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) -#define NVB1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) -#define NVB1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) -#define NVB1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLB1C0QMD_H__ diff --git a/qmd/clc0c0qmd.h b/qmd/clc0c0qmd.h deleted file mode 100644 index 040bdcd..0000000 --- a/qmd/clc0c0qmd.h +++ /dev/null @@ -1,665 +0,0 @@ -/******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLC0C0QMD_H__ -#define __CLC0C0QMD_H__ - -/* -** Queue Meta Data, Version 01_07 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVC0C0_QMDV01_07_OUTER_PUT MW(30:0) -#define NVC0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) -#define NVC0C0_QMDV01_07_OUTER_GET MW(62:32) -#define NVC0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC0C0_QMDV01_07_INNER_GET MW(94:64) -#define NVC0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) -#define NVC0C0_QMDV01_07_INNER_PUT MW(126:96) -#define NVC0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) -#define NVC0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) -#define NVC0C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) -#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) -#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_IS_QUEUE MW(200:200) -#define NVC0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) -#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVC0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) -#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) -#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) -#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_THROTTLED MW(372:372) -#define NVC0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) -#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) -#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 -#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVC0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) -#define NVC0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) -#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 -#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 -#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) -#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) -#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) -#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVC0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVC0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) -#define NVC0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) -#define NVC0C0_QMDV01_07_QMD_VERSION MW(579:576) -#define NVC0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) -#define NVC0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) -#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) -#define NVC0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) -#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) -#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVC0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) -#define NVC0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) -#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVC0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) -#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVC0C0_QMDV01_07_SASS_VERSION MW(1535:1528) -#define NVC0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) -#define NVC0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVC0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVC0C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) -#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVC0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) -#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVC0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) -#define NVC0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) -#define NVC0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) -#define NVC0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) -#define NVC0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) -#define NVC0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) -#define NVC0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) -#define NVC0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) -#define NVC0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) -#define NVC0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) -#define NVC0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) -#define NVC0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 02_00 - */ - -#define NVC0C0_QMDV02_00_OUTER_PUT MW(30:0) -#define NVC0C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) -#define NVC0C0_QMDV02_00_OUTER_GET MW(62:32) -#define NVC0C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC0C0_QMDV02_00_INNER_GET MW(94:64) -#define NVC0C0_QMDV02_00_INNER_OVERFLOW MW(95:95) -#define NVC0C0_QMDV02_00_INNER_PUT MW(126:96) -#define NVC0C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC0C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) -#define NVC0C0_QMDV02_00_QMD_GROUP_ID MW(197:192) -#define NVC0C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) -#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) -#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_IS_QUEUE MW(200:200) -#define NVC0C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_QMD_RESERVED_B MW(223:208) -#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVC0C0_QMDV02_00_QMD_RESERVED_C MW(249:249) -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) -#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC0C0_QMDV02_00_QMD_RESERVED_D MW(335:328) -#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) -#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_THROTTLED MW(372:372) -#define NVC0C0_QMDV02_00_THROTTLED_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_THROTTLED_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC0C0_QMDV02_00_SAMPLER_INDEX MW(382:382) -#define NVC0C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC0C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) -#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) -#define NVC0C0_QMDV02_00_QMD_RESERVED13A MW(447:432) -#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) -#define NVC0C0_QMDV02_00_QMD_RESERVED14A MW(479:464) -#define NVC0C0_QMDV02_00_QMD_RESERVED15A MW(511:480) -#define NVC0C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVC0C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC0C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) -#define NVC0C0_QMDV02_00_QMD_RESERVED_G MW(575:562) -#define NVC0C0_QMDV02_00_QMD_VERSION MW(579:576) -#define NVC0C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) -#define NVC0C0_QMDV02_00_QMD_RESERVED_H MW(591:584) -#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_QMD_RESERVED_I MW(671:648) -#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC0C0_QMDV02_00_QMD_RESERVED_J MW(783:776) -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_QMDV02_00_QMD_RESERVED_K MW(791:791) -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) -#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC0C0_QMDV02_00_QMD_RESERVED_L MW(879:872) -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_QMDV02_00_QMD_RESERVED_M MW(887:887) -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) -#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC0C0_QMDV02_00_QMD_RESERVED_N MW(954:952) -#define NVC0C0_QMDV02_00_BARRIER_COUNT MW(959:955) -#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC0C0_QMDV02_00_REGISTER_COUNT MW(991:984) -#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) -#define NVC0C0_QMDV02_00_SASS_VERSION MW(1023:1016) -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC0C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) -#define NVC0C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVC0C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVC0C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) -#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVC0C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) -#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC0C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) -#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) -#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) -#define NVC0C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) -#define NVC0C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) -#define NVC0C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) -#define NVC0C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) -#define NVC0C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) -#define NVC0C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) -#define NVC0C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) -#define NVC0C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) -#define NVC0C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) -#define NVC0C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 02_01 - */ - -#define NVC0C0_QMDV02_01_OUTER_PUT MW(30:0) -#define NVC0C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) -#define NVC0C0_QMDV02_01_OUTER_GET MW(62:32) -#define NVC0C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC0C0_QMDV02_01_INNER_GET MW(94:64) -#define NVC0C0_QMDV02_01_INNER_OVERFLOW MW(95:95) -#define NVC0C0_QMDV02_01_INNER_PUT MW(126:96) -#define NVC0C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC0C0_QMDV02_01_QMD_GROUP_ID MW(133:128) -#define NVC0C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) -#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) -#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_IS_QUEUE MW(136:136) -#define NVC0C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) -#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) -#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) -#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) -#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_QMD_RESERVED_B MW(159:144) -#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVC0C0_QMDV02_01_QMD_RESERVED_C MW(185:185) -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) -#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) -#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) -#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) -#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) -#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) -#define NVC0C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) -#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC0C0_QMDV02_01_QMD_RESERVED_D MW(335:328) -#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) -#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_THROTTLED MW(372:372) -#define NVC0C0_QMDV02_01_THROTTLED_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_THROTTLED_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC0C0_QMDV02_01_SAMPLER_INDEX MW(382:382) -#define NVC0C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC0C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) -#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) -#define NVC0C0_QMDV02_01_QMD_RESERVED13A MW(447:432) -#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) -#define NVC0C0_QMDV02_01_QMD_RESERVED14A MW(479:464) -#define NVC0C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) -#define NVC0C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVC0C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC0C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) -#define NVC0C0_QMDV02_01_QMD_RESERVED_G MW(575:562) -#define NVC0C0_QMDV02_01_QMD_VERSION MW(579:576) -#define NVC0C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) -#define NVC0C0_QMDV02_01_QMD_RESERVED_H MW(591:584) -#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_QMD_RESERVED_I MW(671:648) -#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC0C0_QMDV02_01_QMD_RESERVED_J MW(783:776) -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_QMDV02_01_QMD_RESERVED_K MW(791:791) -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) -#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC0C0_QMDV02_01_QMD_RESERVED_L MW(879:872) -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_QMDV02_01_QMD_RESERVED_M MW(887:887) -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) -#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC0C0_QMDV02_01_QMD_RESERVED_N MW(954:952) -#define NVC0C0_QMDV02_01_BARRIER_COUNT MW(959:955) -#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC0C0_QMDV02_01_REGISTER_COUNT MW(991:984) -#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) -#define NVC0C0_QMDV02_01_SASS_VERSION MW(1023:1016) -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC0C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) -#define NVC0C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) -#define NVC0C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) -#define NVC0C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) -#define NVC0C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) -#define NVC0C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) -#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) -#define NVC0C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) -#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) -#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC0C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) -#define NVC0C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) -#define NVC0C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) -#define NVC0C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) -#define NVC0C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) -#define NVC0C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) -#define NVC0C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) -#define NVC0C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) -#define NVC0C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) -#define NVC0C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) -#define NVC0C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLC0C0QMD_H__ diff --git a/qmd/clc1c0qmd.h b/qmd/clc1c0qmd.h deleted file mode 100644 index 41f68a4..0000000 --- a/qmd/clc1c0qmd.h +++ /dev/null @@ -1,665 +0,0 @@ -/******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLC1C0QMD_H__ -#define __CLC1C0QMD_H__ - -/* -** Queue Meta Data, Version 01_07 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVC1C0_QMDV01_07_OUTER_PUT MW(30:0) -#define NVC1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) -#define NVC1C0_QMDV01_07_OUTER_GET MW(62:32) -#define NVC1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC1C0_QMDV01_07_INNER_GET MW(94:64) -#define NVC1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) -#define NVC1C0_QMDV01_07_INNER_PUT MW(126:96) -#define NVC1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) -#define NVC1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) -#define NVC1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) -#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) -#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_IS_QUEUE MW(200:200) -#define NVC1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) -#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVC1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) -#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) -#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) -#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_THROTTLED MW(372:372) -#define NVC1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) -#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) -#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 -#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) -#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 -#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 -#define NVC1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) -#define NVC1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) -#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 -#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 -#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) -#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) -#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) -#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) -#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) -#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) -#define NVC1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVC1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) -#define NVC1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) -#define NVC1C0_QMDV01_07_QMD_VERSION MW(579:576) -#define NVC1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) -#define NVC1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) -#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) -#define NVC1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) -#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 -#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) -#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) -#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) -#define NVC1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) -#define NVC1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) -#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) -#define NVC1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) -#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) -#define NVC1C0_QMDV01_07_SASS_VERSION MW(1535:1528) -#define NVC1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) -#define NVC1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVC1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVC1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) -#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVC1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) -#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVC1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) -#define NVC1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) -#define NVC1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) -#define NVC1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) -#define NVC1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) -#define NVC1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) -#define NVC1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) -#define NVC1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) -#define NVC1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) -#define NVC1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) -#define NVC1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) -#define NVC1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 02_00 - */ - -#define NVC1C0_QMDV02_00_OUTER_PUT MW(30:0) -#define NVC1C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) -#define NVC1C0_QMDV02_00_OUTER_GET MW(62:32) -#define NVC1C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC1C0_QMDV02_00_INNER_GET MW(94:64) -#define NVC1C0_QMDV02_00_INNER_OVERFLOW MW(95:95) -#define NVC1C0_QMDV02_00_INNER_PUT MW(126:96) -#define NVC1C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC1C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) -#define NVC1C0_QMDV02_00_QMD_GROUP_ID MW(197:192) -#define NVC1C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) -#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) -#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_IS_QUEUE MW(200:200) -#define NVC1C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) -#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) -#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) -#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) -#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_QMD_RESERVED_B MW(223:208) -#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) -#define NVC1C0_QMDV02_00_QMD_RESERVED_C MW(249:249) -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) -#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) -#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) -#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) -#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC1C0_QMDV02_00_QMD_RESERVED_D MW(335:328) -#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) -#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_THROTTLED MW(372:372) -#define NVC1C0_QMDV02_00_THROTTLED_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_THROTTLED_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC1C0_QMDV02_00_SAMPLER_INDEX MW(382:382) -#define NVC1C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC1C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) -#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) -#define NVC1C0_QMDV02_00_QMD_RESERVED13A MW(447:432) -#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) -#define NVC1C0_QMDV02_00_QMD_RESERVED14A MW(479:464) -#define NVC1C0_QMDV02_00_QMD_RESERVED15A MW(511:480) -#define NVC1C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVC1C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC1C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) -#define NVC1C0_QMDV02_00_QMD_RESERVED_G MW(575:562) -#define NVC1C0_QMDV02_00_QMD_VERSION MW(579:576) -#define NVC1C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) -#define NVC1C0_QMDV02_00_QMD_RESERVED_H MW(591:584) -#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_QMD_RESERVED_I MW(671:648) -#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC1C0_QMDV02_00_QMD_RESERVED_J MW(783:776) -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_QMDV02_00_QMD_RESERVED_K MW(791:791) -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) -#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC1C0_QMDV02_00_QMD_RESERVED_L MW(879:872) -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_QMDV02_00_QMD_RESERVED_M MW(887:887) -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) -#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC1C0_QMDV02_00_QMD_RESERVED_N MW(954:952) -#define NVC1C0_QMDV02_00_BARRIER_COUNT MW(959:955) -#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC1C0_QMDV02_00_REGISTER_COUNT MW(991:984) -#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) -#define NVC1C0_QMDV02_00_SASS_VERSION MW(1023:1016) -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC1C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) -#define NVC1C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) -#define NVC1C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) -#define NVC1C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) -#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) -#define NVC1C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) -#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) -#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC1C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) -#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) -#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) -#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) -#define NVC1C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) -#define NVC1C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) -#define NVC1C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) -#define NVC1C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) -#define NVC1C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) -#define NVC1C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) -#define NVC1C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) -#define NVC1C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) -#define NVC1C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) -#define NVC1C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 02_01 - */ - -#define NVC1C0_QMDV02_01_OUTER_PUT MW(30:0) -#define NVC1C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) -#define NVC1C0_QMDV02_01_OUTER_GET MW(62:32) -#define NVC1C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC1C0_QMDV02_01_INNER_GET MW(94:64) -#define NVC1C0_QMDV02_01_INNER_OVERFLOW MW(95:95) -#define NVC1C0_QMDV02_01_INNER_PUT MW(126:96) -#define NVC1C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC1C0_QMDV02_01_QMD_GROUP_ID MW(133:128) -#define NVC1C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) -#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) -#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_IS_QUEUE MW(136:136) -#define NVC1C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) -#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) -#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) -#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) -#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_QMD_RESERVED_B MW(159:144) -#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVC1C0_QMDV02_01_QMD_RESERVED_C MW(185:185) -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) -#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) -#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) -#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) -#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) -#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) -#define NVC1C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) -#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC1C0_QMDV02_01_QMD_RESERVED_D MW(335:328) -#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) -#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_THROTTLED MW(372:372) -#define NVC1C0_QMDV02_01_THROTTLED_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_THROTTLED_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC1C0_QMDV02_01_SAMPLER_INDEX MW(382:382) -#define NVC1C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC1C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) -#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) -#define NVC1C0_QMDV02_01_QMD_RESERVED13A MW(447:432) -#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) -#define NVC1C0_QMDV02_01_QMD_RESERVED14A MW(479:464) -#define NVC1C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) -#define NVC1C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) -#define NVC1C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC1C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) -#define NVC1C0_QMDV02_01_QMD_RESERVED_G MW(575:562) -#define NVC1C0_QMDV02_01_QMD_VERSION MW(579:576) -#define NVC1C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) -#define NVC1C0_QMDV02_01_QMD_RESERVED_H MW(591:584) -#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_QMD_RESERVED_I MW(671:648) -#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC1C0_QMDV02_01_QMD_RESERVED_J MW(783:776) -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_QMDV02_01_QMD_RESERVED_K MW(791:791) -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) -#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC1C0_QMDV02_01_QMD_RESERVED_L MW(879:872) -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_QMDV02_01_QMD_RESERVED_M MW(887:887) -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) -#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC1C0_QMDV02_01_QMD_RESERVED_N MW(954:952) -#define NVC1C0_QMDV02_01_BARRIER_COUNT MW(959:955) -#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC1C0_QMDV02_01_REGISTER_COUNT MW(991:984) -#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) -#define NVC1C0_QMDV02_01_SASS_VERSION MW(1023:1016) -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC1C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) -#define NVC1C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) -#define NVC1C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) -#define NVC1C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) -#define NVC1C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) -#define NVC1C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) -#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) -#define NVC1C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) -#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) -#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC1C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) -#define NVC1C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) -#define NVC1C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) -#define NVC1C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) -#define NVC1C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) -#define NVC1C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) -#define NVC1C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) -#define NVC1C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) -#define NVC1C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) -#define NVC1C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) -#define NVC1C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLC1C0QMD_H__ diff --git a/qmd/index.html b/qmd/index.html deleted file mode 100644 index 3258a3c..0000000 --- a/qmd/index.html +++ /dev/null @@ -1,12 +0,0 @@ - - qmd - -

qmd

- cla0c0qmd.h
- cla1c0qmd.h
- clb0c0qmd.h
- clb1c0qmd.h
- clc0c0qmd.h
- clc1c0qmd.h
- - -- cgit v1.2.3